CN102244095B - Power semiconductor device - Google Patents
Power semiconductor device Download PDFInfo
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- CN102244095B CN102244095B CN 201010178366 CN201010178366A CN102244095B CN 102244095 B CN102244095 B CN 102244095B CN 201010178366 CN201010178366 CN 201010178366 CN 201010178366 A CN201010178366 A CN 201010178366A CN 102244095 B CN102244095 B CN 102244095B
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Abstract
The invention discloses a power semiconductor device which is provided with a dummy region at the edge of an active region; UIS (unit identification system) test shows that defective pixels occur irregularity and are randomly distributed in the active region of the power semiconductor device, that is to say, the avalanche characteristic of the power semiconductor device is reinforced effectively after the dummy region is introduced.
Description
Technical field
The present invention relates to a kind of power semiconductor.Be particularly related to cellular construction and the device configuration of groove metal oxide semiconductor field effect pipe (MOSFET) and insulated trench gate electrode bipolar type transistor (IGBT).
Background technology
In the power semiconductor field, usually with the method for non-clamper inductive switch test (UIS test) come measuring element when the puncture voltage the UIS electric current so that assess the quality of the avalanche characteristic of power semiconductor.But, can find referring to figs. 1A to Fig. 1 C, after groove metal oxide semiconductor field effect pipe of the prior art (MOSFET) being carried out the UIS test, bad point always appears at the position near active area (active area) edge, thereby affect the avalanche characteristic of groove MOSFET, the below will explain in detail.
Figure 1A is the vertical view of a kind of groove MOSFET of disclosing of prior art, and Figure 1B is the cutaway view in its a-a ' cross section.Shown in Figure 1B, this groove MOSFET comprises: be formed at the N-type doped epitaxial layer 102 on N+ substrate 100; A plurality of gate grooves that are positioned at described epitaxial loayer 102, this gate groove inner surface are lined with grid oxic horizon 108 and fill with gate conduction region territory 104.In addition, described groove MOSFET also comprises: the N+ source region (source) 114 of the P type tagma (body) 112 between every two gate grooves and close this tagma upper surface.Source metal 120 contacts by formation electricity between the metal plug 105 in the body contact trench of source and described P type tagma 112 and described N+ source region 114.In the termination environment of described groove MOSFET, gate metal connecting line (gate metalrunner) 122 is positioned at 112 tops, P type tagma, simultaneously as Metal field plate (field metalplate).
After the UIS test, the bad point of device shown in Figure 1B always appears at the position near the active area edge, as shown in Fig. 1 C.This is that unlatching due to a parasitic triode causes, and the position of this parasitic triode is as shown in Fig. 2 A.With reference to Figure 1A as can be known, device cell is nearest apart from gate metal pad (gate metal pad) and gate metal connecting line, when grid bias increases to open conducting channel gradually, thereby the grid of the device cell of the most close active area marginal position at first open cause near the parasitic triode at active area edge take the lead in open, and then weakened the avalanche characteristic of semiconductor device.In addition, this makes the lower and CURRENT DISTRIBUTION wider range (referring to Fig. 3) of the UIS current value that records under the puncture voltage condition.
Same technical difficulty also exists in traditional insulated trench gate electrode bipolar type transistor (IGBT) device, as shown in Fig. 2 B.Different from the parasitic triode shown in Fig. 2 A is, in the trench IGBT device, due to the existence of P+ substrate 240, its inner phost line is thyristor, and described thyristor is comprised of a NPN and a PNP triode.
Therefore, in the power semiconductor field, especially in the Design and manufacture field of groove MOSFET and trench IGBT, need to propose a kind of cellular construction of novelty and device configuration to solve above-mentioned difficulty and design limitation.
Summary of the invention
The present invention has overcome the shortcoming that exists in the prior art, and a kind of improved power semiconductor is provided, thereby guarantees that device has good avalanche breakdown characteristic.
According to embodiments of the invention, a kind of power semiconductor is provided, comprise a plurality of groove metal oxide semiconductor field effect pipe units, each unit comprises:
(a) substrate of the first conduction type;
(b) epitaxial loayer of the first conduction type, this epitaxial loayer is positioned at the upper surface of described substrate, and the majority carrier concentration of described epitaxial loayer is lower than described substrate;
(c) a plurality of the first grooves, be positioned at active area, and extend into described epitaxial loayer from the upper surface of described epitaxial loayer;
(d) tagma of the second conduction type is positioned at the upper part of described epitaxial loayer;
(e) source region of the first conduction type, be positioned at active area, near the upper surface in described tagma, and the sidewall of close described the first groove, the majority carrier concentration in described source region is higher than described epitaxial loayer;
(f) dummy argument district is positioned at the edge of described active area, and does not have described source region in described dummy argument district;
(g) at least one second groove is positioned at described dummy argument district, extends into described epitaxial loayer from the upper surface of described epitaxial loayer, is used to form at least one dummy argument;
(h) the first insulating barrier covers the inner surface of described the first groove and the second groove;
(i) gate conduction region territory is filled in described the first groove and the second groove, and near described the first insulating barrier;
(j) the second insulating barrier, the upper surface of the described epitaxial loayer of covering;
(k) a plurality of source body contact trench, be positioned at described active area and described dummy argument district, wherein, the source body contact trench that is positioned at described active area passes described the second insulating barrier and described source region, extend down into described tagma, the source body contact trench that is positioned at described dummy argument district passes described the second insulating barrier, extends down into described tagma;
(l) metal plug is filled in the body contact trench of described source;
(m) source metal contacts with forming electricity between metal plug in the body contact trench of source, to connect described source region and tagma;
(n) gate metal connecting line;
(o) drain metal is positioned at the lower surface of described substrate.
In some preferred embodiments, described power semiconductor also comprises termination environment (termination), and described dummy argument district is positioned between described active area and described termination environment.More preferably, in some preferred embodiments, described termination environment comprises the ditch grooved ring (floatingtrench ring) of a plurality of suspensions.In other preferred embodiments, described termination environment comprises guard ring (guard ring) structure of the second conduction type, and described gate metal connecting line covers the top of guard ring described in the termination environment and described epitaxial loayer, as Metal field plate.
In some preferred embodiments, described power semiconductor is closed cellular construction (closed cell).In other preferred embodiments, described power semiconductor is banded cellular construction (stripe cell).
According to embodiments of the invention, a kind of power semiconductor is provided, comprise a plurality of insulated trench gate electrode bipolar type transistors unit, each unit comprises:
(a) substrate of the second conduction type;
(b) the first epitaxial loayer of the first conduction type, this epitaxial loayer is positioned at the upper surface of described substrate;
(c) the second epitaxial loayer of the first conduction type, this epitaxial loayer is positioned at the upper surface of described the first epitaxial loayer, and the majority carrier concentration of described the second epitaxial loayer is lower than described the first epitaxial loayer;
(d) a plurality of the first grooves, be positioned at active area, and extend into described the second epitaxial loayer from the upper surface of described the second epitaxial loayer;
(e) base of the second conduction type is positioned at the upper part of described the second epitaxial loayer;
(f) emitter region of the first conduction type, be positioned at active area, near the upper surface of described base, and the sidewall of close described the first groove, the majority carrier concentration of described emitter region is higher than described the second epitaxial loayer;
(g) dummy argument district is positioned at the edge of described active area, and does not have described emitter region in described dummy argument district;
(h) at least one second groove is positioned at described dummy argument district, extends into described the second epitaxial loayer from the upper surface of described the second epitaxial loayer, is used to form at least one dummy argument;
(i) the first insulating barrier covers the inner surface of described the first groove and the second groove;
(j) gate conduction region territory is filled in described the first groove and the second groove, and near described the first insulating barrier;
(k) the second insulating barrier covers the upper surface of described the second epitaxial loayer;
(l) a plurality of emitter regions-tagma contact trench, be positioned at described active area and described dummy argument district, wherein, be positioned at the emitter region of described active area-base contact trench and pass described the second insulating barrier and described emitter region, extend down into described base, being positioned at the emitter region in described dummy argument district-base contact trench passes described the second insulating barrier, extends down into described base;
(m) metal plug is in filling and described emitter region-base contact trench;
(n) emitter metal contacts with forming electricity between metal plug in emitter region-base contact trench, to connect described emitter region and base;
(o) gate metal connecting line;
(p) electrode metal is positioned at the lower surface of described substrate.
In some preferred embodiments, described power semiconductor is punch (Punch-Through) insulated trench gate electrode bipolar type transistor unit.In other preferred embodiments, described power semiconductor is non-punch (Non Punch-Through) insulated trench gate electrode bipolar type transistor unit.
In some preferred embodiments, described power semiconductor also comprises the termination environment, and described dummy argument district is positioned between described active area and described termination environment.More preferably, in some preferred embodiments, described termination environment comprises the ditch grooved ring of a plurality of suspensions.In other preferred embodiments, described termination environment comprises the guard ring structure of the second conduction type, and described gate metal connecting line covers the top of guard ring described in the termination environment and described epitaxial loayer, as Metal field plate.
In some preferred embodiments, described power semiconductor is closed cellular construction.In other preferred embodiments, described power semiconductor is banded cellular construction.
An advantage of the invention is, edge at active area, exist at least one not comprise that the source region is (for the insulated trench gate electrode bipolar type transistor unit, do not comprise the emitter region) the dummy argument structure, with reference to the device vertical view that has respectively closed cell structure and striped cell structure according to a preferred embodiment of the invention shown in figure 4 and Fig. 5.In the UIS test, when grid bias began to increase, owing to there not being triode parasitic shown in Fig. 2 A (for the trench IGBT unit, with reference to figure 2B) in the dummy argument structure, therefore can serve as buffer cell absorbed avalanche energy.Fig. 3 shows the comparison of prior art and UIS CURRENT DISTRIBUTION according to a preferred embodiment of the invention, and as can be seen from the figure, than prior art, it is narrower that UIS current value according to a preferred embodiment of the invention significantly increases while CURRENT DISTRIBUTION scope.Simultaneously, after UIS test, bad point random distribution but not always appear at as shown in the prior art marginal position near active area in active area, described phenomenon has strengthened the avalanche characteristic of power semiconductor.
Description of drawings
The advantage of these and other execution modes of the present invention will be by the detailed description below in conjunction with accompanying drawing, wherein:
Figure 1A is the vertical view of the groove MOSFET device of prior art announcement.
Figure 1B is that the prior art that discloses of Figure 1A is along the cutaway view in a-a ' cross section.
Fig. 1 C is the bad point position of groove metal oxide semiconductor field effect tube device after the UIS test that prior art discloses.
Fig. 2 A is the schematic diagram of parasitic triode in the groove metal oxide semiconductor field effect tube device that discloses of prior art.
Fig. 2 B is the schematic diagram of parasitic thyristor in the insulated trench gate electrode bipolar type transistor device that discloses of prior art.
Fig. 3 is prior art and UIS electric current comparison diagram according to the preferred embodiment of the invention.
Fig. 4 is the vertical view of the cellular construction with sealing according to a preferred embodiment of the invention.
Fig. 5 is the vertical view with banded cellular construction according to a preferred embodiment of the invention.
Fig. 6 is that a preferred embodiment of groove metal oxide semiconductor field effect pipe shown in Figure 4 is along the cutaway view in b-b ' cross section.
Fig. 7 is that a preferred embodiment of groove metal oxide semiconductor field effect pipe shown in Figure 4 is along the cutaway view in b-b ' cross section.
Fig. 8 is that a preferred embodiment of groove metal oxide semiconductor field effect pipe shown in Figure 4 is along the cutaway view in b-b ' cross section.
Fig. 9 is the cutaway view of insulated trench gate electrode bipolar type transistor according to a preferred embodiment of the present invention.
Figure 10 A is the vertical view of groove metal oxide semiconductor field effect pipe according to a preferred embodiment of the present invention, and wherein the gate metal connecting line is positioned at the periphery of whole device.
Figure 10 B is vertical view according to a preferred embodiment of the present invention, comprises that a plurality of gate metal connecting lines are to reduce resistance.
Figure 10 C is vertical view according to a preferred embodiment of the present invention, and comprising a plurality of Zener diodes, it is positioned at the below of gate metal pad.
Embodiment
Fig. 6 shows the N raceway groove groove metal oxide semiconductor field effect pipe that comprises dummy argument district 650 according to a preferred embodiment of the present invention, and it is also that groove metal oxide semiconductor field effect pipe shown in Figure 4 is along the cutaway view in b-b ' cross section.This N raceway groove groove metal oxide semiconductor field effect pipe is positioned on N+ substrate 600, and its upper surface is N-type epitaxial loayer 601, and lower surface is drain metal 690.This N raceway groove groove metal oxide semiconductor field effect tube device also comprises a plurality of the first grooves, and it is formed at the inside of described N-type epitaxial loayer 601, and described the first grooved inner surface is lined with grid oxic horizon 620 and the polysilicon 610 of filling to adulterate.P type tagma 602 is formed between every two the first adjacent grooves, and comprises N+ source region 603 in the interior part near P type tagma 602 upper surfaces of active area 640.Described groove metal oxide semiconductor field effect tube device also comprises source body contact trench, its inner filling with tungsten plug 612, described source body contact trench passes insulating barrier 604, extend down in described P type tagma 602 to realize described source region 603, the electricity contact between described P type tagma 602 and source metal 605.In addition, be positioned at the bottom of each described source body contact trench, exist P+ body contact zone 622 to reduce contact resistance.It should be noted that in described dummy argument district 650 and do not have described N+ source region.In the termination environment of device, gate metal connecting line 606 also as Metal field plate use, covers the upper surface of described P type tagma 602 and described epitaxial loayer 601 simultaneously.
Fig. 7 shows according to another preferred embodiment of the present invention; it has similar structure to the groove metal oxide semiconductor field effect tube device that Fig. 6 discloses, and difference is that the termination environment of N raceway groove groove metal oxide semiconductor field effect pipe shown in Figure 7 comprises the guard ring structure 718 of the second conduction type.
Fig. 8 shows according to another preferred embodiment of the present invention, it has similar structure to the groove metal oxide semiconductor field effect pipe that Fig. 6 discloses, and difference is that the termination environment of N raceway groove groove metal oxide semiconductor field effect pipe shown in Figure 8 comprises that the ditch grooved ring 819 of a plurality of suspensions and gate metal connecting line are not used as Metal field plate.
Fig. 9 shows the N raceway groove insulated trench gate electrode bipolar type transistor that comprises dummy argument district 950 according to a preferred embodiment of the present invention.This N raceway groove insulated trench gate electrode bipolar type transistor is positioned on P+ substrate 900, and its upper surface is followed successively by N+ the first epitaxial loayer 900 ' and N-type the second epitaxial loayer 901, and lower surface is collector electrode metal 990.This N raceway groove insulated trench gate electrode bipolar type transistor device also comprises a plurality of the first grooves, and it is formed at the inside of described N-type the second epitaxial loayer 901, and described the first grooved inner surface is lined with grid oxic horizon 920 and the polysilicon 910 of filling to adulterate.P type base 902 is formed between every two the first adjacent grooves, and comprises N+ emitter region 903 in the interior part near P type base 902 upper surfaces of active area 940.Described N raceway groove insulated trench gate electrode bipolar type transistor device also comprises emitter region-base contact trench, its inner filling with tungsten plug 912, described emitter region-base contact trench passes insulating barrier 904, extend down in described P type base 902 to realize described emitter region 903, the electricity contact between described P type base 902 and emitter metal 905.In addition, be positioned at the bottom of each described emitter region-base contact trench, exist P+ base stage contact zone 922 to reduce contact resistance.It should be noted that in described dummy argument district 950 and do not have described N+ source region.The termination environment of device comprises P type guard ring 917 and 918, and simultaneously, gate metal connecting line 906 also as Metal field plate, covers the upper surface of described P type base 902 and described the second epitaxial loayer 901 simultaneously.
Figure 10 A shows the vertical view of groove metal oxide semiconductor field effect pipe according to a further advantageous embodiment of the invention, shown in figure after UIS test the position of bad point, and the prior art difference is in preferred structure of the present invention that bad point is random in active area and occurs but not appear near near the edge of active area, thereby strengthened the avalanche characteristic of groove MOSFET.
Figure 10 B shows the vertical view of groove metal oxide semiconductor field effect pipe according to a further advantageous embodiment of the invention, the position in dummy argument shown in figure district, and comprise that a plurality of gate metal connecting lines are to reduce resistance.
Figure 10 C shows the vertical view of groove metal oxide semiconductor field effect pipe according to a further advantageous embodiment of the invention, there is shown the position in dummy argument district, and exists a plurality of Zener diodes to carry out esd protection below the gate metal pad.
Although at this, various embodiment have been described, are appreciated that without departing from the spirit and scope of the present invention and can make various modifications to the present invention.For example, can form with method of the present invention the structure of its conduction type and the various semiconductor regions of opposite conduction type described in literary composition, but the modification of having done should be forgiven within the scope of protection of present invention.
Claims (24)
1. a power semiconductor, comprise a plurality of groove metal oxide semiconductor field effect pipe units, and each unit comprises:
The substrate of the first conduction type;
The epitaxial loayer of the first conduction type, this epitaxial loayer is positioned at the upper surface of described substrate, and the majority carrier concentration of described epitaxial loayer is lower than described substrate;
A plurality of the first grooves are positioned at active area, and extend into described epitaxial loayer from the upper surface of described epitaxial loayer;
The tagma of the second conduction type is positioned at the upper part of described epitaxial loayer;
The source region of the first conduction type is positioned at active area, near the upper surface in described tagma, and the sidewall of close described the first groove, the majority carrier concentration in described source region is higher than described epitaxial loayer;
The dummy argument district is positioned at the edge of described active area, and there is not described source region in described dummy argument in the district;
At least one second groove is positioned at described dummy argument district, extends into described epitaxial loayer from the upper surface of described epitaxial loayer, is used to form at least one dummy argument;
The first insulating barrier covers the inner surface of described the first groove and the second groove;
The gate conduction region territory is filled in described the first groove and the second groove, and near described the first insulating barrier;
The second insulating barrier, the upper surface of the described epitaxial loayer of covering;
A plurality of sources body contact trench, be positioned at described active area and described dummy argument district, wherein, the source body contact trench that is positioned at described active area passes described the second insulating barrier and described source region, extend down into described tagma, the source body contact trench that is positioned at described dummy argument district passes described the second insulating barrier, extends down into described tagma;
Metal plug is filled in the body contact trench of described source;
Source metal contacts with forming electricity between metal plug in the body contact trench of source, to connect described source region and tagma;
The gate metal connecting line;
Drain metal is positioned at the lower surface of described substrate.
2. power semiconductor according to claim 1, also comprise the termination environment, and described dummy argument district is positioned between described active area and described termination environment.
3. power semiconductor according to claim 2, wherein said gate metal connecting line cover the top in tagma and epitaxial loayer in described termination environment, as Metal field plate.
4. power semiconductor according to claim 2, wherein said termination environment comprises the ditch grooved ring of a plurality of suspensions.
5. power semiconductor according to claim 2, wherein said termination environment comprises the guard ring structure of the second conduction type, and described gate metal connecting line covers the top of guard ring described in the termination environment and described epitaxial loayer, as Metal field plate.
6. power semiconductor according to claim 1, wherein said groove metal oxide semiconductor field effect pipe unit are closed cellular construction.
7. power semiconductor according to claim 1, wherein said groove metal oxide semiconductor field effect pipe unit are banded cellular construction.
8. power semiconductor according to claim 1, wherein said gate metal connecting line comprise that a plurality of gate metal connecting lines are to reduce resistance.
9. power semiconductor according to claim 1, also comprise the gate metal pad, and be positioned at the below of gate metal pad, has Zener diode.
10. power semiconductor according to claim 1, wherein said the first conduction type is N-type, described the second conduction type is the P type.
11. power semiconductor according to claim 1 also comprises the body contact zone of the second conduction type, it is positioned at described tagma, and surrounds at least the bottom of described source body contact trench, and the majority carrier concentration of described body contact zone is higher than described tagma.
12. a power semiconductor comprises a plurality of insulated trench gate electrode bipolar type transistors unit, each unit comprises:
The substrate of the second conduction type;
The first epitaxial loayer of the first conduction type, this epitaxial loayer is positioned at the upper surface of described substrate;
The second epitaxial loayer of the first conduction type, this epitaxial loayer is positioned at the upper surface of described the first epitaxial loayer, and the majority carrier concentration of described the second epitaxial loayer is lower than described the first epitaxial loayer;
A plurality of the first grooves are positioned at active area, and extend into described the second epitaxial loayer from the upper surface of described the second epitaxial loayer;
The base of the second conduction type is positioned at the upper part of described the second epitaxial loayer;
The emitter region of the first conduction type is positioned at active area, near the upper surface of described base, and the sidewall of close described the first groove, the majority carrier concentration of described emitter region is higher than described the second epitaxial loayer;
The dummy argument district is positioned at the edge of described active area, and there is not described emitter region in described dummy argument in the district;
At least one second groove is positioned at described dummy argument district, extends into described the second epitaxial loayer from the upper surface of described the second epitaxial loayer, is used to form at least one dummy argument;
The first insulating barrier covers the inner surface of described the first groove and the second groove;
The gate conduction region territory is filled in described the first groove and the second groove, and near described the first insulating barrier;
The second insulating barrier covers the upper surface of described the second epitaxial loayer;
Base, a plurality of emitter region contact trench, be positioned at described active area and described dummy argument district, wherein, base, the emitter region contact trench that is positioned at described active area passes described the second insulating barrier and described emitter region, extend down into described base, being positioned at the emitter region in described dummy argument district-base contact trench passes described the second insulating barrier, extends down into described base;
Metal plug is filled in described emitter region-base contact trench;
Emitter metal contacts with forming electricity between metal plug in emitter region-base contact trench, to connect described emitter region and base;
The gate metal connecting line;
Collector electrode metal is positioned at the lower surface of described substrate.
13. power semiconductor according to claim 12, wherein said insulated trench gate electrode bipolar type transistor are the punch insulated trench gate electrode bipolar type transistor.
14. power semiconductor according to claim 12, wherein said insulated trench gate electrode bipolar type transistor are non-punch insulated trench gate electrode bipolar type transistor.
15. power semiconductor according to claim 12 also comprises the termination environment, described dummy argument district is positioned between described active area and described termination environment.
16. power semiconductor according to claim 15, wherein said gate metal connecting line cover the top in tagma and epitaxial loayer in described termination environment, as Metal field plate.
17. power semiconductor according to claim 15, wherein said termination environment comprise the ditch grooved ring of a plurality of suspensions.
18. power semiconductor according to claim 15, wherein said termination environment comprise the guard ring structure of the second conduction type, and described gate metal connecting line covers the top of guard ring described in the termination environment and described epitaxial loayer, as Metal field plate.
19. power semiconductor according to claim 12, wherein said insulated trench gate electrode bipolar type transistor unit are closed cellular construction.
20. power semiconductor according to claim 12, wherein said insulated trench gate electrode bipolar type transistor unit are banded cellular construction.
21. power semiconductor according to claim 12, wherein said gate metal connecting line comprises a plurality of gate metal connecting lines, to reduce resistance.
22. power semiconductor according to claim 12 also comprises the gate metal pad, and is positioned at the below of gate metal pad, has Zener diode.
23. power semiconductor according to claim 12, wherein said the first conduction type is N-type, and described the second conduction type is the P type.
24. power semiconductor according to claim 12, the contact zone, base that also comprises the second conduction type, it is positioned at described base, and surrounds at least the bottom of described emitter region-base contact trench, and the majority carrier concentration of contact zone, described base is higher than described base.
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| CN102569373B (en) * | 2012-03-08 | 2014-08-13 | 无锡新洁能股份有限公司 | Insulated gate bipolar transistor (IGBT) with low-conductivity saturation voltage drop and manufacturing method for IGBT |
| JP6284314B2 (en) | 2012-08-21 | 2018-02-28 | ローム株式会社 | Semiconductor device |
| JP6577558B2 (en) * | 2012-08-21 | 2019-09-18 | ローム株式会社 | Semiconductor device |
| CN102956638B (en) * | 2012-11-13 | 2015-04-15 | 清华大学 | One-piece IGBT (Insulated Gate Bipolar Translator) device and processing method thereof |
| CN104347708A (en) * | 2013-08-07 | 2015-02-11 | 中芯国际集成电路制造(北京)有限公司 | Multi-grid VDMOS (vertical double-diffused metal oxide semiconductor) transistor and forming method thereof |
| JP5795452B1 (en) * | 2014-09-24 | 2015-10-14 | 新電元工業株式会社 | Silicon carbide semiconductor device, method for manufacturing silicon carbide semiconductor device, and method for designing silicon carbide semiconductor device |
| JP6514519B2 (en) * | 2015-02-16 | 2019-05-15 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
| CN107798150B (en) * | 2016-08-31 | 2021-07-23 | 复旦大学 | Dummy filling method based on unified framework of sequence quadratic programming method |
| US20210202470A1 (en) * | 2019-12-31 | 2021-07-01 | Nami MOS CO., LTD. | Mosfet with integrated esd protection diode having anode electrode connection to trenched gates for increasing switch speed |
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| JP4824296B2 (en) * | 2004-11-04 | 2011-11-30 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| US7629646B2 (en) * | 2006-08-16 | 2009-12-08 | Force Mos Technology Co., Ltd. | Trench MOSFET with terraced gate and manufacturing method thereof |
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| CN1695252A (en) * | 2001-11-21 | 2005-11-09 | 通用半导体公司 | Trench MOSFET device with improved on-resistance |
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