CN102185301A - Static discharge ESD protective circuit - Google Patents

Abstract

The invention discloses an electrostatic discharge ESD protection circuit, which includes an electrostatic discharge branch circuit with one or more MOS transistors, and a gate trigger signal generation circuit for generating a gate trigger signal, and the gate trigger signal is connected to To the gate of at least one MOS transistor; the substrate trigger signal generating circuit is used to generate a substrate trigger signal, and the substrate trigger signal is connected to the substrate of the at least one MOS transistor; wherein, the substrate trigger signal The response time is not less than the rise time of the electrostatic discharge voltage or not less than 20ns. The protection ability of the electrostatic discharge protection circuit is improved, and the possibility of leakage current caused by false triggering is reduced.

Description

Electrostatic discharge ESD protection circuit

technical field

The invention relates to an electrostatic discharge ESD protection circuit.

Background technique

When two non-conductive objects contact and separate, it is possible to cause the transfer of electrons between the two objects, causing the two non-conductive objects to generate additional charges, which are static electricity. Electro-Static Discharge (ESD) occurs when the static electricity accumulated on an object discharges an object with a relatively low potential.

With the development of semiconductor technology, the problem of electrostatic discharge (ESD) is becoming more and more serious in integrated circuits. Designers have developed a variety of electrostatic discharge ESD protection circuits from the process level, device level, circuit level and system level of integrated circuits. Among them, the electrostatic discharge ESD protection circuit based on field effect transistor MOS is widely used because of its easy implementation and good protection ability.

In the electrostatic discharge ESD protection circuit based on the field effect transistor MOS, in order to improve the area utilization rate of the MOS transistor and reduce the gate resistance, an interdigitated structure is generally adopted. In the interdigitated structure, when each interdigit conducts current evenly, the ability of the MOS tube to withstand the current is the largest, and the electrostatic discharge protection ability is the strongest. However, the actual situation is that only a small part of the interdigitated structure can be turned on during electrostatic discharge, and even if it is turned on, it is only partially turned on in the direction of the channel width W.

In order to improve the conduction ability of the MOS tube in the electrostatic discharge ESD protection circuit, that is to increase the protection ability of the electrostatic discharge ESD protection circuit. The above purpose can be effectively achieved by utilizing the gate bias effect or the substrate bias effect, and the effect of the substrate bias effect will be better.

Among them, using the gate bias effect to improve the conduction capability of the MOS tube refers to applying a certain voltage on the gate of the MOS tube to reduce the trigger voltage of the gate of the MOS tube so that the MOS tube works in the sub-valve region. or saturation zone. Since the trigger voltage of the MOS tube is reduced, the MOS tube can quickly respond to electrostatic discharge. At the same time, the secondary breakdown current value of the MOS tube is increased, and the electrostatic discharge protection capability is enhanced. The disadvantage of this method is that since the MOS tube has a surface current concentration effect, when there is a gate voltage, the surface of the MOS tube will inevitably generate a certain amount of thermal power consumption. If the gate voltage continues to exist, the temperature on the surface of the MOS tube will gradually increase, which may damage or destroy the MOS tube.

Improving the conduction capability of the MOS transistor by using the substrate bias refers to applying a certain bias voltage on the substrate of the MOS transistor to make the PN junction between the substrate and the source positively biased and increase the secondary breakdown current of the MOS transistor. value. In the parasitic NPN element, the PN junction between the forward-biased substrate and the source (that is, the emitter junction of the forward-biased parasitic NPN element) can make the NPN element work in the amplification area, conduct a large amount of current, and improve the electrostatic discharge circuit. protection ability. The substrate bias effect will generate a leakage current, which is the key to increasing the electrostatic discharge current during the normal electrostatic discharge ESD process. However, when the substrate bias effect is not triggered by normal static electricity, but is caused by some interference (such as interference pulse), then this leakage current will have an impact on the circuit. Therefore, when the substrate bias effect is used to improve the protection capability of the electrostatic discharge protection circuit, leakage current may be generated due to false triggering.

Contents of the invention

The main technical problem to be solved by the present invention is to provide an electrostatic discharge ESD protection circuit, which can reduce the possibility of leakage current caused by false triggering while improving the electrostatic discharge protection capability. In order to solve the above technical problems, the present invention provides an electrostatic discharge ESD protection circuit, including an electrostatic discharge branch circuit with one or more MOS tubes, and also includes:

A gate trigger signal generating circuit, configured to generate a gate trigger signal, the output terminal of the gate trigger signal generating circuit is connected to the gate of at least one MOS transistor;

A substrate trigger signal generation circuit, configured to generate a substrate trigger signal, the output end of the substrate trigger signal generation circuit is connected to the substrate of the at least one MOS transistor;

Wherein, the response time of the substrate trigger signal is not less than the rise time of the electrostatic discharge voltage; or the response time of the substrate trigger signal is not less than 20 ns.

In one embodiment, the electrostatic discharge branch circuit includes: an NMOS transistor; the NMOS transistor includes a gate, a first electrode, a second electrode and a substrate, and the gate is connected to the gate to trigger signal generation The output terminal of the circuit, the first electrode is connected to the power supply, the second electrode is connected to the ground, and the substrate is connected to the output terminal of the substrate trigger signal generating circuit;

The gate trigger signal generation circuit includes: a first detection circuit and an inverting circuit;

The first detection circuit includes: a first resistance element and a first capacitance element; one end of the first resistance element is connected to a power supply, and one end of the first capacitance element is connected to the other end of the first resistance element One end, the other end of the first capacitive element is connected to ground;

The inverter circuit is formed by cascading an odd number of inverters, including an input end and an output end, the input end is connected between the first resistance element and the first capacitance element, and the output end is the The output terminal of the gate trigger signal generating circuit outputs the gate trigger signal and is connected to the gate of the NMOS transistor.

Further, the time constant of the first resistive element and the first capacitive element of the first detection circuit is a first time constant, and the first time constant is longer than the rise time of the electrostatic discharge voltage and shorter than the duration of the electrostatic discharge voltage.

In one implementation manner, the substrate trigger signal generation circuit includes: a second detection circuit, a buffer, a third detection circuit, and a logic gate;

The second detection circuit includes: a second resistance element and a second capacitance element, one end of the second resistance element is connected to a power supply, and one end of the second capacitance element is connected to the other end of the first resistance element one end, the other end of the second capacitive element is connected to ground;

The buffer includes: an input terminal and an output terminal, the input terminal is connected between the second resistance element and the second capacitance element of the second detection circuit;

The third detection circuit includes: a third resistance element and a third capacitance element, one end of the third resistance element is connected to the output end of the buffer, and one end of the third capacitance element is connected to the The other end of the third resistive element, the other end of the third capacitive element is connected to ground;

The logic gate is an XOR logic gate, including two input terminals and an output terminal, wherein one input terminal is connected between the second resistance element and the second capacitance element of the second detection circuit, and the other input terminal is connected to the third Between the third resistive element and the third capacitive element of the detection circuit; the output end is the output end of the substrate trigger signal generating circuit, which is used to output the substrate trigger signal and is connected to the substrate of the NMOS transistor .

Further, the time constant of the second resistance element and the second capacitance element of the second detection circuit is the second time constant, and the time constant of the third resistance element and the third capacitance element of the third detection circuit is the third time constant. time constant;

The third time constant is greater than the duration of the electrostatic discharge voltage; the second time constant is greater than or equal to the rise time of the electrostatic discharge voltage, but less than the third time constant.

In another embodiment, the electrostatic discharge branch circuit includes: a PMOS transistor; the PMOS transistor includes a gate, a first electrode, a second electrode and a substrate, and the gate is connected to a gate trigger signal generating circuit The output end of the first electrode is connected to the ground, the second electrode is connected to the power supply, and the substrate is connected to the output end of the substrate trigger signal generating circuit;

The gate trigger signal generation circuit includes: a first detection circuit;

The first detection circuit includes: a first resistance element and a first capacitance element; one end of the first resistance element is connected to a power supply, and one end of the first capacitance element is connected to the other end of the first resistance element One end, the other end of the first capacitive element is connected to ground;

The substrate of the PMOS transistor is connected between the first resistance element and the first capacitance element.

In another embodiment, the electrostatic discharge branch circuit includes: a PMOS element; the PMOS element includes a gate, a first electrode, a second electrode and a substrate, and the gate is connected to a gate trigger signal generating circuit The output end of the first electrode is connected to the ground, the second electrode is connected to the power supply, and the substrate is connected to the output end of the substrate trigger signal generating circuit;

The gate trigger signal generation circuit includes: a first detection circuit and a non-inverting circuit;

The first detection circuit includes: a first resistance element and a first capacitance element; one end of the first resistance element is connected to a power supply, and one end of the first capacitance element is connected to the other end of the first resistance element One end, the other end of the first capacitive element is connected to ground;

The non-inverting circuit is formed by cascading an even number of inverters, including an input terminal and an output terminal, the input terminal of the non-inverting circuit is connected between the first resistive element and the first capacitive element, and the output terminal is the The output end of the gate trigger signal generating circuit is connected to the gate of the PMOS transistor.

Further, the time constant of the first resistive element and the first capacitive element of the first detection circuit is a first time constant, and the first time constant is longer than the rise time of the electrostatic discharge voltage and shorter than the duration of the electrostatic discharge voltage.

In another implementation manner, the substrate trigger signal generation circuit includes: a second detection circuit, a buffer, a third detection circuit, a logic gate, and an inverting circuit;

The second detection circuit includes: a second resistance element and a second capacitance element, one end of the second resistance element is connected to a power supply, and one end of the second capacitance element is connected to the other end of the second resistance element one end, the other end of the second capacitive element is connected to ground;

The buffer includes: an input terminal and an output terminal, the input terminal is connected between the second resistance element and the second capacitance element of the second detection circuit;

The third detection circuit includes: a third resistance element and a third capacitance element, one end of the third resistance element is connected to the output end of the buffer, and one end of the third capacitance element is connected to the The other end of the third resistive element, the other end of the third capacitive element is connected to ground;

The logic gate is an XOR logic gate, including two input terminals and an output terminal, wherein one input terminal is connected between the second resistance element and the second capacitance element of the second detection circuit, and the other input terminal is connected to the third Between the third resistance element and the third capacitance element of the detection circuit;

The inverting circuit is formed by cascading an odd number of inverters, including an input terminal and an output terminal, the input terminal of the inverting circuit is connected to the output terminal of the logic gate, and the output terminal of the inverting circuit is the substrate The output terminal of the trigger signal generating circuit is connected to the substrate of the PMOS transistor.

Further, the time constant of the second resistance element and the second capacitance element of the second detection circuit is the second time constant, and the time constant of the third resistance element and the third capacitance element of the third detection circuit is the third time constant. time constant;

The third time constant is greater than the duration of the electrostatic discharge voltage; the second time constant is greater than the rise time of the electrostatic discharge voltage but less than the third time constant.

The beneficial effects of the present invention are: after the gate trigger signal generated by the grid trigger signal generation circuit is added to the gate of the MOS element, the trigger voltage of the MOS element is reduced, which improves the discharge capacity of the electrostatic discharge ESD protection circuit; the substrate trigger After the substrate trigger signal generated by the signal is added to the substrate of the MOS element, the substrate bias effect occurs on the MOS element, which enhances the current conduction capability of the MOS element and improves the discharge capability of the electrostatic discharge protection circuit. At the same time, since the response time of the substrate trigger signal is greater than or equal to the rise time of the electrostatic discharge voltage (about 10 ns), the duration of the falsely triggered pulse is usually not longer than the normal rise time of the electrostatic discharge voltage, so even if a false trigger, the substrate trigger signal will not act on the substrate, thereby reducing the possibility of leakage current under abnormal conditions. When the response time of the substrate trigger signal is set to not less than 20 ns, it is to keep a certain design margin, which is in line with the design idea of the circuit and can achieve better results.

Description of drawings

Fig. 1 is an overall diagram of an electrostatic discharge ESD protection circuit of an embodiment of the present invention;

FIG. 2 is a circuit diagram for generating a gate trigger signal according to an embodiment of the present invention;

3 is a circuit diagram of a gate trigger signal generation circuit in another embodiment of the present invention;

4 is a circuit diagram of a substrate trigger signal generation circuit in an embodiment of the present invention;

5 is a specific structural diagram of a substrate trigger signal generating circuit according to an embodiment of the present invention;

FIG. 6 is a gate trigger signal generation circuit in another embodiment of the present invention;

FIG. 7 is a substrate trigger signal generation circuit in another embodiment of the present invention;

FIG. 8 is a schematic diagram of waveforms of the A signal and the gate trigger signal in FIG. 3;

FIG. 9 is a schematic diagram of the waveforms of the B signal, the C signal, the D signal, the E signal and the substrate trigger signal in 5.

Detailed ways

The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings.

Example 1:

Please refer to FIG. 1 , an electrostatic discharge ESD protection circuit includes an electrostatic discharge branch 30 , a gate trigger signal generation circuit 10 and a substrate trigger signal generation circuit 20 .

Wherein, the electrostatic discharge branch 30 includes one or more MOS transistors, and the types of these MOS transistors may be NMOS transistors or PMOS transistors. When the electrostatic discharge branch 30 includes a plurality of MOS transistors, these MOS transistors form an electrostatic discharge branch in series, in parallel, or in series and parallel. The electrostatic discharge branch 30 includes two external input terminals, which are respectively used to connect to the power supply VCC and the ground VSS, or to connect to the external pad PAD and the ground VSS, and are used to pass the static electricity generated by the power supply VCC or the pad PAD through the static electricity. The discharge branch 30 transmits to the ground to realize discharge. Preferably, the electrostatic discharge branch 30 includes an NMOS transistor or a PMOS transistor.

The gate trigger signal generation circuit 10 is used to generate a gate trigger signal and apply the gate trigger signal to the gate of the MOS transistor. When the electrostatic discharge branch 30 includes only one MOS tube, the gate trigger signal is applied to the grid of the MOS tube; when the electrostatic discharge branch 30 includes multiple MOS tubes, the gate trigger signal is applied to the multiple MOS tubes one or part or all of them. The gate trigger signal is applied to the gate of the MOS tube, which can reduce the gate trigger voltage of the MOS tube, so that the MOS tube can discharge the static electricity as soon as possible, and increase the secondary breakdown current value of the MOS tube.

The substrate trigger signal generating circuit 20 is used to generate a substrate trigger signal and apply the substrate trigger signal to the substrate of the MOS transistor. When the electrostatic discharge branch 30 only includes one MOS tube, the substrate trigger signal is applied to the substrate of the MOS tube; when the electrostatic discharge branch includes multiple MOS tubes, the substrate trigger signal is applied to the substrate of the multiple MOS tubes One or some or all of them. The substrate trigger signal is applied to the substrate of the MOS transistor, so that the substrate bias effect occurs in the MOS transistor, the secondary breakdown current value of the MOS transistor is increased, and the current conduction capability of the MOS transistor is enhanced.

Preferably, the gate trigger signal and the substrate trigger signal are applied to the same one or more MOS transistors.

In the above, there is a time difference between the gate trigger signal and the substrate trigger signal, and the response time of the substrate trigger signal is greater than or equal to the rise time of the electrostatic discharge voltage, or greater than or equal to 20 ns.

Specifically, in a discharge cycle, the gate trigger signal is applied to the gate of the MOS transistor from the beginning of the electrostatic discharge cycle, so that the gate bias effect of the MOS transistor occurs, reducing the gate trigger voltage. Moreover, the duration of the gate trigger signal acting on the MOS tube is longer than the rise time of the electrostatic discharge ESD voltage, and shorter than the duration of the electrostatic discharge ESD voltage, that is, in one electrostatic discharge cycle, the gate trigger signal does not always make the gate of the MOS tube gate bias effect occurs.

The substrate trigger signal has a response time, so that the time point when it starts to act on the MOS transistor substrate is later than the rise time of the electrostatic discharge ESD voltage, but lasts until the electrostatic discharge ends. The substrate trigger signal causes a bias effect on the substrate to improve the current conduction capability of the MOS transistor.

In an electrostatic discharge cycle, the gate trigger signal acts on the gate of the MOS transistor as soon as the electrostatic discharge event occurs, causing the gate bias effect of the MOS transistor to increase the conduction current of the MOS transistor. At the same time, the effect of the gate trigger signal ends before the electrostatic discharge is completed, which reduces the influence of the surface current concentration effect on the MOS tube. The main impact is that when there is a bias voltage on the gate and the current conduction of the MOS tube, if the gate voltage continues to exist, the surface temperature of the MOS tube will become higher and higher due to the surface current concentration effect of the MOS tube. The increased temperature may damage or damage the MOS tube.

The time point when the substrate trigger signal starts to act on the MOS transistor substrate is later than the rise time of the electrostatic discharge ESD voltage, so even if a false trigger occurs, no leakage current will be generated. Because, usually, the false trigger time is very short, less than the rise time of the electrostatic discharge ESD voltage, so the substrate trigger signal will not react to the false trigger, and no leakage current will be generated. And in this way, the response time of the substrate trigger signal can be reasonably designed according to the possible time of false triggering in the actual circuit, so as to better avoid the generation of leakage current caused by false triggering.

Example 2:

On the basis of Embodiment 1, the electrostatic discharge protection circuit when the electrostatic discharge branch circuit includes an NMOS transistor is described with reference to FIGS. 2 to 5 .

The electrostatic discharge branch circuit includes: an NMOS tube. The NMOS transistor includes a gate, a first electrode, a second electrode and a substrate. Wherein, the gate is connected to the output end of the gate trigger signal generating circuit, and the output end of the gate trigger signal generating circuit is used to output the gate trigger signal; the first electrode is a drain and is connected to a power supply; the second electrode is a source , connected to ground; the substrate is connected to the output terminal of the substrate trigger signal generating circuit, and the output terminal of the substrate trigger signal generating circuit is used to output the substrate trigger signal.

As shown in FIG. 2 , the gate trigger signal generation circuit includes: a first detection circuit 101 and an inverting circuit 102 .

Wherein, the first detection circuit 101 includes: a first resistance element and a first capacitance element. The first resistive element is formed by one or more resistors connected in series or in parallel or series-parallel, and the first capacitive element is also formed by one or more capacitors connected in series or in parallel or in series-parallel. Or the first resistance element is realized by other forms, and the first resistance element is realized by other forms. Preferably, as shown in FIG. 3 , the first resistive element is a resistor R1, and the first capacitive element is a capacitor C1.

One end of the first resistance element is connected to the power supply VCC, one end of the first capacitance element is connected to the other end of the first resistance element, and the other end of the first capacitance element is connected to the ground VSS.

The inverter circuit 102 is formed by cascading an odd number of inverters, including an input end and an output end, the input end is connected between the first resistance element and the first capacitance element, and the output end outputs a gate trigger signal, which is connected to the NMOS transistor the grid. Preferably, as shown in FIG. 3 , the inverter circuit 102 includes an inverter, and the inverter is composed of an NMOS transistor and a PMOS transistor connected in series. Among them, the gates of the NMOS transistor and the PMOS transistor are connected between the resistor R1 and the capacitor C1, the source and the substrate of the NMOS transistor are connected to the ground VSS, the drain of the NMOS transistor is connected to the drain of the PMOS transistor and output the gate The trigger signal, the source and substrate of the PMOS transistor are connected to the power supply VCC.

As shown in FIG. 4, the substrate trigger signal generation circuit 20 includes: a second detection circuit 201, a buffer 203, a third detection circuit 202 and a logic gate 204;

Wherein, the second detection circuit 201 includes: a second resistance element and a second capacitance element, and the third detection circuit 202 includes: a third resistance element and a third capacitance element. The second resistive element and the third resistive element are formed by one or more resistors connected in series or in parallel or series-parallel, and the second capacitive element and the third capacitive element are formed by one or more capacitors connected in series or in parallel or in series-parallel. Preferably, as shown in FIG. 5, the second resistive element of the second detection circuit 201 is a resistor R2, and the second capacitive element is a capacitor C2; the third resistive element of the third detection circuit 202 is a resistor R3, and the third The capacitive element is a capacitor C3.

In the second detection circuit 201 , one end of the second resistive element is connected to the power supply VCC, one end of the second capacitive element is connected to the other end of the second resistive element, and the other end of the second capacitive element is connected to the ground VSS.

The buffer 203 includes: an input terminal and an output terminal, the input terminal is connected between the second resistance element and the second capacitance element of the second detection circuit 201 . Preferably, as shown in FIG. 5, the buffer 203 is formed by cascading two inverters. It can be understood that the buffer 203 may be formed by cascading an even number of inverters, or other forms of buffers may be used. .

In the third detection circuit 202, one end of the third resistive element is connected to the output end of the buffer, one end of the third capacitive element is connected to the other end of the third resistive element, and the other end of the third capacitive element is connected to the ground VSS.

The logic gate 204 adopts an XOR logic gate and includes two input terminals and an output terminal, wherein one input terminal is connected between the second resistance element and the second capacitance element of the second detection circuit, and the other input terminal is connected to the third detection circuit. Between the third resistive element and the third capacitive element of the circuit; the output end is used to output the substrate trigger signal, and is connected to the substrate of the NMOS.

In the above, the time constant of the second resistive element and the first capacitive element of the first detection circuit is the first time constant, the time constant of the second resistive element and the second capacitive element of the second detection circuit is the second time constant, the second The time constant of the third resistance element and the third capacitance element of the three detection circuits is a third time constant.

The first time constant is greater than the rise time of the electrostatic discharge voltage (about less than 10ns), and less than the duration of the electrostatic discharge voltage (about 100-1000ns); the third time constant is greater than the duration of the electrostatic discharge voltage; the second time constant is not less than The rise time of the electrostatic discharge voltage is less than the third time constant, and the second time constant is the response time of the substrate trigger signal. At this time, the second time constant is the response time of the substrate trigger signal, and the electrostatic discharge must last for such a long time as the second time constant before the substrate trigger signal causes the substrate of the NMOS transistor to have a substrate bias effect.

Preferably, the gate trigger signal generation circuit 10 and the substrate trigger signal generation circuit 20 respectively have the specific structures shown in FIG. 3 and FIG. 5 as an example below. The function of the tube is explained:

When an electrostatic discharge ESD event occurs between the power supply VCC and the ground VSS, the capacitor C1 in FIG. The waveforms of gate trigger signal Gate, signal A and gate trigger signal Gate are shown in FIG. 8 . It can be seen from FIG. 8 that just before the ESD event occurs, the gate trigger signal Gate has acted on the gate of the NMOS transistor, so that the NMOS transistor works in the saturation region or the linear region, reducing the gate trigger voltage. When an ESD event occurs, since the voltage value across the capacitor C1 cannot change suddenly, the gate trigger signal is still at a high level. After 2.2 times the first time constant, the gate trigger signal Gate drops to 0, and the gate trigger signal Bias effects no longer work. The first time constant is determined by R1 and C1, and its value is 1/R1*C1.

During the electrostatic discharge process, the waveform diagrams of the output signal B of the second detection circuit 201 , the output signal D of the buffer 203 , the output signal E of the third detection circuit 202 and the substrate trigger signal Substrate in FIG. 5 are shown in FIG. 9 . It can be seen from the figure that the substrate trigger signal Substrate is formed by the exclusive OR of the output signal B of the second detection circuit 201 and the output signal E of the third detection circuit 202 . Therefore, when an ESD event occurs, since the output signal B is at a low level, the output signal E is at a high level, and the substrate trigger signal Substrate is at a low level, the substrate bias effect cannot occur on the NMOS transistor. When the ESD event occurs after the second time constant of 2.2 times, the output signal B becomes high level, the output signal E is also high level, and the substrate trigger signal Substrate is high level, so that the substrate is biased effect. When the ESD event passes through the third time constant of 2.2 times, the output signal E becomes low level, and the substrate trigger signal Substrate becomes high level, ending the effect on the substrate. The value of the second time constant is 1/R2*C2, and the value of the third time constant is 1/R3*C3. Since the ESD event must last for 2.2 times the second time constant, the substrate trigger signal Substrate can act on the substrate, causing the substrate bias effect to occur, resulting in leakage current, and improving the discharge capability of the MOS tube. In practice, due to false triggering The time is less than 2.2 times the second time constant (the second time constant is greater than or equal to the rise time of the ESD voltage), so false triggering will not generate leakage current.

In the above, the action time of the gate trigger signal is limited to 0~2.2/R1*C1, and the action time of the substrate trigger signal is limited to 2.2/R2*C2~2.2/R3*C3 in order to retain a certain design margin. Quantity, in line with the requirements of the actual design, can also achieve better results.

In the above, the reaction time of the substrate trigger signal is 2.2 times the second time constant. It can be seen that the reaction time of the substrate trigger signal is related to the second time constant. By reasonably determining the second time constant 1/R2*C2 The values of R2 and C2 can be obtained to determine the response time of the substrate trigger signal.

Example 3:

On the basis of Embodiment 1 and Embodiment 2, continue to refer to FIG. 6 to describe the situation when the electrostatic discharge branch 30 includes a PMOS transistor.

The electrostatic discharge branch circuit includes: a PMOS element. The PMOS element includes a gate, a first electrode, a second electrode and a substrate. Wherein, the gate is connected to the output end of the gate trigger signal generating circuit; the first electrode is the drain and is connected to the ground; the second electrode is connected as the source and is connected to the power supply; the substrate is connected to the substrate trigger signal generating circuit output.

In one implementation manner, the gate trigger signal generation circuit 10 includes: a first detection circuit.

The first detection circuit includes: a first resistance element and a first capacitance element. One end of the first resistive element is connected to the power supply, one end of the first capacitive element is connected to the other end of the first resistive element, and the other end of the first capacitive element is connected to the ground VSS.

The gate of the PMOS transistor is connected between the first resistance element and the first capacitance element of the first detection circuit.

In another implementation manner, as shown in FIG. 6 , the gate trigger signal generation circuit 10 includes: a first detection circuit 101 and an in-phase circuit 102 .

The first detection circuit 101 includes: a first resistive element and a first capacitive element; one end of the first resistive element is connected to the power supply VCC, one end of the first capacitive element is connected to the other end of the first resistive element, and the first capacitive element The other end is connected to ground VCC;

The non-inverting circuit is formed by cascading an even number of inverters, including an input terminal and an output terminal. The input terminal of the non-inverting circuit is connected between the first resistance element and the first capacitive element, and the output end is connected to the gate of the PMOS element.

As shown in FIG. 7, the substrate trigger signal generation circuit includes: a second detection circuit 201, a buffer 203, a third detection circuit 202, a logic gate 204 and an inverting circuit 205;

Wherein, the second detection circuit 201 , the buffer 203 , the third detection circuit 202 and the logic gate 201 are the same as those described in Embodiment 2 and will not be described again.

The inverter circuit 205 is formed by cascading an odd number of inverters, including an input terminal and an output terminal. The input terminal of the inverter circuit is connected to the output terminal of the logic gate, and the output terminal of the inverter circuit is connected to the substrate of the PMOS transistor.

In the above, the time constant of the first resistive element and the first capacitive element of the first detection circuit is the first time constant, the time constant of the second resistive element and the second capacitive element of the second detection circuit is the second time constant, the second The time constant of the third resistive element and the third capacitive element of the three detection circuits is a third time constant;

The first time constant is greater than the rise time of the electrostatic discharge voltage and less than the duration of the electrostatic discharge voltage; the third time constant is greater than the duration of the electrostatic discharge voltage; the second time constant is greater than or equal to the rise time of the electrostatic discharge voltage and less than the third time constant, the response time of the substrate trigger signal is related to the second time constant.

The above content is a further detailed description of the present invention in conjunction with specific embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (10)

1. An electrostatic discharge ESD protection circuit, comprising an electrostatic discharge branch circuit with one or more MOS tubes, is characterized in that, also includes: A gate trigger signal generating circuit, configured to generate a gate trigger signal, the output terminal of the gate trigger signal generating circuit is connected to the gate of at least one MOS transistor; A substrate trigger signal generation circuit, configured to generate a substrate trigger signal, the output end of the substrate trigger signal generation circuit is connected to the substrate of the at least one MOS transistor; Wherein, the response time of the substrate trigger signal is not less than the rise time of the electrostatic discharge voltage; or the response time of the substrate trigger signal is not less than 20 ns. 2. electrostatic discharge ESD protection circuit as claimed in claim 1, is characterized in that, The electrostatic discharge branch circuit includes: an NMOS transistor; the NMOS transistor includes a gate, a first electrode, a second electrode and a substrate, the gate is connected to the output end of the gate trigger signal generating circuit, and the first One electrode is connected to the power supply, the second electrode is connected to the ground, and the substrate is connected to the output terminal of the substrate trigger signal generating circuit; The gate trigger signal generation circuit includes: a first detection circuit and an inverting circuit; The first detection circuit includes: a first resistance element and a first capacitance element; one end of the first resistance element is connected to a power supply, and one end of the first capacitance element is connected to the other end of the first resistance element One end, the other end of the first capacitive element is connected to ground; The inverter circuit is formed by cascading an odd number of inverters, including an input end and an output end, the input end is connected between the first resistance element and the first capacitance element, and the output end is the The output terminal of the gate trigger signal generating circuit outputs the gate trigger signal and is connected to the gate of the NMOS transistor. 3. electrostatic discharge ESD protection circuit as claimed in claim 2, is characterized in that, the time constant of the first resistive element of described first detection circuit and the first capacitive element is the first time constant, and described first time constant Greater than the rise time of the electrostatic discharge voltage, less than the duration of the electrostatic discharge voltage. 4. The electrostatic discharge ESD protection circuit according to any one of claims 1 to 3, wherein the substrate trigger signal generating circuit comprises: a second detection circuit, a buffer, a third detection circuit and a logic gate ; The second detection circuit includes: a second resistance element and a second capacitance element, one end of the second resistance element is connected to a power supply, and one end of the second capacitance element is connected to the other end of the first resistance element one end, the other end of the second capacitive element is connected to ground; The buffer includes: an input terminal and an output terminal, the input terminal is connected between the second resistance element and the second capacitance element of the second detection circuit; The third detection circuit includes: a third resistance element and a third capacitance element, one end of the third resistance element is connected to the output end of the buffer, and one end of the third capacitance element is connected to the The other end of the third resistive element, the other end of the third capacitive element is connected to ground; The logic gate is an XOR logic gate, including two input terminals and an output terminal, wherein one input terminal is connected between the second resistance element and the second capacitance element of the second detection circuit, and the other input terminal is connected to the third Between the third resistive element and the third capacitive element of the detection circuit; the output end is the output end of the substrate trigger signal generating circuit, which is used to output the substrate trigger signal and is connected to the substrate of the NMOS transistor . 5. electrostatic discharge ESD protection circuit as claimed in claim 4, is characterized in that, the time constant of the second resistive element of described second detection circuit and the second capacitive element is the second time constant, and the 3rd detection circuit The time constant of the third resistive element and the third capacitive element is the third time constant; The third time constant is greater than the duration of the electrostatic discharge voltage; the second time constant is greater than or equal to the rise time of the electrostatic discharge voltage, but less than the third time constant. 6. electrostatic discharge ESD protection circuit as claimed in claim 1, is characterized in that, The electrostatic discharge branch includes: a PMOS transistor; the PMOS transistor includes a gate, a first electrode, a second electrode and a substrate, the gate is connected to the output terminal of the gate trigger signal generating circuit, and the first electrode connected to the ground, the second electrode is connected to the power supply, and the substrate is connected to the output end of the substrate trigger signal generating circuit; The gate trigger signal generation circuit includes: a first detection circuit; The first detection circuit includes: a first resistance element and a first capacitance element; one end of the first resistance element is connected to a power supply, and one end of the first capacitance element is connected to the other end of the first resistance element One end, the other end of the first capacitive element is connected to ground; The substrate of the PMOS transistor is connected between the first resistance element and the first capacitance element. 7. electrostatic discharge ESD protection circuit as claimed in claim 1, is characterized in that, The electrostatic discharge branch includes: a PMOS element; the PMOS element includes a gate, a first electrode, a second electrode and a substrate, the gate is connected to the output terminal of the gate trigger signal generating circuit, and the first electrode connected to the ground, the second electrode is connected to the power supply, and the substrate is connected to the output end of the substrate trigger signal generating circuit; The gate trigger signal generation circuit includes: a first detection circuit and a non-inverting circuit; The first detection circuit includes: a first resistance element and a first capacitance element; one end of the first resistance element is connected to a power supply, and one end of the first capacitance element is connected to the other end of the first resistance element One end, the other end of the first capacitive element is connected to ground; The non-inverting circuit is formed by cascading an even number of inverters, including an input terminal and an output terminal, the input terminal of the non-inverting circuit is connected between the first resistive element and the first capacitive element, and the output terminal is the The output end of the gate trigger signal generating circuit is connected to the gate of the PMOS transistor. 8. electrostatic discharge ESD protection circuit as claimed in claim 6 or 7, is characterized in that, the time constant of the first resistive element of described first detection circuit and the first capacitive element is the first time constant, and the first The time constant is greater than the rise time of the electrostatic discharge voltage and less than the duration of the electrostatic discharge voltage. 9. The electrostatic discharge ESD protection circuit as claimed in claim 6 or 7, wherein the substrate trigger signal generating circuit comprises: a second detection circuit, a buffer, a third detection circuit, a logic gate and an inverter circuit ; The second detection circuit includes: a second resistance element and a second capacitance element, one end of the second resistance element is connected to a power supply, and one end of the second capacitance element is connected to the other end of the second resistance element one end, the other end of the second capacitive element is connected to ground; The buffer includes: an input terminal and an output terminal, the input terminal is connected between the second resistance element and the second capacitance element of the second detection circuit; The third detection circuit includes: a third resistance element and a third capacitance element, one end of the third resistance element is connected to the output end of the buffer, and one end of the third capacitance element is connected to the The other end of the third resistive element, the other end of the third capacitive element is connected to ground; The logic gate is an XOR logic gate, including two input terminals and an output terminal, wherein one input terminal is connected between the second resistance element and the second capacitance element of the second detection circuit, and the other input terminal is connected to the third Between the third resistance element and the third capacitance element of the detection circuit; The inverting circuit is formed by cascading an odd number of inverters, including an input terminal and an output terminal, the input terminal of the inverting circuit is connected to the output terminal of the logic gate, and the output terminal of the inverting circuit is the substrate The output terminal of the trigger signal generating circuit is connected to the substrate of the PMOS transistor. 10. electrostatic discharge ESD protection circuit as claimed in claim 9 is characterized in that, the time constant of the second resistance element of described second detection circuit and the second capacitance element is the second time constant, and the third detection circuit The time constant of the third resistive element and the third capacitive element is the third time constant; The third time constant is greater than the duration of the electrostatic discharge voltage; the second time constant is greater than the rise time of the electrostatic discharge voltage but less than the third time constant.

Images