CN102185301A - Static discharge ESD protective circuit - Google Patents
Static discharge ESD protective circuit Download PDFInfo
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Abstract
The invention discloses a static discharge ESD protective circuit comprising a static discharge branch with one or more MOS tubes, a grid trigger signal generating circuit and an underlay trigger signal generating circuit, wherein the grid trigger signal generating circuit is used for generating a grid trigger signal; the grid trigger signal is connected to a grid of at least one MOS tube; the underlay trigger signal generating circuit is used for generating underlay trigger signals that are connected to an underlay of at least one MOS tube; and the reaction time of the underlay trigger signal is not less than the rising time of the static discharge voltage or 20ns. The static discharge ESD protective circuit has the advantages of improving the protective capability of the static discharge protective circuit and reducing the possibility of current leakage caused by error trigger.
Description
Technical field
The present invention relates to the static discharge esd protection circuit.
Background technology
When the contact of two nonconducting objects when separating, all might between two objects, cause the transfer of electronics, and make these two nonconducting objects produce additional charge that this additional charge is static.And when the static of accumulating on the object during to the relatively low object discharge of current potential, just produce static discharge (Electro-StaticDischarge, ESD).
Along with development of semiconductor, static discharge ESD problem is on the rise in integrated circuit.The designer is from the process level of integrated circuit, device level, circuit stages and system-level etc. researched and developed multiple static discharge esd protection circuit.Wherein, based on the static discharge esd protection circuit of field effect transistor MOS since its be easy to realize and protective capability good, be widely used.
In the static discharge esd protection circuit based on field effect transistor MOS, area utilization and minimizing gate resistance in order to improve metal-oxide-semiconductor generally adopt interdigital structure.In the interdigital structure, when each interdigital even conducting electric current, metal-oxide-semiconductor bears the ability maximum of electric current, and the electrostatic discharge (ESD) protection ability is the strongest.But actual situation is, has only the interdigital structure of small part can conducting when static discharge, though conducting, also just in the top conducting of channel width W direction.
In order to improve in the static discharge esd protection circuit, the ducting capacity of metal-oxide-semiconductor promptly increases the protective capability of static discharge esd protection circuit.Utilize the gate bias effect or utilize substrate bias effect to achieve the above object effectively, and the effect of substrate bias effect can be better.
Wherein, the ducting capacity of utilizing the gate bias effect to improve metal-oxide-semiconductor is meant, by apply certain voltage on the grid of metal-oxide-semiconductor, is to make metal-oxide-semiconductor be operated in inferior valve district or saturation region with the gate trigger voltage that reduces metal-oxide-semiconductor.Because the trigger voltage of metal-oxide-semiconductor is reduced, metal-oxide-semiconductor can quickly respond to static discharge.Simultaneously, the second breakdown current value of metal-oxide-semiconductor obtains increasing, and the electrostatic discharge (ESD) protection protective capability is enhanced.The defective that this kind mode exists is that because metal-oxide-semiconductor has the surface current concentrations effect, when having grid voltage, the surface of metal-oxide-semiconductor will inevitably produce certain heat power consumption.If grid voltage continues to exist, then the temperature on metal-oxide-semiconductor surface will increase gradually, may damage or damage metal-oxide-semiconductor.
The ducting capacity of utilizing the substrate biasing to promote metal-oxide-semiconductor is meant, applies certain bias voltage on the substrate of metal-oxide-semiconductor, makes the PN junction positively biased between substrate and source electrode, promotes the second breakdown current value of metal-oxide-semiconductor.In the NPN of parasitism element, the PN junction between positively biased substrate and source electrode (being the emitter junction of positively biased parasitic NPN element) can make the NPN element be operated in the amplification region, the electric current that conducting is a large amount of, the protective capability of raising electrostatic discharge circuit.Substrate bias effect can produce leakage current, and in normal static discharge ESD process, this leakage current improves the key of static discharge current amount just.But, when substrate bias effect is not to be triggered by normal static, but cause that by some interference (such as disturbing pulse) this leakage current will exert an influence to circuit so.When therefore adopting substrate bias effect to improve the protective capability of ESD protection circuit, might be owing to false triggering produces leakage current.
Summary of the invention
The main technical problem to be solved in the present invention is, a kind of static discharge esd protection circuit is provided, and can reduce the possibility that false triggering causes leakage current when improving the electrostatic discharge (ESD) protection ability.For solving the problems of the technologies described above, the invention provides a kind of static discharge esd protection circuit, comprise static discharge branch road with one or more metal-oxide-semiconductors, also comprise:
The grid triggering signal produces circuit, is used to produce the grid triggering signal, and the output of described grid triggering signal generation circuit is connected to the grid of at least one metal-oxide-semiconductor;
The substrate triggering signal produces circuit, is used to produce the substrate triggering signal, and the output of described substrate triggering signal generation circuit is connected to the substrate of described at least one metal-oxide-semiconductor;
Wherein, the reaction time of described substrate triggering signal is not less than the rise time of described static discharge voltage; The reaction time of perhaps described substrate triggering signal is not less than 20ns.
In a kind of execution mode, described static discharge branch road comprises: NMOS pipe; Described NMOS pipe comprises grid, first electrode, second electrode and substrate, described grid is connected to the output that described grid triggering signal produces circuit, first electrode is connected to power supply, and second electrode is connected to ground, and substrate is connected to the output that the substrate triggering signal produces circuit;
Described grid triggering signal produces circuit and comprises: first testing circuit and negative circuit;
Described first testing circuit comprises: one first resistive element and one first capacity cell; One end of described first resistive element is connected to power supply, and an end of described first capacity cell is connected to the other end of described first resistive element, and the other end of described first capacity cell is connected to ground;
Described negative circuit is formed by the cascade of odd number inverter, comprise input and output, described input is connected between described first resistive element and first capacity cell, described output is the output that described grid triggering signal produces circuit, export the grid triggering signal, be connected to the grid of described NMOS pipe.
Further, first resistive element of described first testing circuit and the time constant of first capacity cell are very first time constant, and described very first time constant is greater than the rise time of static discharge voltage, less than the duration of static discharge voltage.
In a kind of execution mode, described substrate triggering signal produces circuit and comprises: second testing circuit, buffer, three testing circuit and gate;
Described second testing circuit comprises: one second resistive element and one second capacity cell, one end of described second resistive element is connected to power supply, one end of described second capacity cell is connected to the other end of described first resistive element, and the other end of described second capacity cell is connected to ground;
Described buffer comprises: input and output, described input are connected between second resistive element and second capacity cell of described second testing circuit;
Described three testing circuit comprises: one the 3rd resistive element and one the 3rd capacity cell, one end of described the 3rd resistive element is connected to the output of described buffer, one end of described the 3rd capacity cell is connected to the other end of described the 3rd resistive element, and the other end of described the 3rd capacity cell is connected to ground;
Described gate is an exclusive or logic gate, comprise two inputs and output, one of them input is connected between second resistive element and second capacity cell of second testing circuit, and another input is connected between the 3rd resistive element and the 3rd capacity cell of three testing circuit; Described output is the output that described substrate triggering signal produces circuit, is used to export the substrate triggering signal, and is connected to the substrate of described NMOS pipe.
Further, second resistive element of described second testing circuit and the time constant of second capacity cell are second time constant, and the 3rd resistive element of described three testing circuit and the time constant of the 3rd capacity cell are the 3rd time constant;
Described the 3rd time constant is greater than the duration of described static discharge voltage; Described second time constant is more than or equal to the rise time of described static discharge voltage, less than the 3rd time constant.
In the another kind of execution mode, described static discharge branch road comprises: PMOS pipe; Described PMOS pipe comprises grid, first electrode, second electrode and substrate, described grid is connected to the output that the grid triggering signal produces circuit, first electrode is connected to ground, and second electrode is connected to power supply, and substrate is connected to the output that the substrate triggering signal produces circuit;
Described grid triggering signal produces circuit and comprises: first testing circuit;
Described first testing circuit comprises: one first resistive element and one first capacity cell; One end of described first resistive element is connected to power supply, and an end of described first capacity cell is connected to the other end of described first resistive element, and the other end of described first capacity cell is connected to ground;
The substrate of described PMOS pipe is connected between described first resistive element and first capacity cell.
In the another kind of execution mode, described static discharge branch road comprises: a PMOS element; Described PMOS element comprises grid, first electrode, second electrode and substrate, described grid is connected to the output that the grid triggering signal produces circuit, first electrode is connected to ground, and second electrode is connected to power supply, and substrate is connected to the output that the substrate triggering signal produces circuit;
Described grid triggering signal produces circuit and comprises: first testing circuit and same circuitry phase;
Described first testing circuit comprises: one first resistive element and one first capacity cell; One end of described first resistive element is connected to power supply, and an end of described first capacity cell is connected to the other end of described first resistive element, and the other end of described first capacity cell is connected to ground;
Describedly form by the even number of inverters cascade with circuitry phase, comprise input and output, described input with circuitry phase is connected between described first resistive element and first capacity cell, output is the output that described grid triggering signal produces circuit, is connected to the grid of described PMOS pipe.
Further, first resistive element of described first testing circuit and the time constant of first capacity cell are very first time constant, and described very first time constant is greater than the rise time of static discharge voltage, less than the duration of static discharge voltage.
In the another kind of execution mode, described substrate triggering signal produces circuit and comprises: second testing circuit, buffer, three testing circuit, gate and negative circuit;
Described second testing circuit comprises: one second resistive element, one second capacity cell, one end of described second resistive element is connected to power supply, one end of described second capacity cell is connected to the other end of described second resistive element, and the other end of described second capacity cell is connected to ground;
Described buffer comprises: input and output, described input are connected between second resistive element and second capacity cell of described second testing circuit;
Described three testing circuit comprises: one the 3rd resistive element and one the 3rd capacity cell, one end of described the 3rd resistive element is connected to the output of described buffer, one end of described the 3rd capacity cell is connected to the other end of described the 3rd resistive element, and the other end of described the 3rd capacity cell is connected to ground;
Described gate is an exclusive or logic gate, comprise two inputs and output, one of them input is connected between second resistive element and second capacity cell of second testing circuit, and another input is connected between the 3rd resistive element and the 3rd capacity cell of three testing circuit;
Described negative circuit is formed by the cascade of odd number inverter, comprise input and output, the input of negative circuit is connected to the output of described gate, and the output of negative circuit is the output that described substrate triggering signal produces circuit, is connected to the substrate of described PMOS pipe.
Further, second resistive element of described second testing circuit and the time constant of second capacity cell are second time constant, and the 3rd resistive element of described three testing circuit and the time constant of the 3rd capacity cell are the 3rd time constant;
Described the 3rd time constant is greater than the duration of described static discharge voltage; Described second time constant is greater than the rise time of described static discharge voltage, less than the 3rd time constant.
The invention has the beneficial effects as follows: after the grid triggering signal produced on the grid that grid triggering signal that circuit produces is added to the MOS element, the trigger voltage of MOS element reduced, and has improved the discharge capability of static discharge esd protection circuit; After the substrate triggering signal that the substrate triggering signal produces was added on the substrate of MOS element, MOS element generation substrate bias effect had strengthened the current lead-through ability of MOS element, has improved the discharge capability of ESD protection circuit.Simultaneously, because the reaction time of substrate triggering signal is greater than or equal to the rise time (being about 10ns) of static discharge voltage, usually the duration of the pulse of false triggering can be greater than the rise time of normal static discharge voltage, so even false triggering has taken place, the substrate triggering signal can not act on substrate yet, thereby has reduced the possibility of leakage current generating under the improper situation.And reaction time of substrate triggering signal when being set to be not less than 20ns be in order to keep certain design margin, the design philosophy of this coincident circuit, and can reach better effect.
Description of drawings
Fig. 1 is the static discharge esd protection circuit overall diagram of one embodiment of the present invention;
Fig. 2 is that the grid triggering signal of one embodiment of the present invention produces circuit diagram;
Fig. 3 is that the grid triggering signal of another embodiment of the present invention produces circuit diagram;
Fig. 4 is that the substrate triggering signal of one embodiment of the present invention produces circuit diagram;
Fig. 5 is the concrete structure figure that the substrate triggering signal of one embodiment of the present invention produces circuit;
Fig. 6 is that the grid triggering signal of another embodiment of the present invention produces circuit;
Fig. 7 is that the substrate triggering signal of another embodiment of the present invention produces circuit;
Fig. 8 is the waveform schematic diagram of a-signal and grid triggering signal among Fig. 3;
Fig. 9 is the waveform schematic diagram of B signal in 5, C signal, D signal, E signal and substrate triggering signal.
Embodiment
In conjunction with the accompanying drawings the present invention is described in further detail below by embodiment.
Embodiment 1:
Please refer to Fig. 1, a kind of static discharge esd protection circuit comprises that static discharge branch road 30, grid triggering signal produce circuit 10 and the substrate triggering signal produces circuit 20.
Wherein, static discharge branch road 30 comprises one or more metal-oxide-semiconductor, and the type of these metal-oxide-semiconductors can be NMOS pipe or PMOS pipe.When static discharge branch road 30 comprised a plurality of metal-oxide-semiconductor, these metal-oxide-semiconductors were formed the static discharge branch road by modes such as series connection or parallel connection or connection in series-parallel.Static discharge branch road 30 comprises two external input terminals, be respectively applied for power supply VCC and be connected with ground VSS, perhaps be connected with ground VSS, be used for the static of power supply VCC or pad PAD generation is transferred to ground by static discharge branch road 30, realize discharge with external pads PAD.Preferably, static discharge branch road 30 comprises a NMOS pipe or a PMOS pipe.
The grid triggering signal produces circuit 10, is used to produce the grid triggering signal, and this grid triggering signal is applied to the grid of metal-oxide-semiconductor.When static discharge branch road 30 included only a metal-oxide-semiconductor, the grid triggering signal was applied to the grid of this metal-oxide-semiconductor; When static discharge branch road 30 comprises a plurality of metal-oxide-semiconductor, the grid triggering signal be applied in a plurality of metal-oxide-semiconductors one or some or all of on.The grid triggering signal is applied on the grid of metal-oxide-semiconductor, can reduce the gate trigger voltage of metal-oxide-semiconductor, and metal-oxide-semiconductor is discharged to static as early as possible, improves the second breakdown current value of metal-oxide-semiconductor.
The substrate triggering signal produces circuit 20, is used to produce the substrate triggering signal, and this substrate triggering signal is applied on the substrate of metal-oxide-semiconductor.When static discharge branch road 30 included only a metal-oxide-semiconductor, the substrate triggering signal was applied to the substrate of this metal-oxide-semiconductor; When the static discharge branch road comprises a plurality of metal-oxide-semiconductor, the substrate triggering signal be applied in a plurality of metal-oxide-semiconductors one or some or all of on.The substrate triggering signal is applied on the substrate of metal-oxide-semiconductor, makes metal-oxide-semiconductor generation substrate bias effect, promotes the second breakdown current value of metal-oxide-semiconductor, strengthens the current lead-through ability of metal-oxide-semiconductor.
Preferably, the grid triggering signal is applied on one or more identical metal-oxide-semiconductor with the substrate triggering signal.
In above-mentioned, grid triggering signal and substrate triggering signal life period are poor, and the reaction time of substrate triggering signal is more than or equal to the rise time of static discharge voltage, perhaps more than or equal to 20ns.
Particularly, in a discharge cycle, the grid triggering signal was applied on the grid of metal-oxide-semiconductor at the very start from the static discharge cycle, made metal-oxide-semiconductor generation gate bias effect, reduced gate trigger voltage.And, the grid triggering signal acts on the rise time of the duration of metal-oxide-semiconductor greater than static discharge ESD voltage, less than the duration of static discharge ESD voltage, promptly at a static discharge in the cycle, the grid triggering signal is not the grid generation gate bias effect that always makes metal-oxide-semiconductor.
The substrate triggering signal has a reaction time, makes its time point that begins to act on the metal-oxide-semiconductor substrate be later than the rise time of static discharge ESD voltage, but lasts till that static discharge finishes.The substrate triggering signal makes substrate generation bias effect, improves the current lead-through ability of metal-oxide-semiconductor.
At a static discharge in the cycle, the grid triggering signal acts on the grid of metal-oxide-semiconductor at electrostatic discharge event when taking place, make metal-oxide-semiconductor generation gate bias effect, has improved the magnitude of current of metal-oxide-semiconductor conducting.Simultaneously, the static discharge that acts on of grid triggering signal is finished preceding end, has reduced the influence of surface current concentrations effect to metal-oxide-semiconductor.Main influence shows, exist bias voltage and metal-oxide-semiconductor to have under the situation of current lead-through at grid, if grid voltage continues to exist, because metal-oxide-semiconductor has the surface current concentrations effect, the temperature on the surface of metal-oxide-semiconductor can be more and more higher, and metal-oxide-semiconductor may be damaged or damage to the temperature that continues to increase.
The time point that the substrate triggering signal begins to act on the metal-oxide-semiconductor substrate is later than the rise time of static discharge ESD voltage, so even false triggering takes place, also can not produce leakage current.Because the time of common false triggering is very short,,, just can not produce leakage current so the substrate triggering signal can not reacted to false triggering less than the rise time of static discharge ESD voltage yet.And this kind mode can be according to reaction time of design substrate triggering signal reasonably possible time of false triggering in the side circuit, thereby realize better avoiding because the generation of the leakage current that false triggering causes.
Embodiment 2:
On the basis of embodiment 1, describe referring to figs. 2 to 5 pairs of ESD protection circuits when the static discharge branch road comprises NMOS pipe.
The static discharge branch road comprises: NMOS pipe.The NMOS pipe comprises grid, first electrode, second electrode and substrate.Wherein, grid is connected to the output that the grid triggering signal produces circuit, and the output that the grid triggering signal produces circuit is used to export the grid triggering signal; First electrode is connected to power supply for drain electrode; Second electrode is a source electrode, is connected to ground; Substrate is connected to the output that the substrate triggering signal produces circuit, and the output that the substrate triggering signal produces circuit is used to export the substrate triggering signal.
As shown in Figure 2, grid triggering signal generation circuit comprises: first testing circuit 101 and negative circuit 102.
Wherein, first testing circuit 101 comprises: one first resistive element and one first capacity cell.First resistive element is formed by one or more resistance series connection or parallel connection or connection in series-parallel, and first capacity cell is also formed by one or more capacitances in series or parallel connection or connection in series-parallel.Perhaps first resistive element is realized by other form, and first resistive element is realized by other form.Preferably, as shown in Figure 3, first resistive element is that a resistance R 1, the first capacity cell is a capacitor C 1.
One end of first resistive element is connected to power supply VCC, and an end of first capacity cell is connected to the other end of first resistive element, and the other end of first capacity cell is connected to ground VSS.
As shown in Figure 4, described substrate triggering signal generation circuit 20 comprises: second testing circuit 201, buffer 203, three testing circuit 202 and gate 204;
Wherein, second testing circuit 201 comprises: one second resistive element and one second capacity cell, three testing circuit 202 comprises: one the 3rd resistive element and one the 3rd capacity cell.Second resistive element and the 3rd resistive element are formed by one or more resistance series connection or parallel connection or connection in series-parallel, and second capacity cell and the 3rd capacity cell are formed by one or more capacitances in series or parallel connection or connection in series-parallel.Preferably, as shown in Figure 5, second resistive element of second testing circuit 201 is that a resistance R 2, the second capacity cells are a capacitor C 2; The 3rd resistive element of three testing circuit 202 is that a resistance R 3, the three capacity cells are a capacitor C 3.
In second testing circuit 201, an end of second resistive element is connected to power supply VCC, and an end of second capacity cell is connected to the other end of second resistive element, and the other end of second capacity cell is connected to ground VSS.
In the three testing circuit 202, an end of the 3rd resistive element is connected to the output of buffer, and an end of the 3rd capacity cell is connected to the other end of the 3rd resistive element, and the other end of the 3rd capacity cell is connected to ground VSS.
In above-mentioned, second resistive element of first testing circuit and the time constant of first capacity cell are very first time constant, second resistive element of second testing circuit and the time constant of second capacity cell are second time constant, and the 3rd resistive element of three testing circuit and time constant at three capacity cells are the 3rd time constant.
Very first time constant is greater than the rise time (approximately less than 10ns) of static discharge voltage, (is about 100～1000ns) less than duration of static discharge voltage; The 3rd time constant is greater than the duration of static discharge voltage; Second time constant is not less than the rise time of described static discharge voltage, and less than the 3rd time constant, second time constant is the reaction time of substrate triggering signal.At this moment, second time constant is the reaction time of substrate triggering signal, and static discharge must continue second time constant after the time so of a specified duration, and the substrate triggering signal just can make the substrate generation substrate bias effect of NMOS pipe.
Preferably, the situation when producing circuit 10 and substrate triggering signal and produce circuit 20 and be respectively Fig. 3 and concrete structure shown in Figure 5 with the grid triggering signal below is an example, and grid triggering signal and the substrate triggering signal effect situation to the NMOS pipe is described:
When the static discharge esd event occurs between power supply VCC and the ground VSS, capacitor C 1 among Fig. 2 can not be suddenlyd change, the signal A of first testing circuit, 101 outputs rises since 0 voltage, effect through negative circuit 102, output grid triggering signal Gate, the waveform signal of signal A and grid triggering signal Gate as shown in Figure 8.As shown in Figure 8, before esd event just took place, grid triggering signal Gate had just acted on the grid of NMOS pipe, makes the NMOS pipe be operated in saturation region or linear zone, has reduced gate trigger voltage.When esd event took place, because the magnitude of voltage at capacitor C 1 two ends can not suddenly change, the grid triggering signal was still a high level, and after through 2.2 times of very first time constants, grid triggering signal Gate just drops to 0, and the gate bias effect is revival not.Very first time constant is by R1 and C1 decision, and its value is 1/R1*C1.
In the static discharge process, the waveform schematic diagram of the output signal E of the output signal D of the output signal B of second testing circuit 201, buffer 203, three testing circuit 202 and substrate triggering signal Substrate as shown in Figure 9 among Fig. 5.As seen from the figure, substrate triggering signal Substrate is formed by the output signal B of second testing circuit 201 and the output signal E XOR of three testing circuit 202.Therefore, when esd event took place, because output signal B is a low level, output signal E was a high level, and substrate triggering signal Substrate is a low level, can not make the NMOS pipe that substrate bias effect takes place.After second time constant of 2.2 times of esd event courses of emergency, output signal B becomes high level, and output signal E also is a high level, and substrate triggering signal Substrate is a high level, makes substrate generation substrate bias effect.After esd event was through 2.2 times the 3rd time constant, output signal E became low level, and substrate triggering signal Substrate becomes high level, finished the effect to substrate.The value of second time constant is 1/R2*C2, and the value of the 3rd time constant is 1/R3*C3.Because after esd event must continue 2.2 times of second time constant, substrate triggering signal Substrate could work to substrate, make it that substrate bias effect take place, produce leakage current, improve in the discharge capability reality of metal-oxide-semiconductor, because the time of false triggering does not reach 2.2 times second time constant (second time constant is more than or equal to the ESD voltage rise time), so false triggering can not produce leakage current.
In above-mentioned, 0～2.2/R1*C1 will be defined as action time of grid triggering signal, being defined as between 2.2/R2*C2～2.2/R3*C3 the action time of substrate triggering signal is in order to keep certain design margin, and realistic designing requirement also can reach better effect.
In above-mentioned, the reaction time of substrate triggering signal is 2.2 times second time constant, this shows, the reaction time of substrate triggering signal is relevant with second time constant, by rationally determining the reaction time of the substrate triggering signal that the value of R2 and C2 can obtain determining among the second time constant 1/R2*C2.
Embodiment 3:
On the basis of embodiment 1 and embodiment 2, the situation when continuation comprises PMOS pipe with reference to 6 pairs of static discharge branch roads 30 of figure describes.
The static discharge branch road comprises: a PMOS element.The PMOS element comprises grid, first electrode, second electrode and substrate.Wherein, grid is connected to the output that the grid triggering signal produces circuit; First electrode is connected to ground for drain electrode; Second electrode is linked as source electrode, is connected to power supply; Substrate is connected to the output that the substrate triggering signal produces circuit.
In a kind of execution mode, the grid triggering signal produces circuit 10 and comprises: first testing circuit.
First testing circuit comprises: one first resistive element and one first capacity cell.One end of first resistive element is connected to power supply, and an end of first capacity cell is connected to the other end of first resistive element, and the other end of first capacity cell is connected to ground VSS.
The grid of PMOS pipe is connected between first resistive element and first capacity cell of first testing circuit.
In the another kind of execution mode, as shown in Figure 6, the grid triggering signal produces circuit 10 and comprises: first testing circuit 101 and with circuitry phase 102.
Formed by the even number of inverters cascade with circuitry phase, comprise input and output, be connected between first resistive element and first capacity cell with the input of circuitry phase, output is connected to the grid of PMOS element.
As shown in Figure 7, substrate triggering signal generation circuit comprises: second testing circuit 201, buffer 203, three testing circuit 202, gate 204 and negative circuit 205;
Wherein, consistent with described in the embodiment 2 of second testing circuit 201, buffer 203, three testing circuit 202 and gate 201, no longer narration.
In above-mentioned, first resistive element of first testing circuit and the time constant of first capacity cell are very first time constant, second resistive element of second testing circuit and the time constant of second capacity cell are second time constant, and the 3rd resistive element of three testing circuit and the time constant of the 3rd capacity cell are the 3rd time constant;
Very first time constant is greater than the rise time of static discharge voltage, less than the duration of static discharge voltage; The 3rd time constant is greater than the duration of static discharge voltage; Second time constant is more than or equal to the rise time of static discharge voltage, and less than the 3rd time constant, the reaction time of substrate triggering signal is relevant with second time constant.
Above content be in conjunction with concrete execution mode to further describing that the present invention did, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (10)
1. a static discharge esd protection circuit comprises the static discharge branch road with one or more metal-oxide-semiconductors, it is characterized in that, also comprises:
The grid triggering signal produces circuit, is used to produce the grid triggering signal, and the output of described grid triggering signal generation circuit is connected to the grid of at least one metal-oxide-semiconductor;
The substrate triggering signal produces circuit, is used to produce the substrate triggering signal, and the output of described substrate triggering signal generation circuit is connected to the substrate of described at least one metal-oxide-semiconductor;
Wherein, the reaction time of described substrate triggering signal is not less than the rise time of described static discharge voltage; The reaction time of perhaps described substrate triggering signal is not less than 20ns.
2. static discharge esd protection circuit as claimed in claim 1 is characterized in that,
Described static discharge branch road comprises: NMOS pipe; Described NMOS pipe comprises grid, first electrode, second electrode and substrate, described grid is connected to the output that described grid triggering signal produces circuit, first electrode is connected to power supply, and second electrode is connected to ground, and substrate is connected to the output that the substrate triggering signal produces circuit;
Described grid triggering signal produces circuit and comprises: first testing circuit and negative circuit;
Described first testing circuit comprises: one first resistive element and one first capacity cell; One end of described first resistive element is connected to power supply, and an end of described first capacity cell is connected to the other end of described first resistive element, and the other end of described first capacity cell is connected to ground;
Described negative circuit is formed by the cascade of odd number inverter, comprise input and output, described input is connected between described first resistive element and first capacity cell, described output is the output that described grid triggering signal produces circuit, export the grid triggering signal, be connected to the grid of described NMOS pipe.
3. static discharge esd protection circuit as claimed in claim 2; it is characterized in that; first resistive element of described first testing circuit and the time constant of first capacity cell are very first time constant; described very first time constant is greater than the rise time of static discharge voltage, less than the duration of static discharge voltage.
4. as each described static discharge esd protection circuit in the claim 1 to 3, it is characterized in that described substrate triggering signal produces circuit and comprises: second testing circuit, buffer, three testing circuit and gate;
Described second testing circuit comprises: one second resistive element and one second capacity cell, one end of described second resistive element is connected to power supply, one end of described second capacity cell is connected to the other end of described first resistive element, and the other end of described second capacity cell is connected to ground;
Described buffer comprises: input and output, described input are connected between second resistive element and second capacity cell of described second testing circuit;
Described three testing circuit comprises: one the 3rd resistive element and one the 3rd capacity cell, one end of described the 3rd resistive element is connected to the output of described buffer, one end of described the 3rd capacity cell is connected to the other end of described the 3rd resistive element, and the other end of described the 3rd capacity cell is connected to ground;
Described gate is an exclusive or logic gate, comprise two inputs and output, one of them input is connected between second resistive element and second capacity cell of second testing circuit, and another input is connected between the 3rd resistive element and the 3rd capacity cell of three testing circuit; Described output is the output that described substrate triggering signal produces circuit, is used to export the substrate triggering signal, and is connected to the substrate of described NMOS pipe.
5. static discharge esd protection circuit as claimed in claim 4, it is characterized in that, second resistive element of described second testing circuit and the time constant of second capacity cell are second time constant, and the 3rd resistive element of described three testing circuit and the time constant of the 3rd capacity cell are the 3rd time constant;
Described the 3rd time constant is greater than the duration of described static discharge voltage; Described second time constant is more than or equal to the rise time of described static discharge voltage, less than the 3rd time constant.
6. static discharge esd protection circuit as claimed in claim 1 is characterized in that,
Described static discharge branch road comprises: PMOS pipe; Described PMOS pipe comprises grid, first electrode, second electrode and substrate, described grid is connected to the output that the grid triggering signal produces circuit, first electrode is connected to ground, and second electrode is connected to power supply, and substrate is connected to the output that the substrate triggering signal produces circuit;
Described grid triggering signal produces circuit and comprises: first testing circuit;
Described first testing circuit comprises: one first resistive element and one first capacity cell; One end of described first resistive element is connected to power supply, and an end of described first capacity cell is connected to the other end of described first resistive element, and the other end of described first capacity cell is connected to ground;
The substrate of described PMOS pipe is connected between described first resistive element and first capacity cell.
7. static discharge esd protection circuit as claimed in claim 1 is characterized in that,
Described static discharge branch road comprises: a PMOS element; Described PMOS element comprises grid, first electrode, second electrode and substrate, described grid is connected to the output that the grid triggering signal produces circuit, first electrode is connected to ground, and second electrode is connected to power supply, and substrate is connected to the output that the substrate triggering signal produces circuit;
Described grid triggering signal produces circuit and comprises: first testing circuit and same circuitry phase;
Described first testing circuit comprises: one first resistive element and one first capacity cell; One end of described first resistive element is connected to power supply, and an end of described first capacity cell is connected to the other end of described first resistive element, and the other end of described first capacity cell is connected to ground;
Describedly form by the even number of inverters cascade with circuitry phase, comprise input and output, described input with circuitry phase is connected between described first resistive element and first capacity cell, output is the output that described grid triggering signal produces circuit, is connected to the grid of described PMOS pipe.
8. as claim 6 or 7 described static discharge esd protection circuits; it is characterized in that; first resistive element of described first testing circuit and the time constant of first capacity cell are very first time constant; described very first time constant is greater than the rise time of static discharge voltage, less than the duration of static discharge voltage.
9. as claim 6 or 7 described static discharge esd protection circuits, it is characterized in that described substrate triggering signal produces circuit and comprises: second testing circuit, buffer, three testing circuit, gate and negative circuit;
Described second testing circuit comprises: one second resistive element, one second capacity cell, one end of described second resistive element is connected to power supply, one end of described second capacity cell is connected to the other end of described second resistive element, and the other end of described second capacity cell is connected to ground;
Described buffer comprises: input and output, described input are connected between second resistive element and second capacity cell of described second testing circuit;
Described three testing circuit comprises: one the 3rd resistive element and one the 3rd capacity cell, one end of described the 3rd resistive element is connected to the output of described buffer, one end of described the 3rd capacity cell is connected to the other end of described the 3rd resistive element, and the other end of described the 3rd capacity cell is connected to ground;
Described gate is an exclusive or logic gate, comprise two inputs and output, one of them input is connected between second resistive element and second capacity cell of second testing circuit, and another input is connected between the 3rd resistive element and the 3rd capacity cell of three testing circuit;
Described negative circuit is formed by the cascade of odd number inverter, comprise input and output, the input of negative circuit is connected to the output of described gate, and the output of negative circuit is the output that described substrate triggering signal produces circuit, is connected to the substrate of described PMOS pipe.
10. static discharge esd protection circuit as claimed in claim 9, it is characterized in that, second resistive element of described second testing circuit and the time constant of second capacity cell are second time constant, and the 3rd resistive element of described three testing circuit and the time constant of the 3rd capacity cell are the 3rd time constant;
Described the 3rd time constant is greater than the duration of described static discharge voltage; Described second time constant is greater than the rise time of described static discharge voltage, less than the 3rd time constant.
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| CN201110132583.XA CN102185301B (en) | 2011-05-20 | 2011-05-20 | Static discharge ESD protective circuit |
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| CN201110132583.XA CN102185301B (en) | 2011-05-20 | 2011-05-20 | Static discharge ESD protective circuit |
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| CN106786455A (en) * | 2015-12-16 | 2017-05-31 | 成都芯源系统有限公司 | Esd protection circuit |
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| US20030133237A1 (en) * | 2001-09-03 | 2003-07-17 | Kei-Kang Hung | Power-rail electrostatic discharge protection circuit with a dual trigger design |
| US20060044716A1 (en) * | 2004-08-31 | 2006-03-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | ESD protection circuit with improved trigger-on voltage |
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