CN102176323A - Storage unit circuit with adaptive leakage current cutoff mechanism - Google Patents

Abstract

The invention provides a storage unit circuit with an adaptive leakage current cutoff mechanism, which is a dual-port read-writing sub-threshold storage unit circuit. The circuit comprises a first inverter and a second inverter which are connected in a cross coupling way; the two inverters are connected between complementary bit lines through an equalizer pipe; and the grid end of the equalizer pipe is connected with an enhanced word line. The invention overcomes the defects of the prior art and provides the sub-threshold storage unit circuit with low power consumption and high robustness; and the sub-threshold storage unit circuit can reduce leakage power consumptions in dynamic operation and static operation while the leakage power at the same time on the premise of not increasing dynamic power consumption or reducing performance, and can balance each index of a storage unit so as to optimize system performance.

Description

A kind of storage unit circuit with self-adaptation leakage-current-interrupting mechanism

Technical field

The present invention relates in the subthreshold value design, low-power consumption storage unit under the subthreshold value perform region, especially a kind of sub-threshold storing unit circuit with self-adaptation leakage-current-interrupting mechanism, its band self-adaptation leakage-current-interrupting mechanism can not increase dynamic power consumption and not reduce under the prerequisite of performance, reduce when realizing in dynamic operation and the static state operation leakage power, have characteristics such as high robust concurrently.

Background technology

Memory cell array is the important component part of Modern Digital System, also the power consumption bottleneck of system design often.Have higher requirement to the reduction power consumption technology of memory cell array to improving constantly of various portable set demands in market.The subthreshold value design is the hot topic of current super low-power consumption design.Enter the subthreshold value zone of circuit by reducing supply voltage Vdd: supply voltage Vdd is less than threshold voltage vt h, makes system works at the linear zone of circuit, so significantly reduce system dynamically, quiescent dissipation.The design of sub-threshold memory cell array has highlighted the low-power consumption superiority of subthreshold value design especially.

Along with further dwindling of technology characteristics size, the long L of grid, grid width W, oxidated layer thickness T _OXAnd process fluctuation such as dopant profiles more can not be ignored the influence that device brings.Wherein mixing at random, (it can have a strong impact on little physical dimension transistorized threshold voltage vt h, particularly sram cell, causes the rapid rising of crash rate for Random DopantFluctuation, having the greatest impact RDF) in fluctuation.Storer is the important component part of Design of Digital Circuit, and its crash rate will directly influence the yield of system.In typical superthreshold six transistor memory unit unit design, the deviser can by the balance pull-down transistor, pull up transistor and access transistor between the drive ratio relation, when satisfying the yield demand, reach the density requirements of memory cell.But it should be noted that in subthreshold value zone transistor drive current and threshold voltage exponent function relation the device technology deviation also becomes to the influence of storage unit yield and has more challenge, only depends on simple trim size can not satisfy the design needs.Memory cell structure is designed to subthreshold value memory circuit balance read-write operation, coordinates each crash rate, satisfies the key of the yield requirement of design.Along with the raising of semiconductor devices integrated level, constantly dwindling of characteristic dimension must cause the increase of static leakage current.The operating characteristic that it should be noted that memory bank has simultaneously determined its some component units will be in idle state (Standby Operation) for a long time.The composition number of transistors of considering memory bank is numerous, corresponding serviceable life and the reliability that increases sharply and then reduce product of the static energy consumption of memory bank.Therefore, how to reduce each storage unit static leakage current of memory bank and guarantee design performance simultaneously, that is on the basis that guarantees certain working current, reduce cell leakage current, become one of important research direction of memory bank design by circuit design.

Summary of the invention

The problem to be solved in the present invention is: the subthreshold value design of storage unit, be subjected to the influence of process, process deviation, need to reduce the storage unit circuit that each storage unit static leakage current of memory bank guarantees design performance simultaneously, on the basis that guarantees certain working current, reduce cell leakage current.

Technical scheme of the present invention is: a kind of storage unit circuit with self-adaptation leakage-current-interrupting mechanism, be provided with four PMOS pipe P1～P4 and eight NMOS pipe N1～N8, described transistor constitutes the sub-threshold storing unit circuit of both-end read-write, and described storage unit circuit is connected bit line BL and bit line Between;

Wherein, the body end of four PMOS pipes is connected with supply voltage Vdd, the body end ground connection of eight NMOS pipes; The drain terminal of NMOS pipe N1 and grid end link together with drain terminal and the grid end of PMOS pipe P1 respectively, form first phase inverter; The drain terminal of NMOS pipe N2 and grid end link together with drain terminal and the grid end of PMOS pipe P2 respectively, form second phase inverter; First phase inverter connects into cross-couplings with second phase inverter: the grid end of NMOS pipe N1 grid end, PMOS pipe P1, the drain terminal of NMOS pipe N2 and the drain terminal of PMOS pipe P2 are connected, and the grid end of the drain terminal of the drain terminal of NMOS pipe N1, PMOS pipe P1, the grid end of NMOS pipe N2 and PMOS pipe P2 is connected; The source end of PMOS pipe P1, P2 is connected with supply voltage Vdd, and the source end of NMOS pipe N1 is connected with the source end of PMOS pipe P3, the drain terminal ground connection of PMOS pipe P3, and the grid end is connected with the drain terminal of NMOS pipe N1 and the drain terminal of PMOS pipe P1; The source end of NMOS pipe N2 is connected with the source end of PMOS pipe P4, the drain terminal ground connection of PMOS pipe P4, and the grid end is connected with the drain terminal of NMOS pipe N2 and PMOS pipe P2;

The grid end of the grid end of NMOS pipe N1 and PMOS pipe P1 is connected with the drain terminal of NMOS pipe N7 by NMOS pipe N3: when the grid terminal potential of NMOS pipe N1 and PMOS pipe P1 is higher than the current potential of NMOS pipe N7 drain terminal, NMOS pipe N3 is a drain terminal with the end that the grid end of NMOS pipe N1 and PMOS pipe P1 is connected, otherwise then is the source end; The source end ground connection of NMOS pipe N7, the grid end is connected with the drain terminal of NMOS pipe N1 and PMOS pipe P1; The drain terminal of NMOS pipe N7 also is connected with bit line BL by NMOS pipe N5, and when the drain terminal voltage of NMOS pipe N7 was higher than the voltage of bit line BL, NMOS pipe N5 was a drain terminal with the end that NMOS pipe N7 drain terminal is connected, otherwise then is the source end;

The grid end of the grid end of NMOS pipe N2 and PMOS pipe P2 is connected with the drain terminal of NMOS pipe N8 by NMOS pipe N4, when the current potential of the grid end of NMOS pipe N2 and PMOS pipe P2 is higher than the current potential of NMOS pipe N8 drain terminal, NMOS pipe N4 is a drain terminal with the end that the grid end of NMOS pipe N2 and PMOS pipe P2 is connected, otherwise then is the source end; The source end ground connection of NMOS pipe N8, the grid end is connected with the drain terminal of NMOS pipe N2 and PMOS pipe P2; The drain terminal of NMOS pipe N8 is by NMOS pipe N6 and bit line

Connect, the drain terminal voltage of managing N8 as NMOS is higher than bit line

Voltage the time, it is drain terminal that NMOS pipe N6 and NMOS manage the end that the N8 drain terminal is connected, otherwise then is the source end;

The grid end of NMOS pipe N3, N4 is connected with write word line WWL, and the grid end of NMOS pipe N5, N6 is connected with word line WL.

The present invention overcomes the defective of prior art, and the sub-threshold storing unit circuit of a kind of low-power consumption, high robust is provided.The present invention can not increase dynamic power consumption and not reduce under the prerequisite of performance in the assurance system, reduces when realizing in dynamic operation and the static state operation leakage power, and every index of balanced memory cell makes the system performance optimization.

As the transistor that a harsh output is come, its source end and drain terminal can exchange.In conventional design especially digital circuit, because PMOS pipe often is used in pull-up circuit, NMOS often is used in pull-down circuit, thus their source end can fix be connected on supply voltage Vdd and ground gnd is motionless.But in design of the present invention, because characteristic that storage unit had: when write operation, the signal on bit line and bit line non-is written into storage unit; When read operation, the signal of storage unit inside is read out on bit line and bit line non-.Signal as the NMOS pipe N3, the N4 that mate pipe, N5, N6 two ends is dynamic change.And according to the definition of source transistor end, drain terminal: the output terminal of charge carrier is the source end, the receiving terminal of charge carrier is a drain terminal, though the concrete annexation of storage unit does not change, the port definition at transistor N3, N4, N5, N6 two ends can change the size variation of last current potential along with the storage unit internal information and with respect to paratope line.

Compared with prior art, the present invention has the following advantages and remarkable result:

(1) sub-threshold memory cell of the band self-adaptation leakage-current-interrupting mechanism of the present invention's design is when obtaining the leakage current performance boost, and dynamic power consumption and time for reading do not have any loss.That is the sub-threshold memory cell that the present invention proposes is not increasing dynamic power consumption and is not reducing under the prerequisite of performance, reduction when having realized in dynamic operation and the static state operation leakage power;

(2) in the sub-threshold memory cell of the limit leakage current that the present invention designs, NMOS pipe N7, N8 form buffer circuit in conjunction with N5, N6, this buffer circuit makes in the read operation process memory node and bit line discrete, the current potential of preliminary filling can not cause the rising of memory node current potential on the bit line, so problem of the most critical of subthreshold value SRAM design---read noise margin and be expanded, the diverse read schemes that just adopts among the present invention has improved the anti-noise ability that reads storage unit in the process, has strengthened the robustness of SRAM;

(3) subthreshold value zone overdrive voltage reduces, load capacitance is big and keep enough write capabilities under the condition of technique change is another challenge of sub-threshold memory cell design.Conventional method is further to reduce sub-threshold memory cell Vdd to write driving force with enhancing in the write operation process.Regrettably, this also reduces the stability of the maintenance operation of storage unit in other not selected row of sharing same supply voltage Vdd simultaneously.The present invention adopts the method that strengthens word line WL and WWL to strengthen and writes driving force, strengthens simultaneously and writes the logic driving force more weak to selected unit not reducing other storage unit stability of not read and write;

(4) mode of the logical organization of the employing of the invention change storage unit makes this design can all adopt the transistor of minimum dimension.Memory bank is the logical block that needs strict control area to consume.Six conventional transistor memory units are respectively formed the constraint condition that Lapie and unit ratio are gone up in the satisfied design of transistorized size by regulating under area-constrained condition, satisfy the yield demand of design.But the adjusting of simple dependence device size has been not enough to satisfy the yield demand of storage unit under the subthreshold value condition.The mode of the logical organization of the employing of the invention change storage unit improves design robustness satisfying under the area-constrained condition.The readability of the storage unit of band self-adaptation leakage-current-interrupting mechanism is guaranteed by buffer circuit (N5-N7, N6-N8); Writability is by configurable external control signal WL, and WWL guarantees.It is area-constrained that this makes that the design can all adopt the transistor of minimum dimension to satisfy memory circuit.

Description of drawings

Fig. 1 is the sub-threshold storing unit circuit structural drawing of low-power consumption of the present invention, high robust band self-adaptation leakage-current-interrupting mechanism.

Fig. 2 is the oscillogram of configurable control signal in the read-write operation of the present invention.

Fig. 3 be the present invention when on every bit line, connecting different number of memory cells read " 0 " operation the time oscillogram.

Fig. 4 is the graph of a relation of word line potential and write capability.

Fig. 5 is under the present invention analyzes in the Monte Carlo of 1000 samplings, and is past

Point is write the transient waveform figure of " 0 ".

Fig. 6 is the static average comparison diagram that keeps noise margin, (a) is traditional six transistor memory units, (b) is design of the present invention.

Fig. 7 is the comparison diagram that keeps noise margin under 10000 Monte Carlo sampling conditions, is with reference to the 10T storage unit (a), (b) designs for the present invention.

Fig. 8 be write signal of the present invention " 0 " extremely

The transient waveform figure of point.

Fig. 9 is the analog waveform figure of Writing/Reading of the present invention/maintenance operation.

Figure 10 is that (a) is with reference to 10T, (b) with reference to ST and (c) design stores unit static leakage current of the present invention and the dynamically comparison diagram of watt current.

Embodiment

Referring to Fig. 1, the storage unit circuit of the band self-adaptation leakage-current-interrupting mechanism of low-power consumption of the present invention, high robust is made up of 12 transistors: four PMOS pipe P1, P2, P3, P4 and eight NMOS pipe N1～N8, described transistor constitutes the sub-threshold storing unit circuit of both-end read-write, and described storage unit circuit is connected bit line BL and bit line

Between.

Wherein, the body end of four PMOS pipes is connected with supply voltage Vdd, the body end ground connection of eight NMOS pipes; The drain terminal of NMOS pipe N1 and grid end link together with drain terminal and the grid end of PMOS pipe P1 respectively, form first phase inverter; The drain terminal of NMOS pipe N2 and grid end link together with drain terminal and the grid end of PMOS pipe P2 respectively, form second phase inverter; First phase inverter connects into cross-couplings with second phase inverter: the grid end of NMOS pipe N1 grid end, PMOS pipe P1, the drain terminal of NMOS pipe N2 and the drain terminal of PMOS pipe P2 are connected, and the grid end of the drain terminal of the drain terminal of NMOS pipe N1, PMOS pipe P1, the grid end of NMOS pipe N2 and PMOS pipe P2 is connected; The source end of PMOS pipe P1, P2 is connected with supply voltage Vdd, and the source end of NMOS pipe N1 is connected with the source end of PMOS pipe P3, the drain terminal ground connection of PMOS pipe P3, and the grid end is connected with the drain terminal of NMOS pipe N1 and the drain terminal of PMOS pipe P1; The source end of NMOS pipe N2 is connected with the source end of PMOS pipe P4, the drain terminal ground connection of PMOS pipe P4, and the grid end is connected with the drain terminal of NMOS pipe N2 and PMOS pipe P2;

The grid end of the grid end of NMOS pipe N1 and PMOS pipe P1 is connected with the drain terminal of NMOS pipe N7 by NMOS pipe N3: when the grid terminal potential of NMOS pipe N1 and PMOS pipe P1 is higher than the current potential of NMOS pipe N7 drain terminal, NMOS pipe N3 is a drain terminal with the end that the grid end of NMOS pipe N1 and PMOS pipe P1 is connected, otherwise then is the source end; The source end ground connection of NMOS pipe N7, the grid end is connected with the drain terminal of NMOS pipe N1 and PMOS pipe P1; The drain terminal of NMOS pipe N7 also is connected with bit line BL by NMOS pipe N5, and when the drain terminal voltage of NMOS pipe N7 was higher than the voltage of bit line BL, NMOS pipe N5 was a drain terminal with the end that NMOS pipe N7 drain terminal is connected, otherwise then is the source end;

The grid end of the grid end of NMOS pipe N2 and PMOS pipe P2 is connected with the drain terminal of NMOS pipe N8 by NMOS pipe N4, when the current potential of the grid end of NMOS pipe N2 and PMOS pipe P2 is higher than the current potential of NMOS pipe N8 drain terminal, NMOS pipe N4 is a drain terminal with the end that the grid end of NMOS pipe N2 and PMOS pipe P2 is connected, otherwise then is the source end; The source end ground connection of NMOS pipe N8, the grid end is connected with the drain terminal of NMOS pipe N2 and PMOS pipe P2; The drain terminal of NMOS pipe N8 is by NMOS pipe N6 and bit line

Connect, the drain terminal voltage of managing N8 as NMOS is higher than bit line

Voltage the time, it is drain terminal that NMOS pipe N6 and NMOS manage the end that the N8 drain terminal is connected, otherwise then is the source end; The grid end of NMOS pipe N3, N4 is connected with write word line WWL, and the grid end of NMOS pipe N5, N6 is connected with word line WL.

Referring to Fig. 2, in the operating process of reality of the present invention, read operation is effectively to control turn-on transistor N5, N6 by word line WL signal, by read path N5-N7 and N6-N8 with the internal signal of storage unit be sent to paratope line to BL and

On, by the internal information of paratope line, finish the operating process that both-end is read, at this moment the WWL invalidating signal to last logical signal recognition memory cell.By word line WL and write word line WWL signal controlling, specific implementation is referring to Fig. 2 during write operation, and this moment, word line WL signal and write word line WWL were all effective, and matching transistor N3, N4, N5, N6 all are in opening.Bit line BL and bit line non-

On signal will be sent to internal node by matching transistor N3, N5 and N4, N6, change the information of storage unit inside, finish the operating process that both-end is write.

The principle of work of the sub-threshold storing unit circuit of low-power consumption of the present invention, high robust band self-adaptation leakage-current-interrupting mechanism is as follows:

1, read operation

In the design of memory bank, three static noise margins: read static noise margin, write static noise margin, keep reading the static noise margin minimum in the static noise margin.How to expand and read the bottleneck that static noise margin becomes the sub-threshold memory cell design.If can read Problem of Failure to the interference of unit node information with regard to solving by masking operation process neutrality line current potential, and then expansion read operation tolerance limit.In the sub-threshold memory cell of limit leakage current, N7, N8 form buffer circuit in conjunction with N5, N6, and it can guarantee in the read operation process that the information of memory cell storage is not destroyed, and then expands the static noise margin of reading of sub-threshold memory cell.The tie point of NMOS pipe N1 grid end and PMOS pipe P1 grid end is the Q point, and the tie point of NMOS pipe N2 grid end and PMOS pipe P2 grid end is

Point is supposed under the starting condition, Q=" 0 ",

In the read operation process, WWL is set to " 0 ", and WL is " 1 ".At this moment, coupling pipe N5, N6 opens and N3, N4 still are in off state.Consider Q=" 0 ",

Transistor N7 conducting all the time, when read operation, the electric charge that bit line BL goes up preliminary filling can discharge by N5 and N7, thereby reads Q point canned data like this.Discrete in view of memory node and bit line in this operating process, the current potential of preliminary filling can not cause the rising of memory node current potential on the bit line, the problem of the most critical of subthreshold value SRAM design---and read noise margin and be expanded.Be that the diverse read schemes that adopts among the design has improved the anti-noise ability that reads storage unit in the process, strengthened the robustness of SRAM.When Fig. 3 had showed the storage unit of series connection varying number on the every bit line, because the existence of buffer circuit N5-N7, N6-N8, Q point current potential was basicly stable, do not change with charges accumulated on the bit line.Simultaneously, this figure also proves absolutely, adopts the design can effectively reduce the failure phenomenon that reads of storage unit.

2, write operation

Subthreshold value zone overdrive voltage reduces, load capacitance is big and keep enough write capabilities under the condition of technique change is another challenge of sub-threshold memory cell design.Conventional method is further to reduce sub-threshold memory cell Vdd to write driving force with enhancing in the write operation process.Regrettably, this also reduces the maintenance operational stability of storage unit in other not selected row of sharing same Vdd simultaneously.Strengthen simultaneously and write the logic driving force more weak in order not reduce other storage unit stability of not read and write, and consider that the constraint of SRAM size and area, the present invention are adopted and strengthen word line WL and WWL and strengthen and write driving force selected unit.Making the required minimum wordline pulse width of the correct upset of storage unit is one of criterion of write capability.Fig. 4 shown for realizing and normally write required bit line current potential, and under the 200mV supply voltage, the gain of the small voltage by giving a 50.41mV of word line just can make the write capability of this design be guaranteed.

Fig. 5 has showed in taking into full account wafer between deviation and wafer that under the condition of deviation, the Monte Carlo sampled result that the instantaneous emulation of write operation is 1000 times is entirely true.This figure has fully proved under 200mV supply voltage condition, adopts the word line (strengthening 50mV) that strengthens can fully guarantee the write capability of the design's sub-threshold memory cell.In other words, the design of enhancing word line can guarantee the driving force of write circuit under the condition of process deviation and noise.The design's good reliability, need not increases extra auxiliary circuit, has simplely, and the system management power consumption is less, the characteristics that area consumption is little.

3, keep operation

Keeping operating period, WL is set to " 0 " and WWL is " 1 ".Coupling pipe N5, N6 turn-off information on the bit line and cell stores information isolation.Coupling pipe N3, N4 unlatching, the information N3-N7 or the N4-N8 that preserve according to storage unit form the current path of power supply to ground, and assurance has the ability that drags down current potential of the node of " 0 ".

Reading static noise margin is the crucial noise margin of conventional storage unit.In the subthreshold value zone, because rapid deterioration, the memory node of storage unit is more vulnerable to the influence of bit line potential fluctuation.For addressing this problem, the design's sub-threshold memory cell adopts transistor N5-N7, and N6-N8 forms buffer circuit.This buffer circuit can be with the information isolation on memory node and the bit line in concrete read operation process Ion/Ioff, so the extension storage unit read static noise margin.Keep static noise margin to become the crucial noise margin of the design's storage unit like this.Fig. 6 has showed the comparison of the crucial noise margin of design of the present invention and traditional 6T design, and obviously the design has more excellent crucial noise margin.

Preamble is by the agency of, is keeping operating period, and WL is set to " 0 ", and WWL enables.In this process, because N3 and N4 are in opening.Concrete according to storage unit like this canned data, N3-N7 or N4-N8 will form a DC channel to ground, strengthen the current potential ability that drags down that has " 0 " node.Accordingly, also guaranteed the static state maintenance tolerance limit of the storage unit that the present invention proposes.Fig. 7 is illustrated in respectively under the condition of considering process deviation and device mismatch, and people such as C.Ik Joon are published in a illiteracy Taka sieve analysis result that keeps static noise margin to sample for 10000 times with reference to 10T design and the design among the IEEE.Can know from figure and see, compare that the storage unit of the present invention's design demonstrates better maintenance tolerance limit with reference 10T storage unit.

4, the storage unit of band self-adaptation leakage-current-interrupting mechanism

Verified in relevant document, reduce the reduction dynamic energy consumption that supply voltage can be quadratic term.If but further reduce supply voltage Vdd to Vdd＜V _OPTCan cause leaking the increase of energy consumption, this is because postpone the increase of the index along with the reduction of supply voltage, thereby has increased total leakage energy consumption.In present System on Chip/SoC design (comprising medical chip), memory bank (SRAM Array) occupies sizable area.Simultaneously, each storage unit of the functional requirement of memory bank needs long-time (being long-time arbitrarily in theory) to keep data.The quiescent dissipation of restriction SRAM memory bank has become a key and very important problem.Introduced the superthreshold state limit leakage current scheme of typical case's six pipe memory banks down in the relevant document.Leakage current when regrettably, present nearly all subthreshold value design does not all have to consider to reduce dynamic operation and static state operation.The present invention proposes a sane subthreshold value sram cell, it can realize the minimizing of dynamic operation (read/write operation) and static state operation leakage current simultaneously under the prerequisite that does not increase dynamic energy consumption and performance loss.

$I_{\mathrm{sub}}=I_{\mathrm{<figure-callout\; id="0"\; label="sub"\; filenames="HSA00000411277700012.png,HSA00000411277700021.png"\; state="\{\{state\}\}">sub</figure-callout>}0}\&CenterDot;e^{\frac{(V_{\mathrm{GS}}-V_{\mathrm{th}}+{\mathrm{\&eta;V}}_{\mathrm{DS}}-{\mathrm{\&gamma;V}}_{\mathrm{SB}})}{{\mathrm{nV}}_T}}(1-e^{\frac{-\left(V_{\mathrm{DS}}\right)}{V_T}})$ 2 (formula one)

$I_{\mathrm{sub}}{I}_{\mathrm{<figure-callout\; id="0"\; label="sub"\; filenames="HSA00000411277700012.png,HSA00000411277700021.png"\; state="\{\{state\}\}">sub</figure-callout>}0}\&CenterDot;e^{\frac{(V_{\mathrm{GS}}-V_{\mathrm{th}}+{\mathrm{\&eta;V}}_{\mathrm{DS}}-{\mathrm{\&gamma;V}}_{\mathrm{SB}})}{{\mathrm{nV}}_T}}(1-e^{\frac{-\left(V_{\mathrm{DS}}\right)}{V_T}})$ (formula two)

Wherein n is a subthreshold value amplitude of oscillation parameter, and η is the DIBL coefficient, and γ is a body-effect coefficient, V _GSBe gate source voltage, V _DSBe drain-source voltage, V _TBe thermal voltage kT/q, its value at room temperature approximates 26mV greatly.I _Sub0Be V _GS=V _Th, the specific currents that obtains under the W/L=1 condition, T is an environment temperature.V _Th0Be the threshold voltage of substrate bias when being " 0 ", V _SBBe the source body bias, 2 φ _FBe surface potential.

Shown in formula one, the principle that self-adaptation is cut off pipe limit leakage current is: subthreshold value zone drain-source current is along with V _GSBe exponential variation with poor (the device overdrive voltage) of transistorized threshold voltage.Suppose Q=under the starting condition " 0 " and

=" 1 ".For " 0 " is write ingress

Bit line BL and bit line

Be changed to " 1 " and " 0 " respectively.Word line WL and WWL become high level, and transistor N3-N6 opens, node

Be discharged to " 0 " current potential, transistor P2 opens, and transistor N2 turn-offs.Accordingly, Q is charged to " 1 " current potential.It should be noted that the V of N1 in this instantaneous operating process _GSIncrease gradually.Finally because N1 is in conducting state, QL point current potential be reduced to and

The point current potential identical (referring to Fig. 1), this make transistor P3 the source end with

End is connected on electricity, and promptly the write operation gate source voltage of finishing moment P3 equals " 0 ", and P3 is transformed into off state, as shown in Figure 8.Formula two is pointed out, if transistorized source body (source is with respect in the body) voltage is not equal to " 0 " (V _SB≠ 0), then

That is this storage unit is in write operation moment operate as normal.In case write operation is finished, the leakage of P3, source electric current are just along with | V _Th| _P3Growth be exponential reduction.Meanwhile, the V of P4 _GSFrom " 0 " become one on the occasion of, according to leakage-source electric current of formula one P4 also with V _GSIncrease be exponential reduction, require V for PMOS transistor opening _GS＜V _Thp, V wherein _GS＜0, V _Thp＜0.

Analog result shown in Figure 9 shows, during read operation and static state operation, QL and

In which can be elevated to positive voltage Δ V (Δ V ') and depends on canned data in the storage element.According to formula one and formula two, consider QL and

Current potential to the V of transistor N1, N2, P3 and P4 _GS, V _SB, | V _Th| influence, the leakage current of the storage unit of flowing through will along with QL and

The reduction that is changed significantly of current potential.Analog result shows, during read operation and static state operation because

The minimizing of the leakage current that causes of increase greater than the influence of transistor parallel connection.Therefore, in the scheme that the present invention proposes, the leakage current in read operation and the static state operation is significantly reduced.

Cut off pipe as self-adaptation, PMOS pipe P3 and P4 can dynamically adjust running status according to the transient operation of memory circuit and limit the leakage current operation.It should be noted that, in self-adaptation limit leakage current of the present invention operating process, both need not additionally additional auxiliary switch help system and entered the also not extra load of introducing on bit line of leakage current shutdown mode, the sub-threshold memory cell of the present invention's design is when obtaining the leakage current performance boost, and dynamic power consumption and time for reading do not have any loss.That is the sub-threshold memory cell that the present invention proposes is not increasing dynamic power consumption and is not reducing under the prerequisite of performance, reduction when having realized in dynamic operation and the static state operation leakage power.

Be the low-power consumption characteristic of investigation the design storage unit of justice, the present invention has realized that under the same process condition people such as C.IkJoon are published in a among the IEEE and are published in a design with reference to ST among the IEEE with reference to people such as 10T design and J.P.Kulkarni.Consider that the word-line signal that the present invention designs is provided by an extra power supply, the memory cell current consumption of comparison of the present invention is meant: electric current by supply voltage Vdd and bit line BL and

The electric current sum.Figure 10 shown with reference to 10T, with reference to the static leakage current of ST and the design's storage unit and dynamically watt current in the distribution situation of considering under process deviation and the device mismatch condition.At first, the design's static leakage current mean value is respectively than the static leakage current mean value little 9.0% and 55.59% of reference 10T and ST storage unit.Secondly, average current with reference to 10T and the dynamic watt current of ST storage unit is respectively 592.845pA and 224.567pA, and the design's storage unit dynamic watt current when 200mV is 154.619pA, is significantly less than the current sinking of storage unit in the list of references.This has fully proved than the storage unit of reference 10T only can reduce static leakage current, the leakage current when the design can reduce dynamic operation and static state operation simultaneously.It should be noted that with the 10T of reference and compare that the present invention's design demonstrates following characteristics: the standard deviation of leakage current has reduced 90.0% and 30.38% respectively during (1) static state operation with the ST storage unit; (2) standard deviation of leakage current has reduced 21.11% and 58.78% respectively during dynamic operation.This explanation is the sub-threshold memory cell design equally, and the present invention's design has better technology robustness.

Claims (1)

1. storage unit circuit with self-adaptation leakage-current-interrupting mechanism, it is characterized in that: be provided with four PMOS pipe P1～P4 and eight NMOS pipe N1～N8, described transistor constitutes the sub-threshold storing unit circuit of both-end read-write, and described storage unit circuit is connected bit line BL and bit line

Between;

Wherein, the body end of four PMOS pipes is connected with supply voltage Vdd, the body end ground connection of eight NMOS pipes; The drain terminal of NMOS pipe N1 and grid end link together with drain terminal and the grid end of PMOS pipe P1 respectively, form first phase inverter; The drain terminal of NMOS pipe N2 and grid end link together with drain terminal and the grid end of PMOS pipe P2 respectively, form second phase inverter; First phase inverter connects into cross-couplings with second phase inverter: the grid end of NMOS pipe N1 grid end, PMOS pipe P1, the drain terminal of NMOS pipe N2 and the drain terminal of PMOS pipe P2 are connected, and the grid end of the drain terminal of the drain terminal of NMOS pipe N1, PMOS pipe P1, the grid end of NMOS pipe N2 and PMOS pipe P2 is connected; The source end of PMOS pipe P1, P2 is connected with supply voltage Vdd, and the source end of NMOS pipe N1 is connected with the source end of PMOS pipe P3, the drain terminal ground connection of PMOS pipe P3, and the grid end is connected with the drain terminal of NMOS pipe N1 and the drain terminal of PMOS pipe P1; The source end of NMOS pipe N2 is connected with the source end of PMOS pipe P4, the drain terminal ground connection of PMOS pipe P4, and the grid end is connected with the drain terminal of NMOS pipe N2 and PMOS pipe P2;

The grid end of the grid end of NMOS pipe N1 and PMOS pipe P1 is connected with the drain terminal of NMOS pipe N7 by NMOS pipe N3: when the grid terminal potential of NMOS pipe N1 and PMOS pipe P1 is higher than the current potential of NMOS pipe N7 drain terminal, NMOS pipe N3 is a drain terminal with the end that the grid end of NMOS pipe N1 and PMOS pipe P1 is connected, otherwise then is the source end; The source end ground connection of NMOS pipe N7, the grid end is connected with the drain terminal of NMOS pipe N1 and PMOS pipe P1; The drain terminal of NMOS pipe N7 also is connected with bit line BL by NMOS pipe N5, and when the drain terminal voltage of NMOS pipe N7 was higher than the voltage of bit line BL, NMOS pipe N5 was a drain terminal with the end that NMOS pipe N7 drain terminal is connected, otherwise then is the source end;

The grid end of the grid end of NMOS pipe N2 and PMOS pipe P2 is connected with the drain terminal of NMOS pipe N8 by NMOS pipe N4, when the current potential of the grid end of NMOS pipe N2 and PMOS pipe P2 is higher than the current potential of NMOS pipe N8 drain terminal, NMOS pipe N4 is a drain terminal with the end that the grid end of NMOS pipe N2 and PMOS pipe P2 is connected, otherwise then is the source end; The source end ground connection of NMOS pipe N8, the grid end is connected with the drain terminal of NMOS pipe N2 and PMOS pipe P2; The drain terminal of NMOS pipe N8 is by NMOS pipe N6 and bit line

Connect, the drain terminal voltage of managing N8 as NMOS is higher than bit line

Voltage the time, it is drain terminal that NMOS pipe N6 and NMOS manage the end that the N8 drain terminal is connected, otherwise then is the source end;

The grid end of NMOS pipe N3, N4 is connected with write word line WWL, and the grid end of NMOS pipe N5, N6 is connected with word line WL.

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