CN102163971B - Pll circuit - Google Patents
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- CN102163971B CN102163971B CN2011100399130A CN201110039913A CN102163971B CN 102163971 B CN102163971 B CN 102163971B CN 2011100399130 A CN2011100399130 A CN 2011100399130A CN 201110039913 A CN201110039913 A CN 201110039913A CN 102163971 B CN102163971 B CN 102163971B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/03—Digital function generators working, at least partly, by table look-up
- G06F1/0321—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
- G06F1/0328—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers in which the phase increment is adjustable, e.g. by using an adder-accumulator
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Abstract
Provided is a PLL circuit improving reliability while suppressing power consumption without degrading noise characteristics. The PLL circuit includes a PLL IC that divides an output frequency Fout from a VCO, compares phase with a reference signal, and feeds back a phase difference as a control voltage to the VCO. A control circuit is capable of finely setting both of a reference frequency Fref and an output frequency Fdds in a DDS circuit, and the DDS circuit generates folding signals of Fdds for Fref and an integral multiple frequency thereof based on the combination of the frequencies. A first AMP amplifies a signal, a variable filter selects a desired Fdds (desired) and a second AMP amplifies the signal and supplies the same to the PLL IC as a reference signal. The control circuit further supplies a division ratio N to the PLL IC.
Description
Technical field
(Phase Locked Loop: circuit phase-locked loop) particularly relates to the PLL circuit that need not to make the noise characteristic deterioration, improves reliability with regard to suppressing to consume electric power to the present invention relates to PLL.
Background technology
[PLL circuit in the past: Fig. 9]
With reference to Fig. 9 in the past PLL circuit is described.Fig. 9 is the structure chart of PLL circuit in the past.
Voltage-controlled oscillator) 1, PLL IC (PLL IntegratedCircuit: phase comparison unit) 2, analog filter 3, reference oscillator 4, DDS (DirectDigital Synthesizer: Direct Digital Frequency Synthesizers) circuit 5, control circuit 6 as shown in Figure 9, PLL circuit in the past is by constituting with the lower part: VCO (VoltageControlled Oscillator:.
VCO1 is according to exporting desirable oscillation frequency Fout from the control voltage of analog filter 3 outputs.
PLL IC2 input frequency of oscillation Fout utilizes from the set point of the frequency dividing ratio of control circuit 6 supplies, carries out frequency division with the output frequency Fdds from DDS circuit 5 as reference signal (clock), and crossover frequency is outputed to analog filter 3.
3 pairs of crossover frequencies from PLL IC2 of analog filter are carried out smoothing and are exported as the control voltage of VCO1.
[action of PLL circuit in the past]
In PLL circuit in the past, 6 couples of PLL IC2 of control circuit and 5 outputs of DDS circuit become the such data (setting data of frequency dividing ratio, Fdds select signal) of channel (frequency) of the regulation in the system that the PLL circuit is used as oscillator, and set.
PLL IC2 determines frequency dividing ratio, count value according to setting data, the Fdds of output frequency arbitrarily that DDS circuit 5 decision is used as the reference signal of PLL IC2.Thus, VCO output becoming assigned frequency Fout.
[correlation technique]
In addition, as relevant prior art, Japanese kokai publication hei 07-131343 communique " cycle シ Application セ サ イ ザ " (applicant: [patent documentation 1], TOHKEMY 2007-208367 communique " same period, signal generating apparatus, send Xin Machine and び system were driven method " (applicant: [patent documentation 2], TOHKEMY 2002-141797 communique " cycle シ Application セ サ イ ザ " (applicant: Mitsubishi Electric Corporation) [patent documentation 3] Kenwood Corp .) Icom Inc.) is arranged.
Following content is disclosed in patent documentation 1: in frequency synthesizer, in memory at the group of each output frequency Memory Reference frequency switching signal and DDS output frequency switching signal, when the PLL circuit has locked, unwanted wave component is limited to by outside the frequency band.
Following content is disclosed in patent documentation 2: in synchronization signal generation device, adjust output frequency/incoming frequency, frequency divider (1/M frequency dividing ratio M a a), the Clock Multiplier Factor M b of frequency multiplier (* M b) of frequency dividing ratio N, the DDS of frequency divider (1/N), become the indication frequency so that send ripple, and the parasitic signal in the output that is combined in DDS of incoming frequency among the DDS and output frequency is made as below the specified level.
In patent documentation 3, disclose following content: in frequency synthesizer, before output input phase synchronous ring, make it changeable frequency mode filter, and the centre frequency of this filter is changed and the removal parasitic signal by narrow-band with DDS.
Summary of the invention
In PLL circuit in the past, under the situation about using being used as synthesizer, make multichannel output become possibility by the setting that changes DDS circuit output frequency Fdds, PLL IC, but there is the upper limit in the frequency Fdds that can export as DDS, in order to improve frequency of oscillation Fout, need to improve the frequency dividing ratio in the PLL IC.
But,, have the problem that makes the noise characteristic deterioration of utilizing Fdds and obtaining by improving the frequency dividing ratio in the PLL IC.
For example, be under 100 the situation establishing frequency dividing ratio, can follow the deterioration of 20l0g100=40dB.
In addition, raising DDS circuit output frequency itself has also increased the consumption electric power as circuit, thereby has the problem of the reliability reduction of PLL circuit.
In addition, at patent documentation 1,2, in 3, not to utilize overlapping frequency at the Fdds of reference frequency and frequency multiplication frequency thereof to generate Fdds (hope) and the structure of selecting desired frequency.
The present invention makes in view of above-mentioned actual state, and purpose is to provide a kind of PLL circuit of making the power noise deterioration in characteristics, improving reliability with regard to suppressing to consume electric power of need not.
The present invention who is used to solve the problem of above-mentioned existing example is a kind of PLL circuit, have voltage-controlled oscillator and phase comparison unit, this phase comparison unit carries out frequency division to the output of voltage-controlled oscillator and compares with the phase place of reference signal, will be based on the signal of phase difference as the control voltage of voltage-controlled oscillator and export, this PLL circuit has: reference oscillator, and select signal to be made as reference frequency variable and output according to reference frequency; The DDS circuit, according to from the output index signal of outside and output signal output, and output needle is to the overlapped signal of the output signal of the frequency multiplication frequency of reference frequency and this frequency according to the reference frequency of being imported; The 1st amplifier utilizes from the 1st of outside input and amplifies set point to amplifying from the output signal of DDS circuit; Variable filter is made as frequency variablely by frequency band according to the variable frequency set point from outside input, pass through and make from the output signal of the 1st amplifier; The 2nd amplifier utilizes from the 2nd amplification set point of outside input the output signal from variable filter is amplified, and outputs to phase comparison unit as reference signal; And control circuit, if imported the index signal that reference signal is made as desirable frequency, then select signal corresponding to the reference frequency of this index signal to reference oscillator output, to the output index signal of DDS circuit output corresponding to this index signal, amplify set point to the output of the 1st amplifier corresponding to the 1st of this index signal, to the variable frequency set point of variable filter output corresponding to this index signal, amplify set point to the output of the 2nd amplifier corresponding to the 2nd of this index signal, to phase comparison unit output frequency division ratio, because the PLL circuit has said structure, so have following effect: can be meticulous and in wide scope, generate and select desirable reference signal, need not to make the noise characteristic deterioration, the reliability that improves circuit with regard to suppressing to consume electric power.
The present invention is in above-mentioned PLL circuit, and for reference signal being made as desirable frequency, control circuit output is made as variable reference frequency with these both sides of output signal in reference frequency in the reference oscillator and the DDS circuit and selects signal and output index signal.
The present invention is in above-mentioned PLL circuit, for reference signal being made as desirable frequency, control circuit makes the overlapping frequency that generates output signal in the DDS circuit at the frequency multiplication frequency of reference frequency and this frequency, and output variable frequency set point, select desirable frequency to utilize variable filter.
The present invention is in above-mentioned PLL circuit, and control circuit has: the frequency form, and the Memory Reference frequency is selected signal and output index signal corresponding to the index signal of being imported; The corresponding form of set point is stored the 1st corresponding to index signal and is amplified set point, the 2nd amplification set point, variable frequency set point, frequency dividing ratio; And control part, export corresponding reference frequency selection signal and output index signal with reference to the frequency form at the input of index signal, export corresponding the 1st amplification set point, the 2nd and amplify set point, variable frequency set point, frequency dividing ratio with reference to the corresponding form of set point.
The present invention is a kind of PLL circuit, have voltage-controlled oscillator and phase comparison unit, this phase comparison unit carries out frequency division to the output of voltage-controlled oscillator and compares with the phase place of reference signal, will be based on the signal of phase difference as the control voltage of described voltage-controlled oscillator and export, this PLL circuit has: reference oscillator, and select signal and be made as reference frequency variable and output according to reference frequency; The DDS circuit, according to from the output index signal of outside and output signal output, and output needle is to the overlapped signal of the output signal of the frequency multiplication frequency of reference frequency and this frequency according to the reference frequency of being imported; The 1st amplifier utilizes from the 1st of outside input and amplifies set point to amplifying from the output signal of DDS circuit; A plurality of filters have different separately frequencies and pass through frequency bandwidth characteristics; The 1st switch is selected a plurality of filters according to the selection signal of importing from the outside, and will be outputed in this selected filter from the output signal of the 1st amplifier; The 2nd switch is selected selected filter according to the selection signal of importing from the outside, and output is from the output signal of this filter; The 2nd amplifier utilizes from the 2nd of outside input and amplifies set point to amplifying from the output signal of the 2nd switch, and outputs to phase comparison unit as reference signal; And control circuit, if imported the index signal that reference signal is made as desirable frequency, then select signal corresponding to the reference frequency of this index signal to reference oscillator output, to the output index signal of DDS circuit output corresponding to this index signal, amplify set point to the output of the 1st amplifier corresponding to the 1st of this index signal, amplify set point to the output of the 2nd amplifier corresponding to the 2nd of this index signal, to the selection signal of the 1st switch and the 2nd switch output corresponding to this index signal, to phase comparison unit output frequency division ratio, because the PLL circuit has said structure, so have following effect: can be meticulous and in wide scope, generate and select desirable reference signal, need not to make the noise characteristic deterioration, the reliability that improves circuit with regard to suppressing to consume electric power.
The present invention is in above-mentioned PLL circuit, and for reference signal being made as desirable frequency, control circuit output is made as variable reference frequency selection signal and output index signal with the both sides of the output signal in reference frequency in the reference oscillator and the DDS circuit.
The present invention is in above-mentioned PLL circuit, for reference signal being made as desirable frequency, control circuit makes the overlapping frequency that generates output signal in the DDS circuit at the frequency multiplication frequency of reference frequency and this frequency, and output selection signal, select desirable frequency to utilize the 1st switch and the 2nd switch.
The present invention is in above-mentioned PLL circuit, and control circuit has: the frequency form, and the Memory Reference frequency is selected signal and output index signal corresponding to the index signal of being imported; The corresponding form of set point is stored the 1st corresponding to index signal and is amplified set point, the 2nd amplification set point, selection signal, frequency dividing ratio; And control part, export corresponding reference frequency selection signal and output index signal with reference to the frequency form at the input of index signal, export corresponding the 1st amplification set point, the 2nd and amplify set point, select signal, frequency dividing ratio with reference to the corresponding form of set point.
Description of drawings
Fig. 1 is the structure chart of 1PLL circuit.
Fig. 2 is the figure that the structure example of DDS circuit is shown.
Fig. 3 is the figure that the example 1 of variable filter is shown.
Fig. 4 is the figure that the example 2 of variable filter is shown.
Fig. 5 is the figure that the example of resulting Fdds (hope) is shown.
Fig. 6 is the structure chart of control circuit.
Fig. 7 is the control part flow chart.
Fig. 8 is the structure chart of the PLL circuit in the 2nd execution mode.
Fig. 9 is the structure chart of PLL circuit in the past.
Description of reference numerals
1...VCO, 2...PLL IC, 3... analog filter, 4... reference oscillator, 5...DDS circuit, 6... control circuit, 7... the 1st amplifier (AMP), 8... variable filter, 8a... filter, 8b... filter, 8c... filter, 9... the 2nd amplifier (A M P), 10a... the 1st switch (SW (1)), 10b... the 2nd switch (SW (2)), 51... adder, 52... bistable multivibrator (flip-flop), 53... sinusoidal wave form, 54... digital/analog converter (DAC), 55... filter, 61... control part, 62... frequency form, 63... corresponding form such as set point
Embodiment
With reference to accompanying drawing embodiments of the present invention are described.
[summary of execution mode]
PLL circuit in the embodiments of the present invention, if set the output frequency Fdds of DDS circuit at reference frequency Fref, then produce Fref ± Fdds, Fref * 2 ± Fdds, Fref * 3 ± Fdds,, such overlapping frequency component.In this PLL circuit, utilize these overlapping frequency components, can be made as Fref and Fdds variable and obtain desired Fdds (hope) by its combination.
[1PLL circuit: Fig. 1]
With reference to Fig. 1 the PLL circuit (1PLL circuit) in the of the present invention the 1st the execution mode is described.Fig. 1 is the structure chart of 1PLL circuit.
As shown in Figure 1, the 1PLL circuit has VCO1, PLL IC2, analog filter 3, reference oscillator 4, DDS circuit 5, control circuit the 6, the 1st amplifier (AMP) 7, variable filter (Filter) the 8, the 2nd amplifier (AMP) 9.
[each several part]
Each several part to the 1PLL circuit describes.
VCO1 is according to exporting desirable oscillation frequency Fout from the control voltage of analog filter 3 outputs.
PLL IC2 is phase comparator or a phase comparison unit as described below: input frequency of oscillation Fout, utilization is from the set point of the frequency dividing ratio of control circuit 6 supplies, with from DDS circuit 5 via the 2nd amplifier 9 and the output frequency Fdds (hope) of output carries out frequency division as reference signal (clock), and crossover frequency is outputed to analog filter 3.
3 pairs of crossover frequencies from PLL IC2 of analog filter are carried out smoothing, and as the control voltage of VCO1 and export.
At this, in DDS circuit 5, not only generate Fdds, also be created on reference frequency Fref and the frequency multiplication frequency Fref * N thereof ± the overlapping frequency of Fdds, these frequency signals also output to the 1AMP7 from DDS circuit 5.
Internal structure, contents processing about control circuit 6 will be in the back explanations.
The 1st amplifier (AMP) 7 is used to amplify corresponding to the signal of selection from the output signal of DDS circuit 5 from the amplification set point 1 of control circuit 6.
Variable filter 8 will be made as variable by frequency band according to the variable frequency set point from control circuit 6, the signal (selected signal) from 1AMP7 is passed through, and be input among the 2AMP9.
The 2nd amplifier (AMP) 9 is used to amplify corresponding to the signal of selection from the output signal of variable filter 8 from the amplification set point 2 of control circuit 6.
[DDS circuit: Fig. 2]
Next, with reference to Fig. 2 DDS circuit 5 is described.Fig. 2 is the figure that the structure example of DDS circuit is shown.
As shown in Figure 2, DDS circuit 5 is made of adder 51, bistable multivibrator 52, sinusoidal wave form 53, digital/analog converter (DAC) 54, filter 55.
To bistable multivibrator 52 and DAC54 input based on sampling clock from the reference frequency Fref of reference oscillator 4.
51 pairs of adders are carried out add operation and are outputed to bistable multivibrator 52 from the frequency setting value of control circuit 6 inputs with from the output valve of bistable multivibrator 52.
DAC54 uses sampling clock that the list data from sinusoidal wave form 53 is carried out analog converting and outputs in the filter 55.
Filtering is carried out in 55 pairs of outputs from DAC54 of filter, and outputs among the 1AMP7 as simulation/sine wave.
[variable filter: Fig. 3,4]
Next, describe with reference to Fig. 3,4 pairs of variable filters 8.Fig. 3 is the figure that the example 1 of variable filter is shown, and Fig. 4 is the figure that the example 2 of variable filter is shown.
As shown in Figure 3, variable filter 1 between input terminal and lead-out terminal, be connected in series varicap D, capacitor C, coil L, apply power supply Vc via resistance R 1 between varicap D and capacitor C, an end of resistance R 2 is connected other end ground connection with the input section.
In addition, as shown in Figure 4, variable filter 2 is based on variable filter 1, the end of coil L2 is connected other end ground connection with the input section, in addition, the end of capacitor C2 is connected with input section and the other end is connected the cathode side of diode D2, the anode-side ground connection of diode D2, between capacitor C2 and diode D2, connect voltage Vc1 via resistance R 2.In addition, also have and the identical structure of input section at deferent segment.
[example of Fdds (hope): Fig. 5]
Next, utilize the example of the Fdds (hope) that Fig. 5 obtains the combination by Fref and Fdds to describe.Fig. 5 illustrates the figure of the example of resulting Fdds (hope).
In Fig. 5, the example of the overlapping frequency that is taken place when establishing Fref and be fixed as 40MHz, making Fdds to change from 10MHz to 20MHz with the stepping of 1MHz is shown.
In the past, under the situation that Fdds is changed, only can obtain 10～20MHz.Relative therewith, in the example of Fig. 5, utilized at the frequency multiplication frequency of 40MHz and 40MHz ± situation of the overlapping frequency of Fdds under, can obtain Fdds (hope) frequency of 20MHz～30MHz, 50MHz～70MHz etc. with the stepping of 1MHz.
In addition, according to purposes, can be meticulous and in wide region, obtain Fdds (hope) by the amplitude of variation of Fdds being changed 100kHz, 10kHz etc. and changing Fref.
In addition, variable filter 8 is set, is provided with 1AMP7,2AMP9 for the incoming level that improves PLL IC2 for the selection precision that improves Fdds (hope).
[control circuit: Fig. 6]
Next, with reference to Fig. 6 control circuit 6 is described.Fig. 6 is the structure chart of control circuit.
As shown in Figure 6, control circuit 6 has corresponding forms 63 such as control part 61, frequency form 62, set point basically.
Wherein, said Fdds (hope) index signal is the index signal that the setting person of PLL circuit is used to obtain Fdds (hope).
It is the signal that is used for determining at the reference frequency Fref of reference oscillator 4 vibrations that Fref selects signal.
The Fdds index signal is the signal of specifying the Fdds in the DDS circuit 5.
The variable frequency set point is corresponding to the variable frequency set point in the variable filter 8 of Fdds (hope).
Frequency dividing ratio N represents corresponding to the frequency dividing ratio among the PLL IC2 of Fdds (hope).
62 storages of frequency form are selected the value of signal, the value of Fdds index signal corresponding to the Fref of Fdds (hope) index signal, and particularly, corresponding relation shown in Figure 5 is for obtaining the form of Fref and Fdds according to Fdds (hope).As mentioned above, Fref and Fdds can both set its value subtly.
Corresponding form 63 such as set point stores in advance at Fdds (hope) index signal and amplifies set point 1,2, variable frequency set point, frequency dividing ratio N.
[control part flow process: Fig. 7]
Next, with reference to Fig. 7 the processing in the control part 61 is described.Fig. 7 is the flow chart of control part.
If imported Fdds (hope) index signal (S1) from outside (operator or setting person), then control part 61 is determined Fref, Fref * N, Fdds (S2) with reference to frequency form 62, and select signal to output to (S3) in the reference oscillator 4 Fref, the Fdds index signal is input to (S4) in the DDS circuit 5.
In addition, control part 61 with reference to corresponding forms 63 such as set point to AMP7,9 outputs corresponding to Fdds (hope) to AMP7,9 amplification set point (S5).
And then the variable frequency set point (S6) that control part 6 is exported corresponding to Fdds (hope) to variable filter 8 with reference to corresponding forms 63 such as set points is to the frequency dividing ratio N (S7) of PLL IC2 output corresponding to Fdds (hope).
[2PLL circuit: Fig. 8]
Next, with reference to Fig. 8 the PLL circuit (2PLL circuit) in the 2nd execution mode is described.Fig. 8 is the structure chart of the PLL circuit in the 2nd execution mode.
As shown in Figure 8, as the part different with 1PLL circuit shown in Figure 1, be that the 2nd PLL circuit is not provided with variable filter 8 and is provided with a plurality of filter 8a, 8b, 8c, the 1st switch (SW (the 1)) 10a that is used to select these filters, the 2nd switch (SW (2)) 10b this point.
In addition, in Fig. 1,6 pairs of variable filters 8 of control circuit have been exported the variable frequency set point, but in Fig. 8, the index signal that 6 couples of SW (1) 10a of control circuit and SW (2) 10b output filter are selected.
In Fig. 8,3 filter 8a～8c are shown, but both can be 2, also can be more than 4.
[different each several parts]
Each several parts different with the 1PLL circuit in the 2PLL circuit is described.
1AMP7 amplifies output to SW (1) 10a output.
SW (1) 10a is to according to the amplifying signal of selecting the selected filter output of signal from 1AMP7 from the filter of control circuit 6.
SW (2) 10b selects from according to selecting the output of the selected filter of signal from the filter of control circuit 6, and outputs among the 2AMP9.
2AMP9 is to amplifying from the output of SW (2) 10b and outputing among the PLL IC2 as Fdds (hope).
Then, 6 couples of SW (1) 10a of control circuit and SW (2) 10b output selects the filter of employed filter to select index signal.
Therefore, in the structure in control part, in corresponding forms 63 such as set point, substitute the variable frequency set point and store the filter selection index signal that is used for selecting employed filter at 2 switches, control part 61 with reference to corresponding forms 63 such as set points, is selected index signal to 2 SW output filters at Fdds (hope) index signal.
[effect of execution mode]
PLL circuit in the embodiments of the present invention, by accomplishing to set subtly Fref and these both sides' of Fdds value, thereby the combination by both generates Fdds (hope) meticulous and that wide region is interior, select desired Fdds (hope) by variable filter 8 or a plurality of filter 8a～8c, and offer PLL IC2, so have following effect: need not to make the noise characteristic deterioration, just can suppress the consumption electric power of PLL circuit, thereby improve the reliability of circuit by the consumption electric power that suppresses DDS circuit 5.
The present invention is applicable to the PLL circuit that need not to make the noise characteristic deterioration, improves reliability with regard to suppressing to consume electric power.
Claims (6)
1. PLL circuit, have voltage-controlled oscillator and phase comparison unit, this phase comparison unit carries out frequency division to the output of described voltage-controlled oscillator and compares with the phase place of reference signal, will be based on the signal of phase difference as the control voltage of described voltage-controlled oscillator and export, this PLL circuit is characterised in that to have:
Reference oscillator selects signal to be made as reference frequency variable and output according to reference frequency;
The DDS circuit, according to from the output index signal of outside and output signal output, and output needle is to the overlapped signal of the output signal of the frequency multiplication frequency of described reference frequency and this frequency according to the reference frequency of being imported;
The 1st amplifier utilizes from the 1st of outside input and amplifies set point to amplifying from the output signal of described DDS circuit;
Variable filter is made as frequency variablely by frequency band according to the variable frequency set point from outside input, pass through and make from the output signal of described the 1st amplifier;
The 2nd amplifier utilizes from the 2nd amplification set point of outside input the output signal from described variable filter is amplified, and outputs to described phase comparison unit as reference signal; And
Control circuit, if imported the index signal that described reference signal is made as desirable frequency, then select signal corresponding to the reference frequency of this index signal to described reference oscillator output, to the output index signal of described DDS circuit output corresponding to this index signal, amplify set point to described the 1st amplifier output corresponding to the 1st of this index signal, to the variable frequency set point of described variable filter output corresponding to this index signal, amplify set point to described the 2nd amplifier output corresponding to the 2nd of this index signal, to described phase comparison unit output frequency division ratio
Control circuit has: the frequency form, and store described reference frequency corresponding to the index signal of being imported and select signal and described output index signal; The corresponding form of set point is stored the described the 1st corresponding to described index signal and is amplified set point, described the 2nd amplification set point, described variable frequency set point and described frequency dividing ratio; And control part, export corresponding reference frequency with reference to described frequency form at the input of described index signal and select signal and output index signal, export corresponding the 1st amplification set point, the 2nd and amplify set point, variable frequency set point and frequency dividing ratio with reference to the corresponding form of described set point.
2. PLL circuit according to claim 1 is characterized in that,
For reference signal being made as desirable frequency, control circuit output is made as variable reference frequency with these both sides of output signal in reference frequency in the reference oscillator and the DDS circuit and selects signal and output index signal.
3. PLL circuit according to claim 1 and 2 is characterized in that,
For reference signal being made as desirable frequency, control circuit makes in the DDS circuit at the frequency multiplication frequency of reference frequency and this frequency and generates the overlapping frequency of output signal, and output variable frequency set point, select desirable frequency to utilize variable filter.
4. PLL circuit, have voltage-controlled oscillator and phase comparison unit, this phase comparison unit carries out frequency division to the output of described voltage-controlled oscillator and compares with the phase place of reference signal, will be based on the signal of phase difference as the control voltage of described voltage-controlled oscillator and export, this PLL circuit is characterised in that to have:
Reference oscillator selects signal to be made as reference frequency variable and output according to reference frequency;
The DDS circuit, according to from the output index signal of outside and output signal output, and output needle is to the overlapped signal of the output signal of the frequency multiplication frequency of described reference frequency and this frequency according to the reference frequency of being imported;
The 1st amplifier utilizes from the 1st of outside input and amplifies set point to amplifying from the output signal of described DDS circuit;
A plurality of filters have different separately frequencies and pass through frequency bandwidth characteristics;
The 1st switch is selected described a plurality of filter according to the selection signal of importing from the outside, and will be outputed to this selected filter from the output signal of described the 1st amplifier;
The 2nd switch is selected described selected filter according to the selection signal of importing from the outside, and output is from the output signal of this filter;
The 2nd amplifier utilizes from the 2nd of outside input and amplifies set point to amplifying from the output signal of described the 2nd switch, and outputs in the described phase comparison unit as reference signal; And
Control circuit, if imported the index signal that described reference signal is made as desirable frequency, then select signal corresponding to the reference frequency of this index signal to described reference oscillator output, to the output index signal of described DDS circuit output corresponding to this index signal, amplify set point to described the 1st amplifier output corresponding to the 1st of this index signal, amplify set point to described the 2nd amplifier output corresponding to the 2nd of this index signal, to the selection signal of described the 1st switch and described the 2nd switch output corresponding to this index signal, to described phase comparison unit output frequency division ratio
Control circuit has: the frequency form, and store described reference frequency corresponding to the index signal of being imported and select signal and described output index signal; The corresponding form of set point is stored the described the 1st corresponding to described index signal and is amplified set point, described the 2nd amplification set point, described selection signal and described frequency dividing ratio; And control part, export corresponding reference frequency with reference to described frequency form at the input of described index signal and select signal and output index signal, export corresponding the 1st amplification set point, the 2nd and amplify set point, select signal and frequency dividing ratio with reference to the corresponding form of described set point.
5. PLL circuit according to claim 4 is characterized in that,
For reference signal being made as desirable frequency, control circuit output is made as variable reference frequency with these both sides of output signal in reference frequency in the reference oscillator and the DDS circuit and selects signal and output index signal.
6. according to claim 4 or 5 described PLL circuit, it is characterized in that,
For reference signal being made as desirable frequency, control circuit makes the overlapping frequency that generates output signal in the DDS circuit at the frequency multiplication frequency of reference frequency and this frequency, and output selection signal, select desirable frequency to utilize the 1st switch and the 2nd switch.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010-034758 | 2010-02-19 | ||
| JP2010034758A JP4933635B2 (en) | 2010-02-19 | 2010-02-19 | PLL circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102163971A CN102163971A (en) | 2011-08-24 |
| CN102163971B true CN102163971B (en) | 2013-07-31 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2011100399130A Active CN102163971B (en) | 2010-02-19 | 2011-02-17 | Pll circuit |
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| Country | Link |
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| US (1) | US8125255B2 (en) |
| JP (1) | JP4933635B2 (en) |
| CN (1) | CN102163971B (en) |
| TW (1) | TWI455486B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4933635B2 (en) * | 2010-02-19 | 2012-05-16 | 日本電波工業株式会社 | PLL circuit |
| CN103389161A (en) * | 2013-07-30 | 2013-11-13 | 东莞理工学院 | Method and phase locking amplifier device for detecting terahertz weak signal |
| US11726790B2 (en) * | 2019-12-12 | 2023-08-15 | Intel Corporation | Processor and instruction set for flexible qubit control with low memory overhead |
| US11621645B2 (en) * | 2020-06-04 | 2023-04-04 | Stmicroelectronics International N.V. | Methods and device to drive a transistor for synchronous rectification |
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- 2011-02-22 US US12/929,857 patent/US8125255B2/en active Active
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| EP1693967A1 (en) * | 2003-12-10 | 2006-08-23 | Matsushita Electric Industrial Co., Ltd. | Delta-sigma type fraction division pll synthesizer |
| CN1815892A (en) * | 2005-01-31 | 2006-08-09 | 瑞昱半导体股份有限公司 | Circuit for detecting phase-error and generating control signal |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2011172071A (en) | 2011-09-01 |
| US20110204935A1 (en) | 2011-08-25 |
| TWI455486B (en) | 2014-10-01 |
| JP4933635B2 (en) | 2012-05-16 |
| TW201220700A (en) | 2012-05-16 |
| CN102163971A (en) | 2011-08-24 |
| US8125255B2 (en) | 2012-02-28 |
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