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CN102163580A - 一种薄型封装体及其制作方法 - Google Patents

一种薄型封装体及其制作方法 Download PDF

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CN102163580A
CN102163580A CN201110062725XA CN201110062725A CN102163580A CN 102163580 A CN102163580 A CN 102163580A CN 201110062725X A CN201110062725X A CN 201110062725XA CN 201110062725 A CN201110062725 A CN 201110062725A CN 102163580 A CN102163580 A CN 102163580A
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sheet metal
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CN102163580B (zh
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莱纳凯斯特纳
柳丹娜
弗兰克德博斯舒茨
李彬
金新城
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Shanghai Kaihong Electronic Co Ltd
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Abstract

一种薄型封装体，包括：引线框，所述引线框包括芯片贴装部和引脚；芯片，所述芯片设置在引线框的芯片贴装部上；金属片，所述金属片电学连接芯片与引线框对应引脚；塑封体，所述塑封体至少包裹所述芯片、金属片以及金属片分别与芯片和引脚的连接处；所述金属片以及引线框与金属片连接的引脚上均设置有至少一个横向的弯折，以缓冲芯片工作时产生的热应力，塑封体进一步包裹引脚上的弯折部分。本发明的优点在于，通过在金属片和与之连接的引脚上设置横向的弯折结构，缓冲芯片工作时对封装体产生的热应力，并且横线弯折结构还能够避免金属片以及引脚与塑封体之间产生相对滑动，提高了封装体的可靠性。

Description

一种薄型封装体及其制作方法
技术领域
本发明涉及半导体器件封装测试领域，尤其涉及一种薄型封装体及其制作方法。
背景技术
随着半导体产业的快速增长，需要设计更为轻薄型的封装体以满足器件的散热和机械性能的需求。功率器件的封装尤其要求封装结构的轻薄以更好地散热。
功率器件芯片的工作区结温很高，因此需要特别的封装结构以及合适的材料来将工作时产生的热量散发到环境中去。另外，器件发热还会在封装体内部产生热应力，这会导致封装体和芯片的碎裂。
在其他的器件中，由于集成电路的集成度和工作频率越来越高，发热量随之增大，热效应也越来越成为一个不可忽视的问题。故如何设计合适的封装结构以保证封装体和芯片的可靠性和寿命，已经成为现有技术中亟待解决的一个问题。
发明内容
本发明所要解决的技术问题是，提供一种薄型封装体及其制作方法，能够提高封装体和芯片的封装可靠性和使用寿命。
为了解决上述问题，本发明提供了一种薄型封装体，包括：引线框，所述引线框包括芯片贴装部和引脚；芯片，所述芯片设置在引线框的芯片贴装部上；金属片，所述金属片电学连接芯片与引线框对应引脚；塑封体，所述塑封体至少包裹所述芯片、金属片以及金属片分别与芯片和引脚的连接处；所述金属片以及引线框与金属片连接的引脚上均设置有至少一个横向的弯折，以缓冲芯片工作时产生的热应力，塑封体进一步包裹引脚上的弯折部分。
作为可选的技术方案，所述芯片贴装部与芯片相对的另一表面具有沟槽。
作为可选的技术方案，所述沟槽是V型槽。
作为可选的技术方案，所述金属片与芯片结合端具有一凸起的平面，所述凸起平面与芯片之间通过焊料连接。
作为可选的技术方案，所述引线框被塑封体包裹的部分设置有数个贯穿孔，塑封体进一步包裹所述贯穿孔。
作为可选的技术方案，芯片贴装部的与芯片相对的另一表面暴露于塑封体之外。
本发明进一步提供了上述封装体的制作方法，包括如下步骤：提供一引线框，所述引线框包括芯片贴装部和引脚，所述引线框与金属片连接的引脚上设置有至少一个横向的弯折；将一芯片安置在引线框的芯片贴装部上；采用至少一金属片将芯片暴露出的表面电学连接至引线框架对应的引脚，所述金属片上设置有至少一个横向的弯折；对安置有所述芯片和金属片的引线框实施注塑，所形成的塑封体至少覆盖所述芯片、金属片、金属片分别与芯片和引脚的连接处以及引脚上的弯折部分。
本发明的优点在于，通过在金属片和与之连接的引脚上设置横向的弯折结构，此横向弯折能够缓冲金属片和引脚沿着纵向的延展程度，增强其弹性，故能够缓冲芯片工作时对封装体产生的热应力，从而提高封装体的可靠性和使用寿命，并且横线弯折结构还能够避免金属片以及引脚与塑封体之间产生相对滑动，进一步提高封装体的可靠性。
附图说明
附图1所示是本具体实施方式所述方法的实施步骤流程图。
附图2A～2D所示是本具体实施方式所述方法的工艺示意图。
具体实施方式
下面结合附图对本发明提供的一种薄型封装体及其制作方法的具体实施方式做详细说明。
附图1所示是本具体实施方式所述方法的实施步骤流程图，包括如下步骤：步骤S10，提供一引线框；步骤S11，将一芯片安置在引线框的芯片贴装部上；步骤S12，采用至少一金属片将芯片暴露出的表面电学连接至引线框架对应的引脚；步骤S13，对安置有所述芯片和金属片的引线框实施注塑。
附图2A所示，参考步骤S10，提供一引线框100，所述引线框100包括芯片贴装部101和引脚102与103。引线框100的引脚102上设置有至少一个横向的弯折105，以缓冲芯片工作时产生的热应力。所述引线框100设置有数个贯穿孔，本实施方式以107与108表示。
附图2B所示，参考步骤S11，将一芯片130安置在引线框100的芯片贴装部101上。此步骤可以采用倒装工艺，即在芯片130表面需要引出电极的部分生长金属凸起(图中未示出)，并将金属凸起对准芯片贴装部101表面与引脚电学连接的部分进行贴装。贴装完毕后，芯片130表面的电极即通过金属凸起和芯片贴装部101电学连接至引线框100的引脚103或者其他更多的引脚上。
附图2C所示，参考步骤S12，采用至少一金属片150将芯片130暴露出的表面电学连接至引线框100对应的引脚102上。金属片150的引脚上设置有至少一个横向的弯折，以缓冲芯片130工作时产生的热应力。本实施方式中，芯片的背面设置有背电极，故需要通过金属片150将背电极电学连接至对应的引脚上。本实施方式中，为了进一步确保工艺的可靠性，在金属片150与芯片130的结合端设置了一凸向芯片130的凸起151。
本实施方式中，金属片150以及引线框100的引脚102上的引脚上均设置有至少一个横向的弯折，以缓冲芯片130工作时产生的热应力。所谓横向弯折，是相对于引脚102和芯片130的连接方向而言的。以引脚102和芯片130相互的连接方向为纵向，与此呈一角度(本实施方式为垂直，但不限于此)的方向即称之为横向。所述弯折可以是一个，也可以是连续排列的多个。芯片130在工作中会产生大量的热量，这些热量一部分进入引线框芯片贴装部101散发到环境中去，此机理将在后文详细叙述。另一部分热量将通过金属片150传递到引脚102再散发到环境中。故在芯片工作的过程中，金属片150和引脚102的温度会显著升高。由于金属片150和引脚102在后续的工艺中会被塑封，而塑封材料的热膨胀系数和金属片150以及引脚102不同，故会产生显著的热应力。此横向弯折能够缓冲金属片150和引脚102沿着纵向的延展程度，增强其弹性，故能够缓冲芯片130工作时对封装体产生的热应力，从而提高封装体的可靠性和使用寿命。
金属片150与芯片130之间的电学连接具体地说是通过将凸起151的突出平面与芯片130之间通过焊料连接来实现的。具体地说，首先将焊料涂敷于芯片130的表面，再将金属片150的凸起151的突出平面压在焊料上。现有技术中的金属片150是搭接在芯片130背面的，采用端部一很窄的平面与芯片130接触，焊料很容易沿金属片150与芯片130的接触部分向两侧流淌到芯片130的侧面，导致封装失效。而上述步骤实施完毕后，焊料被均匀地夹在凸起151与芯片130之间，只要在封装过程中对压力控制得当，能够有效地避免焊料流淌到芯片130的侧面。
附图2D所示，参考步骤S13，对安置有芯片130和金属片150的引线框100实施注塑，所形成的塑封体170至少覆盖芯片130、金属片150、金属片150分别与芯片130和引脚102的连接处以及引脚102上的弯折部分，并将芯片贴装部101与芯片130相对的表面暴露于塑封体170之外。所述芯片贴装部101的与芯片130相对的表面具有V型的沟槽(图中未示出)，在此表面暴露于塑封体170之外的情况下，沟槽能够增大另一侧的表面积，从而更好地将芯片产生的热量散发到环境中去。
附图2D所示即为上述步骤实施完毕后所获得的封装体的剖面示意图。所形成的塑封体170至少覆盖芯片130、金属片150、金属片150分别与芯片130和引脚102的连接处以及引脚102上的弯折部分意在对封装完毕的结构进行保护。本步骤中，塑封体170进一步包裹了引线框上的贯穿孔108和109，防止引线框100在热膨胀的情况下由于同塑封体170的热膨胀系数不同，而与塑封体170之间发生相对滑动导致引线框100与塑封体170相互分离，导致封装结构被破坏，提高了封装体的使用寿命。并且横线弯折结构还能够避免金属片150以及引脚102在外界的拉力作用下与塑封体170之间产生相对滑动，从而进一步提高封装体的可靠性。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (7)

1.一种薄型封装体，包括：
引线框，所述引线框包括芯片贴装部和引脚；
芯片，所述芯片设置在引线框的芯片贴装部上；
金属片，所述金属片电学连接芯片与引线框对应引脚；
塑封体，所述塑封体至少包裹所述芯片、金属片以及金属片分别与芯片和引脚的连接处；其特征在于：
所述金属片以及引线框与金属片连接的引脚上均设置有至少一个横向的弯折，以缓冲芯片工作时产生的热应力，塑封体进一步包裹引脚上的弯折部分。
2.根据权利要求1所述的薄型封装体，其特征在于，所述芯片贴装部与芯片相对的一表面具有沟槽。
3.根据权利要求2所述的薄型封装体，其特征在于，所述沟槽是V型槽。
4.根据权利要求1所述的薄型封装体，其特征在于，所述金属片与芯片结合端具有一凸起的平面，所述凸起平面与芯片之间通过焊料连接。
5.根据权利要求1所述的薄型封装体，其特征在于，所述引线框被塑封体包裹的部分设置有数个贯穿孔，塑封体进一步包裹所述贯穿孔。
6.根据权利要求1所述的薄型封装体，其特征在于，芯片贴装部的与芯片相对的另一表面暴露于塑封体之外。
7.一种权利要求1所述封装体的制作方法，其特征在于，包括如下步骤：
提供一引线框，所述引线框包括芯片贴装部和引脚，所述引线框欲与金属片连接的引脚上设置有至少一个横向的弯折；
将一芯片安置在引线框的芯片贴装部上；
采用至少一金属片将芯片暴露出的表面电学连接至引线框架对应的引脚，
所述金属片上设置有至少一个横向的弯折；
对安置有所述芯片和金属片的引线框实施注塑，所形成的塑封体至少覆盖所述芯片、金属片、金属片分别与芯片和引脚的连接处、以及引脚上的弯折部分。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104882566A (zh) * 2015-05-21 2015-09-02 京东方科技集团股份有限公司 一种发光二极管封装结构和封装方法
CN105047569A (zh) * 2015-06-30 2015-11-11 南通富士通微电子股份有限公司 一种半导体封装方法
CN108039342A (zh) * 2017-12-01 2018-05-15 泰州友润电子科技股份有限公司 一种改进的to-220d7l引线框架
CN109103146A (zh) * 2017-06-21 2018-12-28 三菱电机株式会社 半导体装置
CN109755205A (zh) * 2017-11-08 2019-05-14 株式会社东芝 半导体装置
CN113130422A (zh) * 2021-02-26 2021-07-16 广东美的白色家电技术创新中心有限公司 功率模块及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1149766A (zh) * 1995-10-30 1997-05-14 三菱电机株式会社 树脂密封型半导体器件
CN1941336A (zh) * 2005-09-29 2007-04-04 南茂科技股份有限公司 增进晶背散热的薄型封装构造
US20070090463A1 (en) * 2005-10-20 2007-04-26 Tan Xiaochun Semiconductor devices with multiple heat sinks
US20080164590A1 (en) * 2007-01-10 2008-07-10 Diodes, Inc. Semiconductor power device
CN101803015A (zh) * 2007-07-17 2010-08-11 赛特克斯半导体公司 具有弯曲外引线的半导体芯片封装

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1149766A (zh) * 1995-10-30 1997-05-14 三菱电机株式会社 树脂密封型半导体器件
CN1941336A (zh) * 2005-09-29 2007-04-04 南茂科技股份有限公司 增进晶背散热的薄型封装构造
US20070090463A1 (en) * 2005-10-20 2007-04-26 Tan Xiaochun Semiconductor devices with multiple heat sinks
US20080164590A1 (en) * 2007-01-10 2008-07-10 Diodes, Inc. Semiconductor power device
CN101803015A (zh) * 2007-07-17 2010-08-11 赛特克斯半导体公司 具有弯曲外引线的半导体芯片封装

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104882566A (zh) * 2015-05-21 2015-09-02 京东方科技集团股份有限公司 一种发光二极管封装结构和封装方法
US10038047B2 (en) 2015-05-21 2018-07-31 Boe Technology Group Co., Ltd. Light emitting diode packaging structure and packaging method
CN105047569A (zh) * 2015-06-30 2015-11-11 南通富士通微电子股份有限公司 一种半导体封装方法
CN105047569B (zh) * 2015-06-30 2018-02-27 通富微电子股份有限公司 一种半导体封装方法
CN109103146A (zh) * 2017-06-21 2018-12-28 三菱电机株式会社 半导体装置
CN109103146B (zh) * 2017-06-21 2021-09-21 三菱电机株式会社 半导体装置
CN109755205B (zh) * 2017-11-08 2023-07-04 株式会社东芝 半导体装置
CN109755205A (zh) * 2017-11-08 2019-05-14 株式会社东芝 半导体装置
EP3483931A1 (en) * 2017-11-08 2019-05-15 Kabushiki Kaisha Toshiba Semiconductor device
US11037863B2 (en) 2017-11-08 2021-06-15 Kabushiki Kaisha Toshiba Semiconductor device
US11735505B2 (en) 2017-11-08 2023-08-22 Kabushiki Kaisha Toshiba Semiconductor device
CN108039342A (zh) * 2017-12-01 2018-05-15 泰州友润电子科技股份有限公司 一种改进的to-220d7l引线框架
CN113130422B (zh) * 2021-02-26 2023-04-18 广东美的白色家电技术创新中心有限公司 功率模块及其制备方法
CN113130422A (zh) * 2021-02-26 2021-07-16 广东美的白色家电技术创新中心有限公司 功率模块及其制备方法

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