CN102169840A - Encapsulation method of system level fan-out wafer - Google Patents
Encapsulation method of system level fan-out wafer Download PDFInfo
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- CN102169840A CN102169840A CN2011100322707A CN201110032270A CN102169840A CN 102169840 A CN102169840 A CN 102169840A CN 2011100322707 A CN2011100322707 A CN 2011100322707A CN 201110032270 A CN201110032270 A CN 201110032270A CN 102169840 A CN102169840 A CN 102169840A
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- 238000005538 encapsulation Methods 0.000 title abstract description 21
- 239000002184 metal Substances 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 31
- 238000012856 packing Methods 0.000 claims description 18
- 239000003292 glue Substances 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 238000007639 printing Methods 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 claims description 4
- 238000007906 compression Methods 0.000 claims description 3
- 230000006835 compression Effects 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 239000003566 sealing material Substances 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 description 17
- 238000005516 engineering process Methods 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention relates to an encapsulation method of a system level fan-out wafer. The method comprises the following steps of: forming a cementing layer on a carrier board; adhering a functional surface of a chip and a passive device on the cementing layer; forming a sealing material layer on the surface adhered with the chip and the passive device to perform the encapsulation curing; and removing the carrier board and the cementing layer. Compared with the prior art, the chip and the passive device are encapsulated together after integrating by using the encapsulation method of system level fan-out wafer, so that a final encapsulation product containing the integral system function but not single chip function is formed; compared with the prior system level encapsulation, the wafer level encapsulation with high integrality reduces the interference factors such as resistance and inductance in the system, and more conforms to the slim type trend of the encapsulation of the semiconductor.
Description
Technical field
The present invention relates to semiconductor technology, relate in particular to a kind of system-level fan-out wafer method for packing.
Background technology
Wafer-level packaging (Wafer Level Packaging, WLP) technology is that the full wafer wafer is carried out cutting the technology that obtains single finished chip again after the packaging and testing, chip size and nude film after the encapsulation are in full accord.The crystal wafer chip dimension encapsulation technology has thoroughly been overturned conventional package such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier) and organic leadless chip carrier (Organic LeadlessChip Carrier) isotype, has complied with that market is light day by day, little, short to microelectronic product, thinning and low priceization requirement.It is highly microminiaturized that chip size after crystal wafer chip dimension encapsulation technology encapsulation has reached, chip cost along with chip size reduce significantly reduce with the increase of wafer size.The crystal wafer chip dimension encapsulation technology be IC can be designed, technology that wafer manufacturing, packaging and testing, substrate manufacturing integrate, be the focus and the developing tendency in future of current encapsulation field.
The encapsulation of fan-out wafer is a kind of of wafer-level packaging.For example, the Chinese invention patent application discloses a kind of wafer scale fan-out chip packaging method No. 200910031885.0, comprise following processing step: cover stripping film and thin film dielectrics layer I successively in the carrier disk surfaces, on thin film dielectrics layer I, form litho pattern opening I; Realize the metal electrode be connected with edge of substrate and wiring metal cabling again on figure opening I and surface thereof; At the surface of metal electrode that is connected with edge of substrate, the surface coverage thin film dielectrics layer II of wiring metal cabling surface and thin film dielectrics layer I again, and on thin film dielectrics layer II, form litho pattern opening II; Realize the metal electrode be connected with die terminals at litho pattern opening II; With flip-chip to metal electrode that die terminals is connected after carry out the injection moulding envelope bed of material and solidify, formation has the packaging body of the plastic packaging bed of material; The carrier disk is separated with the packaging body that has the plastic packaging bed of material with stripping film, form the plastic packaging disk; Plant ball and reflux, form solder bumps; The monolithic cutting forms final fan-out chip structure.
The final products of packaged manufacturing only have single chip functions according to the method described above.Realize complete systemic-function as need, need outside final products, add the peripheral circuit that includes various electric capacity, inductance or resistance etc.
Summary of the invention
The technical problem that the present invention solves is: how to realize system-level fan-out wafer encapsulation.
For solving the problems of the technologies described above, the invention provides system-level fan-out wafer method for packing, comprise step: on support plate, form cementing layer; The function face of chip and passive device is affixed on the described cementing layer; The one side of support plate being posted chip and passive device forms the envelope bed of material, carries out package curing; Remove described support plate and cementing layer.
Alternatively, the described envelope bed of material also be filled between described chip and the chip, between chip and the passive device and/or the space between passive device and the passive device.
Alternatively, described passive device comprises electric capacity, resistance and inductance.
Alternatively, the material of the described envelope bed of material is an epoxy resin.
Alternatively, the described envelope bed of material is formed on described chip and the passive device by metaideophone, compression or method of printing.
Alternatively, described cementing layer is a UV glue.
The step of described support plate of described removal and cementing layer specifically comprises:
Remove described cementing layer;
The function face of support plate with chip and passive device separated;
Clean the function face of described chip and passive device.
Alternatively, described chip comprises a plurality of different chips.
Alternatively, described support plate is a glass support plate.
Alternatively, also comprise step: form metal wiring layer again at chip and the exposed function face of passive device; Form protective film on the wiring layer again at metal; On protective film, form the exposing metal opening of wiring layer again; In described opening, form and the described metal ball lower metal layer that is connected of wiring layer again; On the ball lower metal layer, form the metallic tin ball.
Compared with prior art; the system-level fan-out wafer method for packing that the present invention asks for protection; encapsulation in the lump again after chip and passive device integrated; can form and comprise the total system function but not the final encapsulating products of single chip functions; compare the encapsulation of existing systems level; the wafer level packaging of high integration has reduced disturbing factor such as resistance, inductance in the system especially, also more can comply with the compact trend requirement of semiconductor packages.
Description of drawings
Fig. 1 is a system-level fan-out wafer method for packing flow chart in the one embodiment of the invention;
Fig. 2 is a system-level fan-out wafer method for packing flow chart in the another embodiment of the present invention;
Fig. 3 to Figure 10 is an encapsulating structure schematic diagram in the flow process shown in Figure 2.
Embodiment
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when the embodiment of the invention was described in detail in detail, for ease of explanation, described schematic diagram was an example, and it should not limit the scope of protection of the invention at this.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
As shown in Figure 1, in one embodiment of the invention, provide system-level fan-out wafer method for packing, comprise step:
S101 forms cementing layer on support plate;
S102 is affixed on the function face of chip and passive device on the cementing layer;
S103, the one side of support plate being posted chip and passive device forms the envelope bed of material, carries out package curing;
S104 removes support plate and cementing layer.
As shown in Figure 2, in another embodiment of the present invention, provide system-level fan-out wafer method for packing, comprise step:
S201 forms cementing layer on support plate;
S202 is affixed on the function face of chip and passive device on the cementing layer;
S203, the one side of support plate being posted chip and passive device forms the envelope bed of material, carries out package curing;
S204 removes cementing layer;
S205 separates the function face of support plate with chip and passive device;
S206, the function face of cleaning chip and passive device;
S207 carries out metal at the exposed function face of chip and passive device and connects up;
S208 forms diaphragm on connect up again place surface of metal, and form the opening that exposes metal covering on diaphragm;
S209 forms the ball lower metal layer on the metal covering in the diaphragm opening;
S210 forms the metallic tin ball on ball lower metal layer surface.
In the present embodiment, at first execution in step S201 forms cementing layer 102 on support plate 101, forms structure as shown in Figure 3.
In this step, support plate 101 is the bases that are used for carrying follow-up chip 103 and passive device 104.
In the present embodiment, support plate 101 adopts glass material, and better hardness and evenness can be provided, and reduces the inefficacy ratio of packaging.In addition, owing to support plate 101 can be stripped from subsequent step, and the support plate 101 of glass material is easily peeled off, resistance to corrosion is strong, can therefore can not reuse because of the change that physics and chemical property take place with contacting of cementing layer 102.Certainly, those skilled in the art understand, and support plate 101 for example adopts silicon compound also can realize purpose of the present invention.
The cementing layer 102 that forms on support plate 101 is to be used for chip 103 and passive device 104 are fixed on support plate 101.Cementing layer 102 available materials have multiple, and in preferred embodiment of the present invention, cementing layer 102 adopts UV glue.UV glue be a kind of can be to the aitiogenic glueing material of the UV-irradiation of special wavelength.UV glue according to UV-irradiation after the variation of viscosity can be divided into two kinds, a kind of is that UV solidifies glue, be to produce living radical or cation light trigger in the material or sensitising agent absorb ultraviolet light under ultraviolet irradiation after, trigger monomer polymerization, crosslinked and connect Zhi Huaxue reaction, it is solid-state that ultraviolet cured adhesive was converted into by liquid state in the several seconds, thereby the body surface that is in contact with it is bonding; Another kind is that UV glue is that viscosity is very not high when passing through ultraviolet irradiation, is caused viscosity to decline to a great extent or disappears and interrupt through the crosslinking chemical bond in the material after the UV-irradiation.The UV glue that the cementing layer 102 is here adopted promptly is the latter.
The method that forms cementing layer 102 on support plate 101 can for example be by methods such as spin coating or printings cementing layer 102 to be coated on the support plate 101.Such method is well known to those skilled in the art in field of semiconductor manufacture, does not repeat them here.
After forming cementing layer 102 on the support plate 101, can execution in step S202, the function face of chip 103 and passive device 104 is affixed on the cementing layer 102, form structure as shown in Figure 4.
In the specific embodiment of the present invention, the function face of chip 103 and passive device 104 is meant the surface, pad place of the metal electrode and the passive device 104 of chip 103.
In a preferred embodiment of the present invention, the a plurality of chips 103 that fit on the cementing layer 102 can be a plurality of different chips, these chips become the part of a system in package product separately, finish the one or more independent function that realizes in the system level function separately.
In a preferred embodiment of the present invention, chip 103 designs according to systemic-function with the combination of passive device 104.Therefore, around a chip 103, has identical or different other chip 103, passive devices 104 such as perhaps identical or different electric capacity, resistance or inductance; Similarly, around a passive device 104, has the passive device 104 of identical or different other, perhaps one or more identical or different chips 103.
Execution in step S203 carries out encapsulation of the plastic packaging bed of material and curing with the support plate face that posts chip and passive device then, forms to have the packaging body that seals the bed of material 105, promptly forms structure as shown in Figure 5.In the subsequent technique process, packaging body can be protected function face other surfaces in addition of chip 103 and passive device 104, can be used as the supporting body of subsequent technique again.
In one embodiment of the invention, forming the material that seals the bed of material 105 is epoxy resin.The good seal performance of this material, plastotype is easy, is the preferred materials that forms the envelope bed of material 105.The method that forms the envelope bed of material 105 can for example be metaideophone, compression or method of printing.The concrete steps of these methods are well known to those skilled in the art, do not repeat them here.
As previously mentioned, around a chip 103, have other chip 103, perhaps passive device 104; Around a passive device 104, also has the passive device 104 of identical or different other, perhaps one or more identical or different chips 103.Therefore, around chip 103 or passive device 104, have the space.For chip 103 and passive device 104 formed better protection, the envelope bed of material 105 also is filled between chip 103 and the chip 103, between chip 103 and the passive device 104 and/or space between passive device 104 and the passive device 104.
Because the thickness of chip 103 and passive device 104 also is not quite similar, possible chip 103 is thicker, and also possible passive device 104 is thicker.Therefore, the thickness of the envelope bed of material 105 should be greater than one the thickest thickness in each chip 103 and the passive device 104, in order to provide best protection to chip 103 and passive device 104.
S204 removes cementing layer 102.Because cementing layer 102 is organic materials, can be dissolved in specific organic solvent.Therefore, the method that can adopt organic solvent to clean makes cementing layer 102 be dissolved in the organic solvent.
Execution in step S205 separates the function face of support plate 101 with chip 103 and passive device 104 then.That is to say, after execution in step S204, cementing layer 102 solvent has fallen, and perhaps is under the strippable molten condition, can easily the function face of support plate 101 from chip 103 and passive device 104 be stripped down, thereby expose the function face of chip 103 and passive device 104.
Execution in step S206 again, clean the function face of chip 103 and passive device 104, with cementing layer residual on the function face 102, form structure as shown in Figure 6, chip 103 and passive device 104 no longer are fixed together through support plate but have been fixed together by packaging body at this moment, and the metal electrode of chip and the pad of passive device also expose out simultaneously.
Extremely shown in Figure 10 as Fig. 7, follow again execution in step S207 to step S210, comprise: carry out metal at the exposed function face of chip and passive device and connect up 106 again, the metal wire that makes the pad of the metal electrode of chip and passive device see through again cloth is realized the interconnected and cabling of functional system; Form diaphragm 107 on connect up again place surface of metal, and the opening that forms design on diaphragm connects up 106 again to expose metal; Metal in the diaphragm opening connects up and forms ball lower metal layer 108 on 106; Form metallic tin ball 109 on ball lower metal layer 108 surfaces.Step S207 is identical with the method for existing fan-out wafer encapsulation to step S210, does not repeat them here.
Through above-mentioned steps, finish system in package substantially.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. system-level fan-out wafer method for packing is characterized in that, comprises step:
On support plate, form cementing layer;
The function face of chip and passive device is affixed on the described cementing layer;
The one side of support plate being posted chip and passive device forms the envelope bed of material, carries out package curing;
Remove described support plate and cementing layer.
2. the system as claimed in claim 1 level fan-out wafer method for packing is characterized in that: the described envelope bed of material also is filled between described chip and the chip, between chip and the passive device and/or the space between passive device and the passive device.
3. the system as claimed in claim 1 level fan-out wafer method for packing, it is characterized in that: described passive device comprises electric capacity, resistance and inductance.
4. the system as claimed in claim 1 level fan-out wafer method for packing, it is characterized in that: the material of the described envelope bed of material is an epoxy resin.
5. the system as claimed in claim 1 level fan-out wafer method for packing, it is characterized in that: the described envelope bed of material is formed on described chip and the passive device by metaideophone, compression or method of printing.
6. the system as claimed in claim 1 level fan-out wafer method for packing, it is characterized in that: described cementing layer is a UV glue.
7. the system as claimed in claim 1 level fan-out wafer method for packing is characterized in that, the step of described support plate of described removal and cementing layer specifically comprises:
Remove described cementing layer;
The function face of support plate with chip and passive device separated;
Clean the function face of described chip and passive device.
8. the system as claimed in claim 1 level fan-out wafer method for packing, it is characterized in that: described chip comprises a plurality of different chips.
9. the system as claimed in claim 1 level fan-out wafer method for packing, it is characterized in that: described support plate is a glass support plate.
10. the system as claimed in claim 1 level fan-out wafer method for packing is characterized in that, also comprises step:
Form metal wiring layer again at chip and the exposed function face of passive device;
Form protective film on the wiring layer again at metal;
On protective film, form the exposing metal opening of wiring layer again;
In described opening, form and the described metal ball lower metal layer that is connected of wiring layer again;
On the ball lower metal layer, form the metallic tin ball.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100322707A CN102169840A (en) | 2011-01-30 | 2011-01-30 | Encapsulation method of system level fan-out wafer |
| US13/981,116 US9324583B2 (en) | 2011-01-30 | 2012-01-20 | Packaging method |
| PCT/CN2012/070628 WO2012100720A1 (en) | 2011-01-30 | 2012-01-20 | Packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100322707A CN102169840A (en) | 2011-01-30 | 2011-01-30 | Encapsulation method of system level fan-out wafer |
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| CN102169840A true CN102169840A (en) | 2011-08-31 |
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| CN2011100322707A Pending CN102169840A (en) | 2011-01-30 | 2011-01-30 | Encapsulation method of system level fan-out wafer |
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| CN103258770A (en) * | 2012-02-17 | 2013-08-21 | 富士通株式会社 | Method of manufacturing semiconductor device and method of manufacturing electronic device |
| CN104465418A (en) * | 2014-12-24 | 2015-03-25 | 南通富士通微电子股份有限公司 | Fan-out wafer-level encapsulating method |
| US9497862B2 (en) | 2011-01-30 | 2016-11-15 | Nantong Fujitsu Microelectronics Co., Ltd. | Packaging structure |
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| CN104465418A (en) * | 2014-12-24 | 2015-03-25 | 南通富士通微电子股份有限公司 | Fan-out wafer-level encapsulating method |
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Application publication date: 20110831 |