CN102157562B - Method for manufacturing bottom gate metal oxide thin film transistor - Google Patents
Method for manufacturing bottom gate metal oxide thin film transistor Download PDFInfo
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Abstract
The invention relates to a method for manufacturing a bottom gate metal oxide thin film transistor in the technical field of semiconductor manufacturing. The method comprises the following steps: sequentially manufacturing a gate electrode and a metal oxide material; then coating an optical resist on the surface of the metal oxide material and the optical resist, and carrying out planarization treatment on the optical resist by adopting chemical machinery polishing; carrying out annealing treatment or plasma treatment on the metal oxide which is not masked by the optical resist; and finally stripping the optical resist, then carrying out magnetron sputtering and deposition on the source electrode and the drain electrode materials, and forming the source electrode and the drain electrode through photoetching and wet process etching. According to the invention, the characteristic that the metal oxide material can be converted from an insulator into a semiconductor after special treatment is utilized, the metal oxide thin film transistor with an active layer of a special structure is manufactured, and the occurrence of the crack phenomenon of the source electrode and the drain electrode can be prevented effectively.
Description
Technical field
That the present invention relates to is a kind of transistor preparation method of technical field of semiconductors, specifically is a kind of preparation method of bottom gate metal oxide thin-film transistor.
Background technology
At present, active layer adopts amorphous silicon (a-Si) and polysilicon semi-conducting materials such as (p-Si) more in thin-film transistor (TFT) technology.Wherein, a-Si TFT is most widely used general, can cover flat panel display (FPD) product of nearly all size.P-Si TFT is subjected to the restriction of membranous homogeneity, can only be applicable to the small-medium size product at present.From device property, a-Si TFT has advantages such as simple structure, volume production homogeneity be relatively good, but has low (the about 0.5cm of mobility simultaneously
2/ Vs), shortcoming such as light durability difference; Although having than a-Si TFT, p-Si TFT exceeds a lot of mobility (＞10cm
2/ Vs), but have shortcoming such as the big and volume production homogeneity difference of complex structure, leakage current simultaneously.Along with the fast development of FPD technology, more and more higher requirement has been proposed for the performance of TFT.Can't satisfy above-mentioned requirements fully from the characteristic of a-Si TFT and p-Si TFT, so more advanced TFT technology remains to be developed.At present, metal oxide TFT is one of most promising replacer.
Metal oxide has following two aspect advantages as the active layer material of TFT: (1) forbidden band wide (＞3.0eV), bring extraordinary light durability thus, so it is different with a-Si TFT, metal oxide TFT can be made into full impregnated funerary objects spare, thereby significantly increase the aperture opening ratio of panel, and then reduce the power consumption of display; (2) high mobility (about 10cm
2/ Vs).In general, metal oxide TFT has the technical advantage of a-Si TFT and p-Si TFT concurrently, and has feasibility in scale of mass production, so very likely replace the main flow that a-Si TFT becomes flat panel display active electronic driving element in the near future.
The metal current oxide thin film transistor still is in the research and development stage before the volume production.From the document of publishing, research institute adopts the device architecture of metal oxide TFT and manufacturing process to adopt the technology similar with a-Si TFT more.Modal is exactly wrong row's type (Inverted-Staggered) structure of bottom gate and the related manufacturing process flow process that extensively adopts in a-Si TFT actual production.Fig. 1 is the generalized section of the common structure of metal oxide thin-film transistor, comprise glass substrate 110, be arranged at the gate electrode layer 120 on the substrate, be arranged at the gate insulation layer 130 of substrate and gate electrode layer, be arranged at metal oxide semiconductor layer 140, drain electrode layer 151 and source electrode layer 152 on the gate insulation layer.Device protecting layer, pixel electrode layer etc. are because of haveing nothing to do with the present invention and omitting at this.Fig. 2 comprises forming gate electrode pattern T10 for making the technological process that device architecture shown in Figure 1 adopts usually, forms gate insulation layer T20, forms metal oxide semiconductor layer pattern T30, and forms source-drain electrode layer pattern T40.
Research experience shows, the fracture of source-drain electrode film takes place easily in frame of broken lines A and B position when adopting device architecture shown in Figure 1, and this is because exist step to cause the source-drain electrode film at this place can take place due to stress concentrates at the boundary of active layer.When device was used for the flat panel display driving, above-mentioned fracture can cause the generation of point defect.
Summary of the invention
The present invention is directed to the prior art above shortcomings, a kind of preparation method of bottom gate metal oxide thin-film transistor is provided, utilize metal oxide materials after special processing, can be converted into semi-conductive characteristics by insulator, make the metal oxide thin-film transistor that active layer has special construction, can effectively prevent the generation of source-drain electrode film phenomenon of rupture.
The present invention is achieved by the following technical solutions, the present invention includes following steps:
The first step, adopt magnetron sputtering one deck gate electrode film and form gate electrode by photoetching and wet etching at substrate;
Described wet etching refers to: it is 55wt%H that the etching material is immersed in composition
3PO
4, 15%HNO
3And 5wt%CH
3Corrode in the etching liquid of COOH.
Second step, using plasma strengthens chemical vapour deposition (CVD) gate insulation layer material successively on gate electrode, and adopts AC magnetic controlled sputtered metal oxide material;
Described plasma enhanced chemical vapor deposition refers to: the auxiliary reactive material down in the plasma discharge process issues biochemical reaction in the gaseous state condition, generate the substrate surface that solid matter is deposited on heating, and then making solid film, gate insulation layer material wherein refers to: silicon dioxide or silicon nitride.
Described metal oxide materials refers to: zinc oxide, indium oxide gallium zinc, indium zinc oxide or indium oxide gallium, its carrier concentration is 10
10/ cm
3Below.
The 3rd step, adopt chemico-mechanical polishing to carry out planarization at metal oxide materials surface applied photoresist and to photoresist layer;
The thickness of described photoresist layer is the 1.2-2.0 micron; Described employing chemico-mechanical polishing refers to: adopt 100-150gm/cm
2Pressure, photoresist layer is polished smooth with the rotating speed of 60-200rpm.
The 4th step, by annealing in process or plasma treatment not by the metal oxide of photoresist masking, make it to be converted into carrier concentration and increase to 10
13-10
15Cm
-3Above semiconductor;
Described annealing refers to: under vacuum or reducing atmosphere in the process of 200～400 ℃ of heat treated; Described plasma treatment refers to: adopt argon plasma that device is carried out 1～3 minute surface-treated process.
The 5th step, stripping photoresist and magnetron sputtering deposition source-drain electrode material also form source-drain electrode by photoetching and wet etching.
Described peeling off refers to: employing dimethyl sulfoxide (DMSO) and monoethanolamine are that 7: 3 mixing stripper is removed photoresist by weight.
Magnetron sputtering described in the first step, second step and the 5th step refers to: utilize argon plasma under the effect in electric field and magnetic field, the high-energy ion bombardment target material surface that is accelerated, after the energy exchange, the atom of target material surface breaks away from former lattice and overflows, transfer to substrate surface and film forming, sputtering power is 100W, gas pressure is 1Pa, the proportion of oxygen and argon gas is in the sputter gas: 1: 20～1: 100 and argon flow amount are 30sccm, and the material of gate electrode film wherein is: aluminium, molybdenum or chromium metal or its alloy.
The structure of the metal oxide thin-film transistor that the present invention relates to is: a kind of metal oxide thin-film transistor, be formed on the glass substrate, and comprise a gate electrode layer, a gate insulation layer, a metal oxide layer and a source-drain electrode layer.Described gate electrode layer is positioned on the glass substrate, described gate insulation layer is positioned on gate electrode and the glass substrate and the covering grid electrode layer, described metal oxide layer is positioned on the gate insulation layer and complete covering gate insulating barrier, and described source-drain electrode layer is positioned on the metal oxide layer and is overlapping with metal oxide layer near channel region.It is characterized in that: metal oxide layer is divided into two zones, i.e. semiconductor regions and insulator region according to the difference of conductive characteristic.Be positioned near the metal-oxide film of channel region and present characteristic of semiconductor; Other regional metal oxide presents the insulator characteristic.
Utilize the difference of the structure of the metal oxide thin-film transistor that the present invention prepares and common device architecture to be to eliminate the border on active layer island.Compared with prior art, the present invention has taken full advantage of metal oxide materials can divide the characteristics that are semiconductor and insulator under different technology conditions, active layer island in the common structure of metal oxide thin-film transistor is transferred in the insulating layer material that is embedded in equal thickness, so just removed the step that causes because of the existence of active layer island boundaries, thereby the stress that has reduced significantly in the source-drain electrode thin-film material of upper strata is concentrated, and then solved the difficult problem of source-drain electrode film easy fracture, effectively improved the production qualification rate.
Description of drawings
Fig. 1 is the common structural representation of bottom gate metal oxide thin-film transistor.
Fig. 2 is the common process flow diagram of bottom gate metal oxide thin-film transistor.
Fig. 3 is metal oxide thin-film transistor structural representation of the present invention.
Fig. 4 is embodiment 1 process chart.
Fig. 5 is embodiment 2 process charts.
Fig. 6 is embodiment 3 process charts.
Embodiment
Below embodiments of the invention are elaborated, present embodiment is being to implement under the prerequisite with the technical solution of the present invention, provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
Embodiment 1
As shown in Figure 4, the manufacturing process of bottom gate metal oxide thin-film transistor of the present invention comprises the steps:
A) form required pattern (shown in Fig. 4 (a)) at glass substrate deposition one deck gate electrode film and by technologies such as photoetching and etchings.
B) deposition one deck gate insulation layer material (shown in Fig. 4 (b)).
C) deposition layer of metal oxide material makes it be insulator characteristic (shown in Fig. 4 (c)) by the control process conditions.
D) coating photoresist 710 and adopt chemico-mechanical polishing (CMP) technology that photoresist is carried out planarization, make except near other zone channel region all by photoresist covering (shown in 4 (d)).
E) 810 pairs of sulls that expose of method of handling by the employing vacuum annealing are handled and are made it change into characteristic of semiconductor (shown in 4 (e)).
F) remove photoresist (shown in 4 (f)).
G) deposition one deck source-drain electrode film and form required pattern by technologies such as photoetching and etchings is finally finished preparation of devices (as shown in Figure 3).
Described processing step a), film-forming process adopts magnetron sputtering technique usually, target adopts AlNd and MoNb alloy; Etching technics adopts traditional wet etching technique, and etching liquid adopts the mixed solution of phosphoric acid, sulfuric acid and acetic acid.
Described processing step b), using plasma strengthens chemical vapour deposition technique usually.Be example with the deposition of silica, adopting silane and oxygen is reacting gas, and discharge power is 200W, and the substrate heating-up temperature is 300 ℃.
Described processing step c), adopt AC magnetic controlled sputter sputtering technology film forming usually, target adopts ZnO, InGaZnO, InZnO, oxide ceramics sintered bodies such as InGaO.Sputtering pressure is 1Pa, makes in the metal-oxide film carrier concentration 10 by adjusting in the sputter gas ratio of oxygen and argon gas
10/ cm
3Below, thereby show the insulator characteristic.Etching technics adopts traditional wet etching technique usually.Etching liquid adopts the mixed liquor of phosphoric acid and hydrogen peroxide.
Described processing step d), photoresist thickness adopts the 1.2-2.0 micron usually, chemico-mechanical polishing pressure limit 100-150gm/cm
2, rotating speed is 60-200rpm.
Described processing step e), under vacuum, sample is heated to 300 ℃, keeps in air, cooling off after 60 minutes.Make the carrier concentration of processed sull increase to 10
13～10
15Cm
-3In the scope, thereby present characteristic of semiconductor.
Described processing step f), stripper adopts DMSO: MEA=7 usually: 3 (weight ratios).
Described processing step g), film-forming process adopts magnetron sputtering technique usually, and target adopts AlNd and MoNb alloy; Etching technics adopts traditional wet etching technique, and etching liquid adopts the mixed solution of phosphoric acid, sulfuric acid and acetic acid.
Embodiment 2
As shown in Figure 5, the technological process of present embodiment is similar to embodiment 1.Difference be in Fig. 5 (e) to adopt the method (820) of annealing in process in reducing atmosphere realize metal oxide by insulator to semi-conductive transformation.
Described processing step 820 is heated to 300 ℃ with sample under reducing atmospheres such as hydrogen or nitrogen, keep cooling off in air after 30 minutes.Make the carrier concentration of processed metal-oxide film increase to 10
13～10
15Cm
-3In the scope, thereby present characteristic of semiconductor.
Embodiment 3
As shown in Figure 6, the technological process of present embodiment is similar to embodiment 1.Difference be method (830) that in Fig. 6 (e) using plasma is handled realize metal oxide by insulator to semi-conductive transformation.
Described processing step 830 places vacuum chamber with sample, adopts argon plasma that sample is made 3～5 minutes plasma surface treatment, and discharge power is 150W.Make the carrier concentration of processed metal-oxide film increase to 10
13～10
15Cm
-3In the scope, thereby present characteristic of semiconductor.
Adopt the technological process among above-described embodiment 1-3, saved the processing step of active layer photoetching and etching, replace chemico-mechanical polishing and annealing (or plasma treatment) technology, conventional process flow more shown in Figure 2 is simple.
A kind of bottom gate metal oxide thin-film transistor structural representation of Fig. 3 for adopting the inventive method to prepare, its basic structure is as follows: be formed on the glass substrate substrate 310, comprise a gate electrode layer 320, one gate insulation layer 330, one metal oxide layer, 340, one drain electrode layer 351 and a source electrode layer 352.
Described gate electrode layer 310 is positioned on the glass substrate, is made of materials such as metallic aluminium, molybdenum, chromium usually.Gate electrode layer generally is made of aluminium neodymium/molybdenum niobium alloy in large scale flat panel display backplane technology, and it is bad that the conductive characteristic that can obtain can prevent that again " hillock " etc. from appearring in film surface.Gate electrode layer thickness is generally about 300 nanometers.
Described gate insulation layer is positioned on gate electrode and the glass substrate and the covering grid electrode layer, is made of silicon dioxide or silicon nitride usually, and film thickness is about 300 nanometers.
Described metal oxide layer is positioned on the gate insulation layer, can be the polycrystalline metal oxide materials of representative for zinc oxide (ZnO), also can be that indium gallium zinc oxygen (IGZO) is the amorphous metal oxide material of representative.It is characterized in that: metal oxide layer is divided into two zones, i.e. semiconductor regions and insulator region according to the difference of conductive characteristic; Be positioned near the metal-oxide film of channel region and present characteristic of semiconductor; Other regional metal-oxide film presents the insulator characteristic.The thickness of metal oxide layer can be in the 100-300 nanometer range.
Described source-drain electrode layer is positioned on the gate insulation layer and is overlapping with metal oxide layer near raceway groove, usually constituted by materials such as metallic aluminium, molybdenum, chromium, gate electrode layer generally is made of molybdenum niobium/aluminium neodymium/molybdenum niobium alloy in large scale flat panel display backplane technology, and it is bad that the conductive characteristic that can obtain can prevent that again " hillock " etc. from appearring in the film upper and lower surface.The thickness of source-drain electrode layer is generally about 300 nanometers.
Compared with prior art, the design feature of the metal oxide thin-film transistor of the present invention's preparation has been to eliminate the border on active layer island.The present invention has taken full advantage of metal oxide materials can divide the characteristics that are semiconductor and insulator under different technology conditions, active layer island in the common structure of metal oxide thin-film transistor is transferred in the insulating layer material that is embedded in equal thickness, so just removed the step that causes because of the existence of active layer island boundaries, thereby the stress that has reduced significantly in the source-drain electrode thin-film material of upper strata is concentrated, and then solved the difficult problem of source-drain electrode film easy fracture, effectively improved the production qualification rate.
Claims (8)
1. the preparation method of a bottom gate metal oxide thin-film transistor is characterized in that, may further comprise the steps:
The first step, adopt magnetron sputtering one deck gate electrode film and form gate electrode by photoetching and wet etching at substrate;
Second step, using plasma strengthens chemical vapour deposition (CVD) gate insulation layer material successively on gate electrode, and adopts AC magnetic controlled sputtered metal oxide material;
The 3rd step, adopt chemico-mechanical polishing to carry out planarization at metal oxide materials surface applied photoresist and to photoresist layer;
The 4th step, by annealing in process or plasma treatment not by the metal oxide of photoresist masking, make it to be converted into carrier concentration and increase to 10
13-10
15Cm
-3Semiconductor;
The 5th step, stripping photoresist and magnetron sputtering deposition source-drain electrode material also form source-drain electrode by photoetching and wet etching.
2. the preparation method of bottom gate metal oxide thin-film transistor according to claim 1, it is characterized in that, the first step, magnetron sputtering described in second step and the 5th step refers to: utilize argon plasma under the effect in electric field and magnetic field, the high-energy ion bombardment target material surface that is accelerated, after the energy exchange, the atom of target material surface breaks away from former lattice and overflows, transfer to substrate surface and film forming, sputtering power is 100W, gas pressure is 1Pa, the proportion of oxygen and argon gas is in the sputter gas: 1: 20～1: 100 and argon flow amount are 30sccm, and the material of gate electrode film wherein is: aluminium, molybdenum or chromium metal or its alloy.
3. the preparation method of bottom gate metal oxide thin-film transistor according to claim 1 is characterized in that, described wet etching refers to: it is 55wt%H that the etching material is immersed in composition
3PO
4, 15wt%HNO
3, 5wt%CH
3COOH and 25wt%H
2Corrode in the etching liquid of O.
4. the preparation method of bottom gate metal oxide thin-film transistor according to claim 1, it is characterized in that, described plasma enhanced chemical vapor deposition refers to: the auxiliary reactive material down in the plasma discharge process issues biochemical reaction in the gaseous state condition, generate the substrate surface that solid matter is deposited on heating, and then making solid film, gate insulation layer material wherein refers to: silicon dioxide or silicon nitride.
5. according to the preparation method of the described bottom gate metal oxide thin-film transistor of above-mentioned arbitrary claim, it is characterized in that described metal oxide materials refers to: zinc oxide, indium oxide gallium zinc, indium zinc oxide or indium oxide gallium, its carrier concentration is 10
10/ cm
3Below.
6. the preparation method of bottom gate metal oxide thin-film transistor according to claim 1 is characterized in that, the thickness of the photoresist layer described in the 3rd step is the 1.2-2.0 micron; Described employing chemico-mechanical polishing refers to: adopt 100-150gm/cm
2Pressure, photoresist layer is polished smooth with the rotating speed of 60-200rpm.
7. the preparation method of bottom gate metal oxide thin-film transistor according to claim 1 is characterized in that, the annealing described in the 4th step refers to: under vacuum or reducing atmosphere in the process of 200～400 ℃ of heat treated; Described plasma treatment refers to: adopt argon plasma that device is carried out 1～3 minute surface-treated process.
8. the preparation method of bottom gate metal oxide thin-film transistor according to claim 1 is characterized in that, peeling off described in the 5th step refers to: adopt dimethyl sulfoxide (DMSO) and monoethanolamine by weight for the mixing stripper of 7:3 photoresist being removed.
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| KR102110226B1 (en) * | 2013-09-11 | 2020-05-14 | 삼성디스플레이 주식회사 | Display panel and method for fabricating the same |
| CN105702742A (en) * | 2016-02-25 | 2016-06-22 | 深圳市华星光电技术有限公司 | Oxide film transistor and preparation method thereof |
| CN107146818B (en) * | 2017-06-27 | 2020-02-18 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
| KR102142268B1 (en) * | 2018-06-25 | 2020-08-12 | 삼성전자 주식회사 | Thin film transistor and vertical non-volatile memory device including transition metal-induced polycrystalline metal oxide channel layer |
| CN112420519B (en) * | 2020-11-19 | 2021-06-08 | 绵阳惠科光电科技有限公司 | Preparation method of indium gallium zinc oxide thin film transistor device |
| CN114171457B (en) * | 2021-12-07 | 2023-07-04 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN114509903B (en) * | 2022-02-10 | 2024-02-13 | 武汉华星光电技术有限公司 | display panel |
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| CN101859799A (en) * | 2009-04-02 | 2010-10-13 | 株式会社半导体能源研究所 | The manufacture method of semiconductor device and this semiconductor device |
| EP2256795A1 (en) * | 2009-05-29 | 2010-12-01 | Semiconductor Energy Laboratory Co., Ltd. | Oxide semiconductor device and manufacturing method thereof |
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