CN102130184A - High-robustness back biased diode applied to high-voltage static protection - Google Patents
High-robustness back biased diode applied to high-voltage static protection Download PDFInfo
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- CN102130184A CN102130184A CN 201010600772 CN201010600772A CN102130184A CN 102130184 A CN102130184 A CN 102130184A CN 201010600772 CN201010600772 CN 201010600772 CN 201010600772 A CN201010600772 A CN 201010600772A CN 102130184 A CN102130184 A CN 102130184A
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Abstract
The invention discloses a high-robustness back biased diode applied to high-voltage static protection, comprising a P type substrate, wherein a buried oxide layer is arranged on the P type substrate; a P type epitaxial layer is arranged on the buried oxide layer; a first low-voltage P type well, a first low-voltage N type well and a second high-voltage N type well are arranged at the upper part of the P type epitaxial layer; a P type anode region is arranged in the first low-voltage P type well; an N type cathode region is arranged in the second high-voltage N type well and cathode metal is connected to the N type cathode region; and anode metal is connected to the P type anode region. The high-robustness back biased diode is characterized in that a P type cathode region connected to the cathode metal is arranged on the upper surface inside the second high-voltage N type well and is tightly attached to the right boundary of the N type cathode region; a second P type buffer well is arranged in the first low-voltage P type well; and the P type anode region is positioned in the second P type buffer well. By using the device, the trigger voltage in the static protection process can be effectively reduced and the secondary breakdown current of a lifting device is greatly improved, and thereby the high-robustness back biased diode has better robustness.
Description
Technical field
The present invention relates to the reliability field of integrated circuit, is the high robust back biased diode structure that is applicable to the high-pressure electrostatic protection about a kind of.
Background technology
Along with energy-conservation demand strengthens day by day, the performance of power integrated circuit product more and more receives publicity, and wherein the integrity problem of circuit also comes also to be subjected to circuit design engineer's attention more.Along with constantly dwindling of technology characteristics size, how on littler area, to design and to realize that electrostatic discharge protection does not have the electrostatic protection device of breech lock risk to become a puzzlement greatly of high-pressure process again.
At present, the manufacturing process according to power integrated circuit mainly is divided into based on body silicon, extension and silicon-on-insulator (SOI).Wherein, bulk silicon technological is because there is more defective in silicon face layer, so the large scale integrated circuit mainly adopts this technology in early days; Silicon-on-insulator (SOI) technology is owing to exist insulating barrier that surface silicon and substrate silicon layer are isolated, insulating barrier is generally silica in addition, vertical puncture voltage of the device of this technology of employing is higher like this, simultaneously substrate current there is good restraining, help reducing the power consumption of device, yet, cause the heat dissipation problem of power integrated circuit more serious, and the disk cost of silicon-on-insulator process is higher because the heat-sinking capability of silicon oxide layer is 1/100 of a silicon layer; Epitaxy technique has solved the blemish problem that bulk silicon technological exists well, has heat dispersion preferably simultaneously, so be widely used based on the power integrated circuit design of epitaxy technique.
At the electrostatic protection of low pressure process, people have worked out many devices that can meet the different needs, comprising grounded-grid N type metal oxide layer semiconductor transistor, forward bias diode, triode and silicon controlled rectifier.These devices with and the electrostatic protection exploitation of structure in low pressure process be tending towards ripe, but but have very big problem in the design of the electrostatic protection in high-pressure process.So wherein grounded-grid N type metal oxide layer semiconductor transistor, triode and silicon controlled rectifier are because there is very big breech lock risk in its very low voltage of keeping; the withstand voltage low of forward bias diode can not be satisfied requirement of withstand voltage, is very restricted in the design of the electrostatic protection of structure in high-pressure process more than these shortcomings make and the application.
At present at the electrostatic protection of high-pressure process the most frequently used two kinds of structures are arranged, the one, the transient state diode, another is a back biased diode.Being most widely used of transient state diode; its advantage be the response time fast, transient power is big, leakage current is low, puncture voltage deviation, clamping voltage are more easy to control, do not have the limit of damage, volume is little; but maximum shortcoming is to be integrated in the same chip with circuit, belongs to discrete electrostatic protection device.So people have designed the back biased diode that can develop simultaneously with circuit in same technology, its maximum shortcoming be because trigger voltage is higher snowslide after high electric field make that the second breakdown electric current is lower, promptly the robustness of device is lower.For the second breakdown electric current of boost device usually adopts the Method for Area that strengthens device, the increase that can bring cost like this.
Round the requirement of the electrostatic protection of high-pressure process to low trigger voltage, high robust, low breech lock risk and lower cost; this paper has introduced a kind of novel back biased diode; compare its trigger voltage under same size with traditional back biased diode lower and the second breakdown electric current is higher, thereby possess higher robustness.
Summary of the invention
The present invention provides a kind of and can effectively reduce the back biased diode that trigger voltage improves the high-pressure electrostatic protection of device robustness, and do not have the breech lock risk in high-pressure process on the basis of the area that does not change device.
The present invention adopts following technical scheme:
A kind of high robust back biased diode that is applied to the high-pressure electrostatic protection; comprise: P type substrate; on P type substrate, be provided with and bury oxide layer; be provided with P type epitaxial loayer on the oxide layer burying; be provided with the first low pressure P type trap on the top of P type epitaxial loayer; the first low pressure N type trap and the second high-pressure N-shaped trap and the described second high-pressure N-shaped trap extend to the lower surface of P type epitaxial loayer from the upper surface of P type epitaxial loayer; in the first low pressure P type trap, be provided with P type Yang Qu; in the second high-pressure N-shaped trap, be provided with the cloudy district of N type; be provided with field oxide and described field oxide on the upper surface of P type epitaxial loayer between the second high-pressure N-shaped trap and P type sun district; at the second high-pressure N-shaped trap; the upper surface of field oxide and P type Yang Qu is provided with passivation layer; in the cloudy district of N type, be connected with cathodic metal; on P type Yang Qu, be connected with anode metal; it is characterized in that; upper surface in the described second high-pressure N-shaped trap inside also is provided with the cloudy district of the P type that is connected in cathodic metal; and the right margin in the cloudy district of N type is close in the cloudy district of P type; be provided with the 2nd P type buffering trap in the described first low pressure P type trap, described P type Yang Qu is positioned at second P type buffering trap.
Compared with prior art, the present invention has following advantage:
(1) this structure is compared with traditional back biased diode that is used for electrostatic protection, has added a cloudy district of new P type at negative electrode.When negative electrode faces electrostatic stress, the anti-inclined to one side living avalanche breakdown of binding up one's hair of device, electron stream that snowslide produces and hole flow point are not collected by cloudy district 9 of N type and P type sun district 6.These portions of electronics streams of collecting by the cloudy district 9 of N type make when flowing through 10 belows, the cloudy district of P type the cloudy district of P type down the current potential in 10 N type zone descend, when the current potential in the cloudy district 10 of P type is higher than 0.7V than the current potential in the N type zone under it, a large amount of hole stream is injected in cloudy district 10 beginnings of P type in device body, therefore compare with traditional back biased diode, this structure has increased a new current injection area territory and then can improve the ability of device leakage current.
(2) this structure is compared with traditional back biased diode, has added new the 2nd P type buffering trap 5 in a bag P type sun district 6 at anode.In general; under big injection situation; the Kirk effect can take place in the PNP pipe of this device parasitism; it is the base broadening effect; make the interface of the PN junction that the snowslide peak of device is made up of the first original low pressure N trap 8 and the first low pressure P trap 4 transfer near the P type sun district 6; because P type sun district 6 is heavy doping; thereby peak electric field can be higher under the same voltage; thereby under the same current density because the local heat that produces with the product relation in direct ratio of electric field and electric current thereby can make near the P type sun district 6 the higher heat of generation make device that second breakdown just take place under lower current density to cause device to burn; and this 2nd P type buffering trap 5 that is provided with can suppress the generation of Kirk effect; and reduce the peak value electric field of this part and then reduce the generation of amount of localized heat, prevent device too early burning in the electrostatic protection process.
Second effect of (3) the 2nd P types buffering trap 5 is the Kirk effects by suppression device, reduces the peak value electric field in the cloudy district 10 of P type and then reduced the avalanche multiplication factor, makes the voltage of keeping of device raise, thereby reduced the risk of breech lock.
The 3rd effect of (4) the 2nd P types buffering trap 5 is the static trigger voltages that reduced this device, because an anti-low-doped side of PN junction has partially determined the puncture voltage of device, the 2nd P type cushions the concentration that the first low pressure P trap 4 that can promote this device is set of trap 5 thereby has reduced trigger voltage.
(5) this structure is compared with traditional back biased diode, is provided with polysilicon field plate 14 and described polysilicon field plate 14 across the first low pressure P type trap 4 and the first low pressure N type trap 8 on field oxide 13.Polysilicon field plate 14 the PN junction electric field that can reduce effectively between the first low pressure P type trap 4 and the first low pressure N type trap 8 is set, thereby prevent the excessive buildup of this PN junction place temperature.
(6) device of the present invention do not change the original chip area of device when trigger voltage improves the device robustness reducing, and do not need extra too much technological process.
Description of drawings
Fig. 1 is a profile, illustrates the high robust back biased diode cross-section structure that is used for the high-pressure electrostatic protection among the present invention.
Fig. 2 is the equivalent circuit diagram that is used for the high robust back biased diode of high-pressure electrostatic protection among the present invention.
Fig. 3 be used among the present invention the high robust back biased diode of high-pressure electrostatic protection and traditional high-voltage diode the comparison diagram of transmission line pulse (TLP) test result, the device parallel connection that all to adopt 4 width be 70um.
Fig. 4 is the process schematic representation that forms the second high-pressure N-shaped trap 11 of the high robust back biased diode that is used for the high-pressure electrostatic protection among the present invention.
Fig. 5 is the process schematic representation that forms the first low pressure N type trap 8 of the high robust back biased diode that is used for the high-pressure electrostatic protection among the present invention.
Fig. 6 is the process schematic representation that forms the first low pressure P type trap 4 of the high robust back biased diode that is used for the high-pressure electrostatic protection among the present invention.
Fig. 7 is the process schematic representation that forms the 2nd P type buffering trap 5 of the high robust back biased diode that is used for the high-pressure electrostatic protection among the present invention.
Fig. 8 forms the field oxygen 13 of the high robust back biased diode that is used for the high-pressure electrostatic protection among the present invention and the process schematic representation of polysilicon field plate 14.
Fig. 9 is the process schematic representation that forms the high robust back biased diode P type sun district 6, the cloudy district 10 of P type and the cloudy district 9 of N type that are used for the high-pressure electrostatic protection among the present invention.
Figure 10 is the profile that is completed into the high robust back biased diode that is used for the high-pressure electrostatic protection among the present invention.
Embodiment
A kind of high robust back biased diode that is applied to the high-pressure electrostatic protection; comprise: P type substrate 1; on P type substrate 1, be provided with and bury oxide layer 2; be provided with P type epitaxial loayer 3 on the oxide layer 2 burying; be provided with the first low pressure P type trap 4 on the top of P type epitaxial loayer 3; the first low pressure N type trap, the 8 and second high-pressure N-shaped trap 11 and the described second high-pressure N-shaped trap 11 extend to the lower surface of P type epitaxial loayer 3 from the upper surface of P type epitaxial loayer 3; in the first low pressure P type trap 4, be provided with P type sun district 6; in the second high-pressure N-shaped trap 11, be provided with the cloudy district 9 of N type; be provided with field oxide 13 and described field oxide 13 on the upper surface of P type epitaxial loayer 3 between the second high-pressure N-shaped trap 11 and P type sun district 6; at the second high-pressure N-shaped trap 11; the upper surface in field oxide 13 and P type sun district 6 is provided with passivation layer 15; in the cloudy district 9 of N type, be connected with cathodic metal 12; in P type sun district 6, be connected with anode metal 7; upper surface in the described second high-pressure N-shaped trap 11 inside also is provided with the cloudy district 10 of the P type that is connected in cathodic metal 12; and the right margin in the cloudy district 9 of N type is close in the cloudy district 10 of P type; be provided with the 2nd P type buffering trap 5 in the described first low pressure P type trap 4, described P type sun district 6 is positioned at the 2nd P type buffering trap 5.
Be provided with polysilicon field plate 14 and described polysilicon field plate 14 across the first low pressure P type trap 4 and the first low pressure N type trap 8 at described field oxide 13 upper surfaces.
Described polysilicon field plate 14 projections differ in the length of the first low pressure P type trap 4 and the first low pressure N type trap 8 and are no more than 1 micron.
The present invention adopts following method to prepare:
The first step is got the silicon-on-insulator disk with P type epitaxial loayer, inject by the high-energy phosphonium ion, and high annealing forms the second high-pressure N-shaped trap 11 and P type epitaxial loayer 3.
Second step, inject with high-octane phosphonium ion, form the first low pressure N type trap 8 behind the high annealing.
The 3rd step, inject with high-octane boron ion, form the first low pressure P type trap 4 behind the high annealing.
The 4th step, inject with high-octane boron ion, on the first low pressure P trap 4, form the 2nd P type buffering trap 5 behind the high annealing.
The 5th step, deposit and etch silicon nitride, the field oxide of at high temperature growing, and deposit polysilicon etch the polysilicon field plate.
In the 6th step,, make each electrode contact zone by the boron ion and the phosphonium ion injection of high dose.
The 7th step, deposit silicon dioxide, depositing metal trace layer and etch away excess metal behind the etching electrode contact hole.
In the 8th step, carry out the making of passivation layer.
Claims (5)
1. one kind is applied to the high robust back biased diode that high-pressure electrostatic is protected; comprise: P type substrate (1); on P type substrate (1), be provided with and bury oxide layer (2); be provided with P type epitaxial loayer (3) on the oxide layer (2) burying; be provided with the first low pressure P type trap (4) on the top of P type epitaxial loayer (3); the first low pressure N type trap (8) and the second high-pressure N-shaped trap (11) and the described second high-pressure N-shaped trap (11) extend to the lower surface of P type epitaxial loayer (3) from the upper surface of P type epitaxial loayer (3); in the first low pressure P type trap (4), be provided with P type Yang Qu (6); in the second high-pressure N-shaped trap (11), be provided with the cloudy district of N type (9); be positioned between the second high-pressure N-shaped trap (11) and the P type Yang Qu (6) being provided with field oxide (13) and described field oxide (13) on the upper surface of P type epitaxial loayer (3); at the second high-pressure N-shaped trap (11); the upper surface of field oxide (13) and P type Yang Qu (6) is provided with passivation layer (15); in the cloudy district of N type (9), be connected with cathodic metal (12); on P type Yang Qu (6), be connected with anode metal (7); it is characterized in that; also be provided with the cloudy district of P type (10) that is connected in cathodic metal (12) at the inner upper surface of the described second high-pressure N-shaped trap (11); and the right margin in the cloudy district of N type (9) is close in the cloudy district of P type (10); be provided with the 2nd P type buffering trap (5) in the described first low pressure P type trap (4), described P type Yang Qu (6) is positioned at the 2nd P type buffering trap (5).
2. a kind of high robust back biased diode that is applied to the high-pressure electrostatic protection according to claim 1 is characterized in that the length in the cloudy district of described P type (10) is greater than the length in the cloudy district of N type (9).
3. a kind of high robust back biased diode that is applied to the high-pressure electrostatic protection according to claim 1 is characterized in that the adjacent boundary between the described first low pressure P type trap (4) and the first low pressure N type trap (8) contacts.
4. a kind of high robust back biased diode that is applied to the high-pressure electrostatic protection according to claim 1 is characterized in that being provided with polysilicon field plate (14) and described polysilicon field plate (14) across the first low pressure P type trap (4) and the first low pressure N type trap (8) between field oxide (13) and passivation layer (15).
5. a kind of high robust back biased diode that is applied to the high-pressure electrostatic protection according to claim 4; it is characterized in that the length of length and the remainder polysilicon field plate (14) that is positioned at the first low pressure N type trap (8) top that is positioned at a part of polysilicon field plate (14) of the first low pressure P type trap (4) top differs within 1 micron.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010600772A CN102130184B (en) | 2010-12-22 | 2010-12-22 | High-robustness back biased diode applied to high-voltage static protection |
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| CN201010600772A CN102130184B (en) | 2010-12-22 | 2010-12-22 | High-robustness back biased diode applied to high-voltage static protection |
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| CN102130184A true CN102130184A (en) | 2011-07-20 |
| CN102130184B CN102130184B (en) | 2012-10-10 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105374814A (en) * | 2015-10-14 | 2016-03-02 | 东南大学 | High-robustness high-voltage electrostatic discharge protector |
| CN108807373A (en) * | 2018-06-25 | 2018-11-13 | 湖南大学 | electrostatic protection device |
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| US20090020814A1 (en) * | 2007-01-12 | 2009-01-22 | Yong-Cheol Choi | High Voltage Semiconductor Device with Floating Regions for Reducing Electric Field Concentration |
| CN101587894A (en) * | 2008-05-16 | 2009-11-25 | 万国半导体股份有限公司 | Electrostatic discharge (esd) protection applying high voltage lightly doped drain (ldd) cmos technologies |
| CN101673684A (en) * | 2009-09-22 | 2010-03-17 | 上海宏力半导体制造有限公司 | Method for manufacturing electro-static discharge protection diodes in high-voltage process |
| CN201904344U (en) * | 2010-12-22 | 2011-07-20 | 东南大学 | High-robustness back biased diode applied to high-voltage electrostatic protection |
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2010
- 2010-12-22 CN CN201010600772A patent/CN102130184B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1990014690A1 (en) * | 1989-05-17 | 1990-11-29 | David Sarnoff Research Center, Inc. | Voltage stress alterable esd protection structure |
| JP2001257366A (en) * | 2000-03-10 | 2001-09-21 | Toshiba Corp | Semiconductor device |
| CN1851923A (en) * | 2006-05-24 | 2006-10-25 | 杭州电子科技大学 | SOI LIGBT device unit of integrated ESD diode |
| US20090020814A1 (en) * | 2007-01-12 | 2009-01-22 | Yong-Cheol Choi | High Voltage Semiconductor Device with Floating Regions for Reducing Electric Field Concentration |
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| CN201904344U (en) * | 2010-12-22 | 2011-07-20 | 东南大学 | High-robustness back biased diode applied to high-voltage electrostatic protection |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105374814A (en) * | 2015-10-14 | 2016-03-02 | 东南大学 | High-robustness high-voltage electrostatic discharge protector |
| WO2017063320A1 (en) * | 2015-10-14 | 2017-04-20 | 东南大学 | High-robustness high-voltage electrostatic discharge protection device |
| CN108807373A (en) * | 2018-06-25 | 2018-11-13 | 湖南大学 | electrostatic protection device |
| CN108807373B (en) * | 2018-06-25 | 2021-04-13 | 湖南大学 | Electrostatic protection device |
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| CN102130184B (en) | 2012-10-10 |
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