CN102122949B - A kind of flash memory circuit - Google Patents
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- CN102122949B CN102122949B CN201110057568.3A CN201110057568A CN102122949B CN 102122949 B CN102122949 B CN 102122949B CN 201110057568 A CN201110057568 A CN 201110057568A CN 102122949 B CN102122949 B CN 102122949B
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Abstract
A kind of flash memory circuit, at least include peripheral circuit and row decoding circuit, wherein said row decoding circuit includes level shift circuit, word line selection circuit and drives latch cicuit, wherein said level shift circuit includes: the first pull-up metal-oxide-semiconductor and the second pull-up metal-oxide-semiconductor, first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor and the first phase inverter, by increasing the source voltage of the first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor, make the described source voltage grid voltage more than the first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor；Increase the first pull-up metal-oxide-semiconductor and the underlayer voltage of the second pull-up metal-oxide-semiconductor simultaneously, make described underlayer voltage pull up metal-oxide-semiconductor and the source voltage of the second pull-up metal-oxide-semiconductor more than first.The present invention is by the improvement to the level shift circuit in existing flash memory circuit so that when flash memory system is in standby, it is possible to reduces the leakage current flowing through metal-oxide-semiconductor, makes metal-oxide-semiconductor will not be subject to the infringement of high leakage current.
Description
Technical field
The present invention relates to flash memory design circuit field, particularly to a kind of flash memory circuit.
Background technology
As it is shown in figure 1, mainly include peripheral circuit 11, row decoding circuit 12, array decoding circuit 13 and storage array 14 in existing flash memory 1.Wherein, described peripheral circuit 11 is connected with described row decoding circuit 12 and described array decoding circuit 13 respectively, and described row decoding circuit 12 is connected with storage array 14 with described array decoding circuit 13.Further, described row decoding circuit 12 also includes level shift circuit 121, word line selection circuit 122 and driving latch cicuit 123, wherein said level shift circuit 121 is connected with the word line selection circuit 122 of rear stage, and described word line selection circuit 122 is connected with described driving latch cicuit 123.Specifically, described level shift circuit is similar to a voltage switch, the high level signal of output complementation and low level signal, then word line selection circuit selects corresponding wordline according to the high level signal received or low level signal, and by driving latch cicuit 123 to drive corresponding wordline in described storage array 14.Specifically, it is possible to reference to the method that Chinese Patent Application No. is 201010161459.1 structures disclosing a kind of voltage level shifter and voltage level shifting.
The schematic diagram of level shift circuit in prior art is illustrated with reference to Fig. 2.Specifically, the receiving terminal IN1 of described level shift circuit receives the input signal including high level signal and low level signal, and exports the output signal with voltage level complementation in output terminals A and outfan B.
As in figure 2 it is shown, described level shift circuit includes pull-up metal-oxide-semiconductor 101 and 102, drop-down metal-oxide-semiconductor 103 and 104 and the first phase inverter 105, wherein said pull-up metal-oxide-semiconductor 101 and 102 is P-channel type metal-oxide-semiconductor, described drop-down metal-oxide-semiconductor 103 and 104 is N-channel type metal-oxide-semiconductor.Further, the source electrode of described pull-up metal-oxide-semiconductor 101 and 102 is connected on voltage ZVDD2, described pull-up metal-oxide-semiconductor 101 with 102 drain electrode be connected with the drain electrode of described drop-down metal-oxide-semiconductor 103 and 104 composition output terminals A and outfan B, the source ground of described drop-down metal-oxide-semiconductor 103 and 104.Described input IN1 is connected with the grid of described drop-down metal-oxide-semiconductor 103, is connected with the grid of described drop-down metal-oxide-semiconductor 104 after the first phase inverter 105.
The operation principle of described level shift circuit is as follows: when the input signal of described input IN1 is high level signal, and described drop-down metal-oxide-semiconductor 103 turns on, and the output signal of outfan B is pulled down to 0V (i.e. ground connection)；Then make pull-up metal-oxide-semiconductor 102 turn on, the output signal of output terminals A is pulled to ZVDD2；Then pull-up metal-oxide-semiconductor 101 is made to end, so that it is guaranteed that the output signal of outfan B is 0V.
On the contrary, when the input signal of described input IN1 is low level signal, described drop-down metal-oxide-semiconductor 103 ends, and described drop-down metal-oxide-semiconductor 104 turns on, and the output signal of output terminals A is pulled down to 0V (i.e. ground connection)；Then make described pull-up metal-oxide-semiconductor 101 turn on, the output signal of outfan B is pulled to ZVDD2；Then described pull-up metal-oxide-semiconductor 102 is made to end, it is ensured that the output signal of output terminals A is 0V.
But, in above-mentioned level shift circuit, when each metal-oxide-semiconductor is when cut-off state, usually can there is more serious leaky, thus metal-oxide-semiconductor is produced infringement.At present, in existing technology for this problem but without good solution.
Summary of the invention
The problem that this invention address that is to provide a kind of flash memory circuit, reduces the leakage current of each metal-oxide-semiconductor of the level shift circuit flow through in described flash memory circuit.
For solving the problems referred to above, the present invention provides a kind of flash memory circuit, at least include peripheral circuit and row decoding circuit, wherein said row decoding circuit includes level shift circuit, word line selection circuit and driving latch cicuit, wherein said level shift circuit includes: the first pull-up metal-oxide-semiconductor and the second pull-up metal-oxide-semiconductor, first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor and the first phase inverter, the source electrode of described first drop-down metal-oxide-semiconductor and the source electrode of described second drop-down metal-oxide-semiconductor are connected to the first voltage end and the second voltage end, the voltage of wherein said first voltage end is more than the grid voltage of the first drop-down metal-oxide-semiconductor, the voltage of described second voltage end is more than the grid voltage of the second drop-down metal-oxide-semiconductor；The substrate of described first pull-up metal-oxide-semiconductor and the substrate of described second pull-up metal-oxide-semiconductor are connected to tertiary voltage end and the 4th voltage end, the voltage of wherein said tertiary voltage end is more than the described first source voltage pulling up metal-oxide-semiconductor, and the voltage of described 4th voltage end is more than the described second source voltage pulling up metal-oxide-semiconductor.
Alternatively, the source electrode of the first pull-up metal-oxide-semiconductor described in described level shift circuit and the second pull-up metal-oxide-semiconductor is connected on the first running voltage end, the grid of described first pull-up metal-oxide-semiconductor is connected to the drain electrode of the second pull-up metal-oxide-semiconductor, and the grid of described second pull-up metal-oxide-semiconductor is connected to the drain electrode of the first pull-up metal-oxide-semiconductor；The grid of described first drop-down metal-oxide-semiconductor is connected to the input of described level shift circuit, the drain electrode of described first pull-up metal-oxide-semiconductor and the second pull-up metal-oxide-semiconductor is connected to form two outfans with the drain electrode of described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor respectively, the input of described first phase inverter is connected to the grid of described first drop-down metal-oxide-semiconductor, and outfan is connected to the grid of described second drop-down metal-oxide-semiconductor.
Alternatively, the first voltage end described in described level shift circuit is the outfan of described first phase inverter.
Alternatively, the second voltage end described in described level shift circuit is the input of described first phase inverter.
Alternatively, described peripheral circuit at least includes voltage regulator circuit, described voltage regulator circuit and the first running voltage end, tertiary voltage end and the 4th voltage end are connected, and described voltage regulator circuit produces the voltage of the voltage of described first running voltage end, the voltage of described tertiary voltage end and described 4th voltage end.
Alternatively, the voltage of described tertiary voltage end and the voltage of described 4th voltage end are equal.
Alternatively, described voltage regulator circuit includes multi stage charge pump, single stage charge pump, comparison controller and switching circuit；Described single stage charge pump is connected to the outfan of described multi stage charge pump；The outfan of described comparison controller and single stage charge pump is connected to the input of described switching circuit；The outfan of described switching circuit exports the voltage of the voltage of described first running voltage end, the voltage of described tertiary voltage end and described 4th voltage end respectively.
Alternatively, described level shift circuit also includes power supply circuits, the input of wherein said power supply circuits is connected with peripheral circuit, described power supply circuits respectively with described first pull up metal-oxide-semiconductor drain electrode, described second pull-up metal-oxide-semiconductor drain electrode be connected, the drain electrode of described first drop-down metal-oxide-semiconductor, described second drop-down metal-oxide-semiconductor drain electrode be connected, export the second running voltage to described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor.
Alternatively, described power supply circuits include the first high-voltage tube and the second high-voltage tube, the grid of wherein said first high-voltage tube and the second high-voltage tube is connected to the drain electrode of the input of described power supply circuits, described first high-voltage tube and the second high-voltage tube and is connected with the drain electrode of described first pull-up metal-oxide-semiconductor and the second pull-up metal-oxide-semiconductor respectively, and the source electrode of described first high-voltage tube and the second high-voltage tube is connected with the drain electrode of described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor respectively；Described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor are low-voltage tubes.
Alternatively, described first high-voltage tube and described second high-voltage tube are N-channel type metal-oxide-semiconductors.
Alternatively, the first pull-up metal-oxide-semiconductor described in described level shift circuit and the second pull-up metal-oxide-semiconductor are P-channel type metal-oxide-semiconductors, and described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor are N-channel type metal-oxide-semiconductors.
Compared with prior art, the embodiment of the present invention has the advantage that on the basis of the level shift circuit in existing flash memory circuit, by increasing the source voltage of the first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor, makes described source voltage more than grid voltage；Increase the first pull-up metal-oxide-semiconductor and the underlayer voltage of the second pull-up metal-oxide-semiconductor simultaneously, make described underlayer voltage more than source voltage.So when any of the above-described metal-oxide-semiconductor cut-off, it is possible to reduce the leakage current flowing through metal-oxide-semiconductor, make metal-oxide-semiconductor will not be subject to the infringement of high leakage current.
Accompanying drawing explanation
Fig. 1 is the structural schematic block diagram of existing flash memory circuit；
Fig. 2 is the schematic diagram of existing level shift circuit；
Fig. 3 is the schematic diagram of the first embodiment of level shift circuit provided by the invention；
Fig. 4 is the schematic diagram of the second embodiment of level shift circuit provided by the invention；
Fig. 5 is the schematic block diagram of the voltage regulator circuit in flash memory circuit of the present invention in peripheral circuit.
Detailed description of the invention
Inventor have found that in the level shift circuit of existing row decoding circuit, when each metal-oxide-semiconductor is in cut-off state, more serious leaky usually can occur so that described metal-oxide-semiconductor is subject to the infringement of high leakage current.Such as, with reference to the level shift circuit shown in Fig. 2, when the input signal of input IN1 is low level signal, the Vgs of drop-down metal-oxide-semiconductor 103 is 0V, but still can produce leakage current due to sub-threshold leakage and flow through described drop-down metal-oxide-semiconductor 103.Again such as, when the input signal of input IN1 is high level signal, pull-up metal-oxide-semiconductor 101 ends, but due to the sub-threshold leakage of described pull-up metal-oxide-semiconductor, still can produce leakage current and flow through described pull-up metal-oxide-semiconductor 101.
Therefore, for the problems referred to above, the connected mode of metal-oxide-semiconductor in existing level shift circuit is made and is changed by inventor, drop-down metal-oxide-semiconductor source electrode is connected to more than on the voltage end of its grid voltage, by pull-up metal-oxide-semiconductor substrate be connected to more than on the voltage end of its source voltage, thus reducing the leakage current flowing through each metal-oxide-semiconductor, reduce the power consumption of the whole flash memory system each metal-oxide-semiconductor when standby.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
First, with reference to the schematic block diagram of the voltage regulator circuit in peripheral circuit in the flash memory circuit shown in Fig. 5.Described voltage regulator circuit produces the voltage of the voltage of the first running voltage end needed for level shift circuit described in the embodiment of the present invention, the voltage of tertiary voltage end and the 4th voltage end.Alternatively, wherein, the voltage of described tertiary voltage end and the voltage of the 4th voltage end are equal.Specifically, in an embodiment of the present invention, the voltage of described first running voltage end is ZVDD2, and the voltage of described tertiary voltage end and the voltage of the 4th voltage end are ZVDD2_PLUS, and described ZVDD2_PLUS is more than described ZVDD2.Specifically, as it is shown in figure 5, described voltage regulator circuit includes multi stage charge pump 111, single stage charge pump 112, comparison controller 113 and switching circuit 114.Wherein, described single stage charge pump 112 is connected to the outfan of the outfan of described multi stage charge pump 111, described comparison controller 113 and single stage charge pump and is connected to the input of described switching circuit 114.Then, the outfan of described switching circuit 114 exports described voltage ZVDD2_PLUS and described voltage ZVDD2 respectively.It should be noted that described voltage ZVDD2 is produced by described multi stage charge pump 111, described voltage ZVDD2_PLUS is produced jointly by described multi stage charge pump 111 and single stage charge pump 112.
First embodiment schematic diagram with reference to level shift circuit as shown in Figure 3.Specifically, described level shift circuit includes first pull-up metal-oxide-semiconductor the 101, second pull-up metal-oxide-semiconductor 102, first drop-down metal-oxide-semiconductor the 103, second drop-down metal-oxide-semiconductor 104 and the first phase inverter 105.Alternatively, described first pull-up metal-oxide-semiconductor 101 and the second pull-up metal-oxide-semiconductor 102 are P-channel type metal-oxide-semiconductors, and described first drop-down metal-oxide-semiconductor 103 and the second drop-down metal-oxide-semiconductor 104 are N-channel type metal-oxide-semiconductors.
The source electrode of described first pull-up metal-oxide-semiconductor 101 and the second pull-up metal-oxide-semiconductor 102 is connected on the first running voltage end, and the voltage of described first running voltage end is ZVDD2.The grid of described first pull-up metal-oxide-semiconductor 101 is connected to the drain electrode of the second pull-up metal-oxide-semiconductor 102, the grid of described second pull-up metal-oxide-semiconductor 102 is connected to the drain electrode of the first pull-up metal-oxide-semiconductor 101, the grid of described first drop-down metal-oxide-semiconductor 103 and the second drop-down metal-oxide-semiconductor 104 is connected to input IN1, the drain electrode of described first pull-up metal-oxide-semiconductor 101 and the second pull-up metal-oxide-semiconductor 102 is connected to form two output terminals A and B with the drain electrode of described first drop-down metal-oxide-semiconductor 103 and the second drop-down metal-oxide-semiconductor 104 respectively, the input of described first phase inverter 105 is connected to the grid of described first drop-down metal-oxide-semiconductor 103, outfan is connected to the grid of described second drop-down metal-oxide-semiconductor 104.
With existing level shift circuit the difference is that, the source electrode of described first drop-down metal-oxide-semiconductor 103 is connected to the first voltage end, in the present embodiment be described first phase inverter 105 outfan, be connected with the grid of described second drop-down metal-oxide-semiconductor 104.The source electrode of described second drop-down metal-oxide-semiconductor 104 is connected to the second voltage end, is the input of described first phase inverter 105 in the present embodiment, is connected with the grid of described first drop-down metal-oxide-semiconductor 103.It is connected to tertiary voltage end and the 4th voltage end at the described first substrate pulling up metal-oxide-semiconductor 101 and described second pull-up metal-oxide-semiconductor 102, in the present embodiment, the voltage of described tertiary voltage end and the voltage of described 4th voltage end are equal, the ZVDD2_PLUS that namely voltage regulator circuit described in peripheral circuit produces.Alternatively, the voltage ZVDD2 of described first running voltage end is 2.5V, and the voltage of described tertiary voltage end and the voltage ZVDD2_PLUS of described 4th voltage end are 3.6V.
The operation principle of described level shift circuit is as follows: 1) when the input signal of described input IN1 is low level signal, described first drop-down metal-oxide-semiconductor 103 ends, described input signal becomes high level signal after the first phase inverter 105, described second drop-down metal-oxide-semiconductor 104 turns on, and now the output signal of output terminals A is low level.Then, owing to the output signal of described output terminals A is low level, therefore described first pull-up metal-oxide-semiconductor 101 turns on, and now the output signal of described outfan B is high level ZVDD2, so described second pull-up metal-oxide-semiconductor 102 ends, and the output signal keeping described output terminals A is low level.
Compared with existing level shift circuit, owing to the source electrode of described first drop-down metal-oxide-semiconductor 103 is connected to the outfan of described first phase inverter 105, it is connected with the grid of described second drop-down metal-oxide-semiconductor 104, therefore when the input signal of described input IN1 is low level, the source electrode of described first drop-down metal-oxide-semiconductor 103 is high level voltage, so the Vgs (gate source voltage) of the first drop-down metal-oxide-semiconductor 103 is negative voltage, so can reduce the leakage current flowing through described first drop-down metal-oxide-semiconductor 103.
On the other hand, being connected to the 4th voltage end owing to pulling up described second on the substrate of metal-oxide-semiconductor 102, the voltage ZVDD2_PLUS of described 4th voltage end is more than the voltage ZVDD2 of described first running voltage end.Therefore, when described second pull-up metal-oxide-semiconductor 102 ends, owing to the voltage ZVDD2_PLUS of described 4th voltage end is more than the voltage ZVDD2 of described first working end, the leakage current flowing through described second pull-up metal-oxide-semiconductor 102 so can be reduced.
2) when the input signal of described input IN1 is high level voltage, described first drop-down metal-oxide-semiconductor 103 turns on, described input signal IN1 becomes low level signal after the first phase inverter 105, and described second drop-down metal-oxide-semiconductor 104 ends, and now the output signal of described outfan B is low level.Then, owing to the output signal of described outfan B is low level, therefore described second pull-up metal-oxide-semiconductor 102 turns on, and now the output signal of described output terminals A is high level ZVDD2, so described first pull-up metal-oxide-semiconductor 101 ends, and the output signal keeping described outfan B is low level.
Compared with existing level shift circuit, owing to the source electrode of described second drop-down metal-oxide-semiconductor 104 is connected to the input of described first phase inverter 105, it is connected with the grid of described first drop-down metal-oxide-semiconductor 103, therefore when the grid voltage being added in described first drop-down metal-oxide-semiconductor 103 is high level signal, the source electrode of described second drop-down metal-oxide-semiconductor 104 is high level voltage, the Vgs (gate source voltage) of so described second drop-down metal-oxide-semiconductor 104 is negative voltage, so can reduce the leakage current flowing through described second drop-down metal-oxide-semiconductor 104.
On the other hand, connecting tertiary voltage end owing to pulling up described first on the substrate of metal-oxide-semiconductor 101, the voltage ZVDD2_PLUS of described tertiary voltage end is more than the voltage ZVDD2 of described first running voltage end.Therefore, when described first pull-up metal-oxide-semiconductor 101 ends, owing to the voltage ZVDD2_PLUS of described tertiary voltage end is more than the voltage ZVDD2 of described first working end, the leakage current flowing through described first pull-up metal-oxide-semiconductor 101 so can be reduced.
It should be noted that, in embodiment one, due in described level shift circuit, described first running voltage ZVDD2 is high voltage (2.5V), and therefore described first pull-up metal-oxide-semiconductor 101, described second pull-up metal-oxide-semiconductor 102, described first drop-down metal-oxide-semiconductor 103 and described second drop-down metal-oxide-semiconductor 104 are all high-voltage tubes.But use high-voltage tube to have certain defect, because the circuit area shared by high-voltage tube is relatively big and typically require higher running voltage to drive high-voltage tube to enter duty, hence for the problems referred to above, inventor additionally provides the technical scheme of improvement further, specific as follows:
The second embodiment schematic diagram with reference to the level shift circuit shown in Fig. 4.Described level shift circuit adds power supply circuits 106 on the basis of Fig. 3, and described power supply circuits 106 are for providing the second running voltage to described first drop-down metal-oxide-semiconductor 103 and described second drop-down metal-oxide-semiconductor 104.Specifically, the input IN2 of described power supply circuits 106 is connected with peripheral circuit 11, described power supply circuits 106 respectively with described first pull up metal-oxide-semiconductor 101 drain electrode, described second pull-up metal-oxide-semiconductor 102 drain electrode be connected, the drain electrode of described first drop-down metal-oxide-semiconductor 103, described second drop-down metal-oxide-semiconductor 104 drain electrode be connected, export the second running voltage to described first drop-down metal-oxide-semiconductor 103 and the second drop-down metal-oxide-semiconductor 104.
In the present embodiment, alternatively, described power supply circuits 106 include the first high-voltage tube 1061 and the second high-voltage tube 1062, and alternatively, wherein said first high-voltage tube 1061 and described second high-voltage tube 1062 are N-channel type metal-oxide-semiconductors.Wherein, the grid of described first high-voltage tube 1061 be the input of described power supply circuits 106, described first high-voltage tube 1061 and the grid of described second high-voltage tube 1062 be connected to the input of described power supply circuits 106, described first high-voltage tube 1061 and the drain electrode of described second high-voltage tube 1062 respectively with described first pull up metal-oxide-semiconductor 101 and described second pull-up metal-oxide-semiconductor 102 drain electrode be connected, described first high-voltage tube 1061 is connected with the drain electrode of described first drop-down metal-oxide-semiconductor 103 and the second drop-down metal-oxide-semiconductor 104 respectively with the source electrode of described second high-voltage tube 1062.
Specifically, the input IN2 of described power supply circuits 106 receives from the voltage VB (not shown) on peripheral circuit 11, and described voltage VB is available for described first high-voltage tube 1061 and the second high-voltage tube 1062 works.Wherein, described voltage VB is at least above the threshold voltage vt of described first high-voltage tube 1061 and the second high-voltage tube 1062, and alternatively, in the present embodiment, described voltage VB is VDD+Vt, and wherein said VDD is 1.8V.Then, providing the second running voltage to described first drop-down metal-oxide-semiconductor 103 and described second drop-down metal-oxide-semiconductor 104 respectively by described power supply circuits 106, in the present embodiment, described second running voltage is VDD.It should be noted that owing to described voltage VB is also flash memory system required voltage when standby, so extra area will not be increased.
With embodiment one the difference is that, the second running voltage owing to being provided for described first drop-down metal-oxide-semiconductor 103 and the second drop-down metal-oxide-semiconductor 104 by described power supply circuits 106 is low-voltage, and so described first drop-down metal-oxide-semiconductor 103 and the second drop-down metal-oxide-semiconductor 104 can use low-voltage tube.So improve and be advantageous in that, owing to the area of the area higher pressure pipe of low-voltage tube is less, therefore largely reduce the size of described level shift circuit.
Although the present invention is with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art are without departing from the spirit and scope of the present invention; may be by the method for the disclosure above and technology contents and technical solution of the present invention is made possible variation and amendment; therefore; every content without departing from technical solution of the present invention; according to any simple modification, equivalent variations and modification that above example is made by the technical spirit of the present invention, belong to the protection domain of technical solution of the present invention.
Claims (9)
1. a flash memory circuit, including peripheral circuit and row decoding circuit, wherein said row decoding circuit includes level shift circuit, word line selection circuit and drives latch cicuit, wherein said level shift circuit includes: the first pull-up metal-oxide-semiconductor and the second pull-up metal-oxide-semiconductor, first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor and the first phase inverter, it is characterized in that
The source electrode of described first drop-down metal-oxide-semiconductor and the source electrode of described second drop-down metal-oxide-semiconductor are connected to the first voltage end and the second voltage end, the voltage of wherein said first voltage end is more than the grid voltage of the first drop-down metal-oxide-semiconductor, and the voltage of described second voltage end is more than the grid voltage of the second drop-down metal-oxide-semiconductor；The substrate of described first pull-up metal-oxide-semiconductor and the substrate of described second pull-up metal-oxide-semiconductor are connected to tertiary voltage end and the 4th voltage end, the voltage of wherein said tertiary voltage end is more than the described first source voltage pulling up metal-oxide-semiconductor, and the voltage of described 4th voltage end is more than the described second source voltage pulling up metal-oxide-semiconductor；
The source electrode of the first pull-up metal-oxide-semiconductor described in described level shift circuit and the second pull-up metal-oxide-semiconductor is connected on the first running voltage end, the grid of described first pull-up metal-oxide-semiconductor is connected to the drain electrode of the second pull-up metal-oxide-semiconductor, and the grid of described second pull-up metal-oxide-semiconductor is connected to the drain electrode of the first pull-up metal-oxide-semiconductor；The grid of described first drop-down metal-oxide-semiconductor is connected to the input of described level shift circuit, the drain electrode of described first pull-up metal-oxide-semiconductor and the second pull-up metal-oxide-semiconductor is connected to form two outfans with the drain electrode of described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor respectively, the input of described first phase inverter is connected to the grid of described first drop-down metal-oxide-semiconductor, and outfan is connected to the grid of described second drop-down metal-oxide-semiconductor；
Described peripheral circuit at least includes voltage regulator circuit, described voltage regulator circuit and the first voltage end, tertiary voltage end and the 4th voltage end are connected, described voltage regulator circuit produces the voltage of the voltage of described first voltage end, the voltage of described tertiary voltage end and described 4th voltage end, the voltage of described first running voltage end is ZVDD2, the voltage of described tertiary voltage end and the voltage of the 4th voltage end are ZVDD2_PLUS, and the voltage of described tertiary voltage end and the voltage ZVDD2_PLUS of the 4th voltage end are more than the voltage ZVDD2 of described first running voltage end.
2. flash memory circuit according to claim 1, it is characterised in that the first voltage end described in described level shift circuit is the outfan of described first phase inverter.
3. flash memory circuit according to claim 1, it is characterised in that the second voltage end described in described level shift circuit is the input of described first phase inverter.
4. flash memory circuit according to claim 1, it is characterised in that the voltage of described tertiary voltage end and the voltage of described 4th voltage end are equal.
5. flash memory circuit according to claim 1, it is characterised in that described voltage regulator circuit includes multi stage charge pump, single stage charge pump, comparison controller and switching circuit；Described single stage charge pump is connected to the outfan of described multi stage charge pump；The outfan of described comparison controller and single stage charge pump is connected to the input of described switching circuit；The outfan of described switching circuit exports the voltage of the voltage of described first running voltage end, the voltage of described tertiary voltage end and described 4th voltage end respectively.
6. flash memory circuit according to claim 1, it is characterized in that, described level shift circuit also includes power supply circuits, the input of wherein said power supply circuits is connected with peripheral circuit, described power supply circuits respectively with described first pull up metal-oxide-semiconductor drain electrode, described second pull-up metal-oxide-semiconductor drain electrode be connected, the drain electrode of described first drop-down metal-oxide-semiconductor, described second drop-down metal-oxide-semiconductor drain electrode be connected, export the second running voltage to described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor.
7. flash memory circuit according to claim 6, it is characterized in that, described power supply circuits include the first high-voltage tube and the second high-voltage tube, the grid of wherein said first high-voltage tube and the second high-voltage tube is connected to the drain electrode of the input of described power supply circuits, described first high-voltage tube and the second high-voltage tube and is connected with the drain electrode of described first pull-up metal-oxide-semiconductor and the second pull-up metal-oxide-semiconductor respectively, and the source electrode of described first high-voltage tube and the second high-voltage tube is connected with the drain electrode of described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor respectively；Described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor are low-voltage tubes.
8. flash memory circuit according to claim 7, it is characterised in that described first high-voltage tube and described second high-voltage tube are N-channel type metal-oxide-semiconductors.
9. flash memory circuit according to claim 1, it is characterised in that the first pull-up metal-oxide-semiconductor described in described level shift circuit and the second pull-up metal-oxide-semiconductor are P-channel type metal-oxide-semiconductors, and described first drop-down metal-oxide-semiconductor and the second drop-down metal-oxide-semiconductor are N-channel type metal-oxide-semiconductors.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110057568.3A CN102122949B (en) | 2011-03-10 | 2011-03-10 | A kind of flash memory circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110057568.3A CN102122949B (en) | 2011-03-10 | 2011-03-10 | A kind of flash memory circuit |
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| CN102122949A CN102122949A (en) | 2011-07-13 |
| CN102122949B true CN102122949B (en) | 2016-07-13 |
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| CN103106921B (en) * | 2012-12-26 | 2017-03-08 | 上海华虹宏力半导体制造有限公司 | Level displacement shifter for row decoding circuit |
| CN113258910B (en) * | 2021-06-25 | 2021-10-19 | 中科院微电子研究所南京智能技术研究院 | Computing device based on pulse width modulation |
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| CN102122949A (en) | 2011-07-13 |
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