CN102122269B - Flash memory writing overtime control method and memory device thereof - Google Patents

Abstract

The invention relates to a write timeout control method for a flash memory, wherein the flash memory comprises a plurality of spare blocks and data blocks, the data blocks are provided with a plurality of mother blocks, and the method comprises the following steps: receiving a write command and an initial logical block address; determining an update mode according to a target mother block linked by the initial logical block address; judging whether the first mother block executes pre-clearing operation or not; if yes, executing post-clearing operation of the first mother block in a first time period; resetting the first mother block as a spare block; executing a write data programming program on the target mother block; judging whether the number of the mother blocks exceeds a first critical value; and when the first critical value is exceeded, executing pre-clearing operation on the second mother block in a second time period; the first and second parent blocks are marked as blocks to be cleared. The invention also relates to a memory device. The invention can solve the problem of write-in timeout of the flash memory, thereby improving the overall access efficiency of the memory device.

Description

Flash memory writing overtime control method and memory device thereof

technical field

The present invention relates to the relevant technical field of flash memory (flash memory), and more specifically, relates to a write timeout (write timeout) control method suitable for flash memory and a memory device thereof.

Background technique

Flash memory is a non-volatile memory that can maintain its stored data without relying on electricity. Due to its advantages of small size, high memory density, low power consumption and low cost, it is widely used in mobile phones, digital cameras, In various consumer electronic products such as personal digital assistants (PDAs).

Flash memory generally includes multiple blocks, and each block has a plurality of pages for storing data. Further, the flash memory performs data programming (program) in units of pages, and performs data erasure (erase) in units of blocks. In other words, when the flash memory erases data on a block, the data stored in all pages of the block will be erased together.

In addition, each page of flash memory is only allowed to be programmed once. When the data stored in some pages of a block needs to be updated, the updated data cannot be directly programmed into the pages because the pages already store old data. That is to say, if these pages are to be updated, the block must be erased first, and then the updating data can be written or programmed. This additional erasing and reprogramming operation not only causes delay in execution time, but also creates additional workload, resulting in a decline in overall access performance.

Furthermore, in order to match the trend of increasing memory capacity of flash memory, the number of pages in each block can be increased, for example: from 128 pages to 256 pages, or the memory capacity of each page can be increased, for example: from 4K bytes (bytes) It is increased to 8K bytes to make the flash memory have a larger memory capacity. However, this also means that updating data will consume more time for erasing and reprogramming, which may even exceed the programming time allowed by the flash memory specification, for example: 250 milliseconds (ms). Generally speaking, a block of 128 pages takes 200 milliseconds to complete the erase operation. Therefore, it takes 400 milliseconds to complete the block erase operation of 256 pages, plus the reprogramming time for updating data, there will be write overtime, resulting in a serious drop in overall access performance.

Therefore, there is a need for a write timeout control method suitable for flash memory, which can avoid write timeout when programming data or updating data, thereby improving the overall access performance of flash memory.

Contents of the invention

The technical problem to be solved by the present invention is to provide a writing time-out control method for flash memory and a memory device thereof, aiming at the above-mentioned defects of the prior art.

One of the technical solutions adopted by the present invention to solve the technical problems is: construct a write timeout control method of a flash memory, the flash memory includes a plurality of data blocks and a plurality of spare blocks, further, the data blocks include Multiple parent blocks. The method includes: receiving a write command from a host and a corresponding initial logical block address; determining an update mode according to a target parent block linked by the initial logical block address; judging a first Whether the parent block has performed a pre-clear operation, wherein the first parent block is marked as a block to be cleared; when the first parent block has performed the pre-clear operation, in a first time period, performing a post-clear operation of the first parent block; resetting the first parent block as a spare block; according to the update mode, on the target parent block linked by the initial logical block address , executing a write data programming program corresponding to the write command; judging whether the number of the mother blocks exceeds a first critical value; and when the number of the mother blocks exceeds the first critical value, at For a second time period, perform the pre-clear operation on a second parent block, wherein the second parent block is marked as the block to be cleared.

The writing overtime control method for flash memory described in the present invention, wherein, after receiving the initial logical block address, further includes:

A series of data units representing the write data are sequentially received.

The writing overtime control method for flash memory according to the present invention, wherein, after receiving the series of data units, further includes:

A stop transmission command sent by the host is received to indicate that the write data corresponding to the write command has been transmitted.

In the write timeout control method for flash memory according to the present invention, the first time period is used to indicate a period of time after a first data unit is received and before a second data unit is received.

In the write timeout control method for flash memory according to the present invention, the second time period is used to represent a period of time after receiving the predetermined command and before receiving the next command from the host.

The writing overtime control method for flash memory described in the present invention further includes:

performing the pre-erase operation on the first parent block during the first time period when the first parent block has not yet performed the pre-erase operation; and

performing the post clear operation of the first parent block during a third time period,

Wherein, the third time period is after the first time period and before the second time period, and is used to represent an interval time for receiving two consecutive data units.

In the write timeout control method for flash memory described in the present invention, wherein the data blocks further include a plurality of update blocks, and each update block has one or more update blocks for updating a corresponding parent block Update the page.

In the writing overtime control method for flash memory of the present invention, wherein, the steps of the pre-clear operation and the post-clear operation include:

Obtain the update mode of the block to be cleared;

When the update mode of the block to be cleared is a sub-block mode, searching for a last updated page from an update block corresponding to the block to be cleared;

According to the last updated page, from the block to be cleared, move the data of the last updated page to the updated block; and

Erase the block to be cleared.

In the writing overtime control method for flash memory of the present invention, wherein, the steps of the pre-clear operation and the post-clear operation include:

Obtain the update mode of the block to be cleared;

When the update mode of the block to be cleared is a file allocation table block mode, obtain a predetermined spare block;

Reading a lookup table from an update block corresponding to the block to be cleared, the lookup table records the corresponding update positions of the one or more update pages and the block to be cleared;

According to the lookup table, the data stored in the block to be cleared and the data stored in the one or more update pages are integrated to obtain integrated write data;

programming the consolidated write data into the intended spare block; and

Erase the block to be cleared and the update block.

The writing overtime control method for flash memory described in the present invention further includes:

When the number of the parent blocks does not exceed the first critical value, determine whether the update mode of the target parent block is a file configuration table block mode;

When the update mode of the target parent block is the file allocation table block mode, obtain a data length of the written data;

According to the initial logical block address and the data length, it is used to calculate an update block corresponding to the target parent block, and an end logical block address after executing the write data programming procedure;

Obtaining an available page quantity of the update block according to the end logical block address and the size of the update block;

judging whether the number of available pages is less than a second critical value;

When the number of available pages is less than the second critical value, marking the target parent block as the block to be cleared; and

During the second time period, the pre-erase operation of the target parent block is performed.

The second technical solution adopted by the present invention to solve the technical problem is to construct a memory device, which is coupled to a host and includes a flash memory and a controller. The flash memory includes a flash memory, including a plurality of data blocks and a plurality of spare blocks, wherein the data blocks include a plurality of parent blocks. The controller is coupled to the flash memory for receiving a write command from the host and a corresponding initial logical block address, determining an update mode according to a target parent block linked to the initial logical block address, judging whether a first parent block marked as a block to be cleared has performed a pre-clear operation, and when the first parent block has performed the pre-clear operation, perform the first parent block in a first time period A post-clear operation of the block, resetting the first parent block as a spare block, performing the write corresponding to the target parent block linked by the starting logical block address according to the update mode A write data programming program of input command, judging whether the number of the parent blocks exceeds a first critical value, and when the number of the parent blocks exceeds the first critical value, in a second time period, The pre-erase operation is performed on a second parent block marked as the block to be cleared.

In the memory device of the present invention, after receiving the initial logical block address, the controller sequentially receives a series of data units representing the write data.

In the memory device of the present invention, after receiving the series of data units, the controller receives a stop transmission command issued by the host to indicate that the write data corresponding to the write command has been transmitted.

In the memory device of the present invention, the first time period is used to represent a period of time after a first data unit is received and before a second data unit is received.

In the memory device of the present invention, the second time period is used to indicate a period of time after receiving the predetermined command and before receiving a next command from the host.

In the memory device of the present invention, when the first parent block has not yet performed the pre-erase operation, the controller executes the pre-erase operation of the first parent block in the first time period, and in a performing the post-clearing operation of the first parent block in a third time period,

Wherein, the third time period is after the first time period and before the second time period, and is used to represent an interval time for receiving two consecutive data units.

In the memory device of the present invention, the data blocks further include a plurality of update blocks, and each update block has one or more update pages for updating a corresponding parent block.

In the memory device of the present invention, wherein the controller obtains the update mode of the block to be cleared, and when the update mode of the block to be cleared is a sub-block mode, from the block corresponding to the block to be cleared Find a last update page in the update block, move the data after the last update page from the block to be cleared to the update block according to the last update page, and erase the block to be cleared, using to perform the pre-clear operation and the post-clear operation.

In the memory device of the present invention, wherein the controller obtains the update mode of the block to be cleared, and obtains a predetermined spare block when the update mode of the block to be cleared is a file allocation table block mode 1. Read a lookup table from an update block corresponding to the block to be cleared, the lookup table records the corresponding update positions of the one or more update pages and the block to be cleared, and according to the lookup table, The data stored in the block to be erased and the data stored in the one or more update pages are integrated to obtain integrated write data, program the integrated write data into the predetermined spare block, and erase The block to be cleared and the update block are used to perform the pre-clear operation and the post-clear operation.

In the memory device of the present invention, when the number of the parent blocks does not exceed the first critical value, the controller determines whether the update mode of the target parent block is a file allocation table block mode, When the update mode of the target parent block is the file configuration table block mode, obtain a data length of the written data, and use it to calculate the target parent block according to the initial logical block address and the data length An update block corresponding to the block obtains an available page of the update block according to the end logical block address and the size of the update block after executing the write-in data programming program. number, judging whether the number of available pages is less than a second critical value, when the number of available pages is less than the second critical value, marking the target parent block as the block to be cleared, and in the second time period, Execute the pre-clear operation of the target parent block.

Implementing the write overtime control method for flash memory and its memory device of the present invention has the following beneficial effects: in the process of the controller receiving write data from the host, or from the host receiving the stop transmission command to receiving the next command In the previous waiting period, the integration operation of the paired block group can be divided into a pre-clear operation and a post-clear operation in sequence. Therefore, during the execution of each command, the controller can integrate one or more pairs of block groups at the same time, so as to save the time spent on the integration of paired block groups, and solve the problem of writing timeout, thereby improving The overall access performance of the memory device.

Description of drawings

The present invention will be further described below in conjunction with accompanying drawing and embodiment, in the accompanying drawing:

Fig. 1 is a memory device block diagram of the embodiment of the present invention;

FIG. 2 is a schematic diagram of a target parent block and an update block according to an embodiment of the present invention;

3 is a flowchart of a write timeout control method for flash memory according to an embodiment of the present invention;

4 is a timing diagram of a write command, a corresponding starting logical block address, and a data unit according to an embodiment of the present invention;

5 is a schematic diagram of a target parent block and an update block in the child block mode according to another embodiment of the present invention;

FIG. 6 is a schematic diagram of a target parent block and an update block in the block mode of the file allocation table according to another embodiment of the present invention.

[Description of main component symbols]

10～memory device; 12～host;

102～controller; 104～flash memory;

106～data area; 108～reserve area;

D0～DI～data block; S0～SJ～spare block;

202, 502, 602～target parent block; and

204, 504, 604～update blocks.

Detailed ways

Preferred embodiments of the present invention are described below. The following descriptions are used to understand the present invention more easily, but are not intended to limit the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

FIG. 1 is a block diagram of a memory device 10 according to an embodiment of the present invention.

As shown in FIG. 1 , the memory device 10 is coupled to a host 12 and includes a controller 102 and a flash memory 104 . In one embodiment, the flash memory 104 is a NAND flash memory, and the memory device 10 includes various memory cards related to the flash memory, such as a secure digital (SD) card. In FIG. 1 , the flash memory 104 includes a plurality of blocks, and each block includes a plurality of pages.

Further, the flash memory 104 can be divided into a data pool 106 and a spare pool 108 , each of which includes a plurality of data blocks and a plurality of spare blocks. For example, in the data area 106, blocks D ₀ -D _I are data blocks that store data, and in the spare area 108, blocks S ₀ -S _J are data blocks that have not stored data or have been erased. spare block. I and J may be the same or different values.

As mentioned above, since data is only allowed to be written to pages that have not stored data (that is, unprogrammed or erased), when a data block, such as: multiple pages of block D ₀ have not been stored data, the controller 102 can program data to the pages of the data block.

However, when the host 12 intends to update the data in the page of the data block, the controller 102 cannot program the data to the page of the stored data. In this case, according to an embodiment of the present invention, the controller 102 can utilize the spare blocks S ₀ ˜S _J of the spare area 108 for data update.

FIG. 2 is a schematic diagram of a target parent block 202 and an update block 204 according to an embodiment of the present invention.

Refer to Figures 1 and 2. Specifically, assume that the host 12 requests the controller 102 to update a data block with a write data #DATA, for example, a plurality of pages to be updated in the block D ₀ . Since data is already stored in the pages to be updated in the data block, the controller 102 cannot directly program the write data #DATA into the pages to be updated in the data block. In this case, the controller 102 can set the data block as the target mother block 202 . Second, a spare block, such as block S ₀ , is selected from the spare area 108 as the update block 204 of the update target parent block 202 . Afterwards, the write data #DATA is programmed into the update page of the update block 204 .

In the above embodiment, since the update block 204 has a plurality of update pages for updating the corresponding target parent block 202, the target parent block 202 and the update block 204 can be called a paired block group.

In addition, without affecting the normal operation of the memory device 10, the controller 102 can configure a predetermined number of paired block groups according to the requirement of access performance, so as to use multiple target parent blocks and corresponding update blocks to Perform data update operations. In one embodiment, when a predetermined condition is met, for example, when the update block 204 is full of data for updating the target parent block 202, or the pairing blocks allowed by the memory device 10 have been reached When the number of groups is large, the controller 102 needs to further integrate the target parent block 202 and the update block 204 .

In one embodiment, the controller 102 marks the target parent block 202 as a block to be cleared, so as to integrate the data stored in the target parent block 202 into the update block 204 . Afterwards, the target parent block 202 is erased, and the erased target parent block 202 is reconfigured as a spare block for subsequent use.

In another embodiment, the controller 102 marks the target parent block 202 as a block to be cleared. Next, the controller 102 selects a spare block from the spare area 108 , such as the block S ₁ , and integrates the target parent block 202 and the update block 204 into the block S ₁ . Afterwards, the target parent block 202 and the update block 204 are erased, and the erased target parent block 202 and the update block 204 are reset as spare blocks for subsequent use. More specifically, in order to avoid writing timeout due to the memory capacity of the block, the integration process of the above-mentioned target parent block 202 and update block 204 can be divided into at least two times. The process of data update and integration will be described in detail with reference to the embodiments in FIGS. 3-6 as follows.

FIG. 3 is a flowchart of a write timeout control method 30 for flash memory according to an embodiment of the present invention.

Referring to FIGS. 1 to 3 , assume that the host 12 requests the controller 102 to update a data block, such as block D ₀ . The controller 102 receives a write command and a corresponding starting logical block address (LBA) from the host 12 (step S302 ). Afterwards, the controller 102 links the initial logical block address to the data block to be updated, namely the block D ₀ . Therefore, the controller 102 sets the block D ₀ as the target parent block 202 to be updated, and selects a spare block (for example: block S ₀ ) from the spare area 108 as the corresponding target parent block 202 Update block 204 .

Next, the controller 102 obtains write data #DATA from the host 12 to update the pages to be updated in the target parent block 202 . Specifically, each page can be further divided into 4 storage segments (sectors). Therefore, in one embodiment, the segment can be stored as a unit, but not limited thereto, and the write data #DATA is divided into a series of data units. In other words, after receiving the initial logical block address, the controller 102 sequentially receives a series of data units representing the writing data #DATA, such as the data units U ₀ -U _K shown in FIG. 4 .

FIG. 4 is a timing diagram of a write command CMD _N , a corresponding initial logical block address LBA _N , and data units U ₀ -U _K according to an embodiment of the present invention.

As shown in FIG. 4 , after receiving the write command CMD _N and the corresponding initial logical block address LBA _N , the controller 102 immediately receives a series of data units U ₀ -U _K . Further, after receiving the data units U ₀ ˜U _K , the controller 102 receives a stop transmission command STOP_TRAN sent by the host 12 to indicate that the data units U ₀ ˜U _K have been transmitted. In one embodiment, the interval between two consecutive data units, such as the data units U ₀ and U ₁ , that is, the programming busy recording time, is 250 milliseconds (ms) or less. In addition, there is also a period of 250 milliseconds between receiving the stop transmission command STOP_TRAN and before receiving the next command CMD _N+1 . Therefore, the controller 102 can utilize the aforementioned time period to divide the integration operation of the paired block groups into at least two operations. For example, the controller 102 can utilize the aforementioned time period to divide the integration operation of the paired block groups into a pre-clear operation and a post-clear operation to complete.

In addition, the controller 102 determines an update mode according to the target parent block 202 to which the initial logical block address LBA _N is linked (step S304 ). In one embodiment, when the host 12 intends to update consecutive pages of the target mother block 202, the update mode of the target mother block 202 is a mother-child mode. In another embodiment, when the host 12 intends to update fragmented pages of the target parent block 202, the update mode of the target parent block 202 is a file allocation table (file allocation table, FAT) block mode (mother-FAT mode) .

FIG. 5 is a schematic diagram of a target parent block 502 and an update block 504 in the child block mode according to another embodiment of the present invention.

As shown in FIG. 5 , the target parent block 502 includes N pages 502_0˜502_N−1, respectively storing data P502_0˜P502_N−1. Correspondingly, the update block 504 also includes N update pages 504_0˜504_N−1. Since the update block 504 is a spare block, the N update pages 504_0˜504_N−1 do not store any data.

In this embodiment, assume that the host 12 requests the controller 102 to update the data P502_0 - P502_4 stored in the consecutive pages 502_0 - 502_4 of the target parent block 502 . Therefore, the controller 102 determines that the updating mode of the target parent block 502 is the sub-block mode. That is to say, the controller 102 sets the update block 504 as a child block for performing data update operations in the child block mode.

According to the embodiment of FIG. 5, when the controller 102 stores the update data corresponding to the pages 502_0-502_4 of the target parent block 502 into the update pages 504_0-504_4 of the update block 504, the controller 102 further integrates the target parent block 502 and update block 504. First, the controller 102 marks the target parent block 502 as a block to be cleared. Next, the controller 102 searches for a last updated page, namely the updated page 504_4 , from the updated block 504 corresponding to the target parent block 502 . Therefore, in the pre-clear operation, according to the last updated page 504_4, the controller 102 first moves the data P502_5-P502_N-1 stored in the unupdated pages 502_5-402_N-1 in the target parent block 502 to the update block 504. Pages 504_5~504_N-1. Further, in the post erase operation, the controller 102 erases the target parent block 502 .

FIG. 6 is a schematic diagram of a target parent block 602 and an update block 604 in the file allocation table block mode according to another embodiment of the present invention.

As shown in FIG. 6 , the target parent block 602 includes N pages 602_0˜602_N−1, respectively storing data P602_0˜P602_N−1. Correspondingly, the update block 604 also includes N update pages 604_0˜604_N−1. Since the update block 604 is a spare block, the N update pages 604_0˜604_N−1 do not store any data.

In this embodiment, assume that the host 12 requests the controller 102 to update the data P602_2 , P602_3 , P602_4 , P602_7 and P602_8 stored in the discontinuous pages 602_2 , 602_3 , 602_4 , 602_7 and 602_8 of the target parent block 602 . Therefore, the controller 102 determines that the update mode of the target parent block 602 is the file allocation table block mode. In other words, the controller 102 sets the update block 604 as a FAT block for performing data update operations in the FAT block mode.

For example, when the host 12 requests to update the pages 602_2, 602_3, 602_4, 602_7, and 602_8 of the target parent block 602 with the update data P2, P3, P4, P7, and P8, the controller 102 first updates the pages 602_2, 602_3, 602_4, 602_7, and 602_8 of the target parent block 602. P4 is stored in update pages 604_0 , 604_1 and 604_2 of update block 604 . Afterwards, the controller 102 utilizes the lookup table TABLE_1 to record the update page of the update block 604 and the corresponding page to be updated of the target parent block 602 . That is to say, the lookup table TABLE_1 records the corresponding relationship between the pages 602_2 , 602_3 and 602_4 of the target parent block 602 and the update pages 604_0 , 604_1 and 604_2 of the update block 604 . Next, the controller 102 programs the lookup table TABLE_1 into the update page 604_3 of the update block 604 . Further, the controller 102 stores the update data P7 and P8 in the update pages 604_4 and 604_5 of the update block 604 . Similarly, the controller 102 uses the lookup table TABLE_2 again to record the corresponding relationship between the pages 602_7 and 602_8 of the target parent block 602 and the update pages 604_4 and 604_5 of the update block 604 . Then, the controller 102 programs the lookup table TABLE_2 into the update page 604_6 of the update block 604 to end the data update operation in the file configuration table block mode.

According to the embodiment of FIG. 6 , when the update block 604 is full of data for updating the target parent block 602 , the controller 102 needs to integrate the target parent block 602 and the update block 604 . The controller 102 first marks the target parent block 602 as a block to be cleared. Next, the controller 102 selects a spare block from the spare area 108 , such as the block S ₁ . Therefore, in the pre-erase operation, according to the lookup tables TABLE_1 and TABLE_2, the controller 102 integrates the data stored in the target parent block 602 and the update data stored in the update page of the update block 604 to obtain an integrated write input data. Specifically, the controller 102 updates the data stored in the non-updated pages of the target parent block 602, such as 602_0, 602_1, 602_5, 602_6, 602_9-602_N-1, and updates the updated pages 602_0-602_2 and 602_4 of the block 604 The data stored in ~602_5 are integrated to generate the integrated write data. Afterwards, the controller 102 programs the integrated write data into the block S ₁ . Further, in the post erase operation, the controller 102 erases the target parent block 602 and update block 604 .

Further, referring to FIG. 3 and FIG. 4 , after the update mode of the target parent block is determined, the controller 102 obtains the write data #DATA for updating from the host 12 , that is, the data units U ₀ ˜U _K . Specifically, after the controller 102 receives the first data unit U ₀ (step S306 in FIG. 3 ), it immediately determines whether there is an unfinished integration operation during the execution of the previous command CMD _N-1 . That is, the controller 102 determines whether a specific parent block marked as a block to be cleared has been pre-cleared (step S308 in FIG. 3 ).

When the pre-clear operation has been performed on the specific parent block, the controller 102 executes the post-clear operation on the specific parent block within 250 milliseconds of the first time period T1 (step S310 of FIG. 3 ).

If the specific parent block has not performed the pre-clear operation during the execution of the previous command CMD _N−1 , the controller 102 first performs the pre-clear operation on the specific parent block within the first time period T1. Afterwards, the controller 102 may perform the post-clear operation of the specific parent block in another time period, for example, the period between the data units _U1 and _U2 (step S312 in FIG. 3 ).

Further, after the specific parent block is erased, the controller 102 resets the specific parent block as a spare block (step S314 in FIG. 3 ).

Next, the controller 102 continues to receive the remaining data units to perform the sub-block mode data update operation in FIG. 5 or the file allocation table block mode data update operation in FIG. 6 . Specifically, the controller 102 executes a programming procedure of writing data #DATA corresponding to the writing command CMD _N and the starting logical block address LBA _N (step S316 in FIG. 3 ). That is, according to the update mode of the target parent block 502 or 602 , the controller 102 sequentially programs all the data units U ₀ ˜U _K into corresponding update pages of the update block 504 or 604 .

After receiving the stop transmission command STOP_TRAN, the controller 102 immediately determines whether the number of paired block groups exceeds a predetermined number (step S318 in FIG. 3 ).

When the number of paired block groups configured by the controller 102 reaches a predetermined number, the normal operation of the memory device 10 may be affected. Therefore, the controller 102 first selects a set of paired block sets from the current paired block sets to perform the integration operation. Afterwards, after receiving the stop transmission command STOP_TRAN, within a period of time before receiving the next command CMD _N+1 , that is, within 250 milliseconds of the second time period T2 as shown in FIG. The selected paired block group performs a partial integration operation, that is, the aforementioned pre-clearing operation (step S320 in FIG. 3 ). Further, the controller 102 may, during the execution of the next command CMD _N+1 , for example: within 250 milliseconds after receiving the first data unit of the next command CMD _N+1 , the selected paired block The group performs the remaining integration operations, the aforementioned post-purge operations. In this way, the problem of flash memory write timeout can be effectively solved.

When the number of paired block groups has not exceeded the predetermined number, the controller 102 further determines whether the update mode of the target parent block is the file configuration table block mode (step S322 in FIG. 3 ).

Referring to Figures 3, 4 and 6, when the update mode of the target parent block 602 is determined to be the file configuration table block mode, the controller 102 obtains the write data #DATA for updating the target parent block 602, that is, the data unit U ₀ ~ U _K , the data length. Afterwards, according to the initial logical block address LBA _N and the data length, the controller 102 calculates the end logical block address of the corresponding update block 604 of the target parent block 602 after executing the write data #DATA programming program, as shown in the figure 6 shows the updated page 604_6. Next, the controller 102 obtains the number of available pages of the update block 604 according to the end logical block address and the size of the update block 604 . Specifically, according to the embodiment of FIG. 6 , the update block 604 has N update pages, and the end logical block address is the update page 604_6 . In this case, the number of available pages of the update block 604 is (N-7). Then, the controller 102 determines whether the number of available pages (N-7) of the update block 604 is smaller than a predetermined threshold (step S324 of FIG. 3 ).

When the number of available pages (N-7) of the update block 604 is greater than the preset threshold, it means that the number of available pages (N-7) of the update block 604 is sufficient to maintain subsequent data update operations. In other words, the target parent block 602 and update block 604 do not need to be integrated yet.

On the contrary, when the number of available pages (N−7) of the update block 604 is less than the preset threshold, it means that the controller 102 needs to further integrate the target parent block 602 and the update block 604 . Specifically, the controller 102 first marks the target parent block 602 as a block to be cleared. Afterwards, during the second time period T2 shown in FIG. 4 , the controller 102 performs a pre-clear operation on the target parent block 602 and the update block 604 (step S326 in FIG. 3 ). Furthermore, during the execution of the next command CMD _N+1 , for example: within 250 milliseconds after receiving the first data unit of the next command CMD _N+1 , the controller 102 updates the target parent block 602 and Block 604 performs a post flush operation. The pre-clear operation and post-clear operation of the target parent block 602 and the update block 604 have been described in detail in FIG. 6 and its related embodiments, and will not be repeated here.

To sum up, according to the embodiment of the present invention, in order to avoid the write timeout of the memory device, a paired block group with the target parent block and the corresponding update block can be configured to perform the data update operation. Further, the integration operation of the paired block groups can be divided into at least two times. That is to say, during the process of the controller receiving write data from the host, or during the waiting period from the host receiving the stop transmission command to receiving the next command, the integration operation of the paired block group can be sequentially divided into pre-clear operation and post-clear operation. Therefore, during the execution of each command, the controller can integrate one or more pairs of block groups at the same time, so as to save the time spent on the integration of paired block groups, solve the problem of write timeout, and thus improve The overall access performance of the memory device.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention should be defined by the scope of the appended patent application.

Claims (14)

1. A writing overtime control method for flash memory, the flash memory includes a plurality of data blocks and a plurality of spare blocks, wherein the data blocks include a plurality of parent blocks and a plurality of update blocks, Each update block has one or more update pages for updating a corresponding parent block, characterized in that the method includes: receiving a write command from a host and a corresponding initial logical block address; A target parent block linked to the initial logical block address is used to determine an update mode; judging whether a first parent block has performed a pre-clear operation, wherein the first parent block is marked as a block to be cleared; when the first parent block has performed the pre-clear operation, performing a post-clear operation of the first parent block during a first time period; resetting the first parent block as a spare block; According to the update mode, on the target parent block linked by the initial logical block address, execute a write data programming procedure corresponding to the write command; judging whether the number of the parent blocks exceeds a first threshold; and When the number of the parent blocks exceeds the first critical value, performing the pre-clearing operation of a second parent block in a second time period, wherein the second parent block is marked as the pending clearing operation block; Wherein, the steps of the pre-clearing operation and the post-clearing operation include: Obtain the update mode of the block to be cleared; When the update mode of the block to be cleared is a sub-block mode, a last update page is searched from an update block corresponding to the block to be cleared; according to the last update page, from the area to be cleared In the block, the data after the last updated page is moved to the update block; and the block to be cleared is erased; Wherein, when the host intends to update consecutive pages of the target parent block, the update mode of the target parent block is the child block mode; When the update mode of the block to be cleared is a file configuration table block mode, obtain a predetermined spare block; read a lookup table from an update block corresponding to the block to be cleared, and the lookup The table records the corresponding update positions of the one or more update pages and the block to be cleared; according to the lookup table, the data stored in the block to be cleared and the data stored in the one or more update pages are integrated, for obtaining an integrated write data; programming the integrated write data into the predetermined spare block; and erasing the block to be erased and the update block; Wherein, when the host intends to update scattered pages of the target parent block, the update mode of the target parent block is the block mode of the file configuration table. 2. The write overtime control method for flash memory according to claim 1, wherein, after receiving the initial logical block address, further comprising: A series of data units representing the write data are sequentially received. 3. The write timeout control method for flash memory according to claim 2, wherein, after receiving the series of data units, further comprising: A stop transmission command sent by the host is received to indicate that the write data corresponding to the write command has been transmitted. 4. The write timeout control method for flash memory according to claim 3, wherein, the first time period is used to indicate that after a first data unit is received, the period from receiving a second data unit some time ago. 5. The write timeout control method for flash memory according to claim 4, wherein, the second time period is used to represent a period before receiving the next command from the host after the predetermined command is received. time. 6. The write overtime control method for flash memory according to claim 5, further comprising: performing the pre-erase operation on the first parent block during the first time period when the first parent block has not yet performed the pre-erase operation; and performing the post clear operation of the first parent block during a third time period, Wherein, the third time period is after the first time period and before the second time period, and is used to represent an interval time for receiving two consecutive data units. 7. The writing overtime control method for flash memory according to claim 1, further comprising: When the number of the parent blocks does not exceed the first critical value, determine whether the update mode of the target parent block is a file configuration table block mode; When the update mode of the target parent block is the file allocation table block mode, obtain a data length of the written data; According to the initial logical block address and the data length, it is used to calculate an update block corresponding to the target parent block, and an end logical block address after executing the write data programming procedure; Obtaining an available page quantity of the update block according to the end logical block address and the size of the update block; judging whether the number of available pages is less than a second critical value; When the number of available pages is less than the second critical value, marking the target parent block as the block to be cleared; and During the second time period, the pre-erase operation of the target parent block is performed. 8. A memory device coupled to a host, comprising: A flash memory, including a plurality of data blocks and a plurality of spare blocks, wherein the data blocks include a plurality of parent blocks and a plurality of update blocks, and each update block has one or more One update page corresponding to the parent block; and A controller, coupled to the flash memory, used to receive a write command from the host and a corresponding initial logical block address, and determine an update mode according to a target parent block linked to the initial logical block address , judging whether a first parent block marked as a block to be cleared has performed a pre-clear operation, and when the first parent block has performed the pre-clear operation, perform the first A post-clearing operation of the parent block, resetting the first parent block as a spare block, performing corresponding A write data programming program of write command, judging whether the number of the parent blocks exceeds a first critical value, and when the number of the parent blocks exceeds the first critical value, in a second time period , performing the pre-clearing operation on a second parent block marked as the block to be cleared; Wherein, the pre-clearing operation and the post-clearing operation include obtaining the update mode of the block to be cleared, and when the update mode of the block to be cleared is a sub-block mode, from the block corresponding to the block to be cleared Find a last updated page in the update block, move the data after the last updated page from the block to be cleared to the update block according to the last updated page, and erase the block to be cleared; wherein, When the host intends to update consecutive pages of the target parent block, the update mode of the target parent block is the child block mode; When the update mode of the block to be cleared is a file configuration table block mode, a predetermined spare block is obtained, and a lookup table is read from an update block corresponding to the block to be cleared, and the lookup table is read. The table records the corresponding update positions of the one or more update pages and the block to be cleared, and integrates the data stored in the block to be cleared with the data stored in the one or more update pages according to the look-up table, Used to obtain an integrated write data, program the integrated write data into the predetermined spare block, and erase the block to be cleared and the update block; wherein, when the host wants to update the scattered pages of the target parent block , the update mode of the target parent block is the file configuration table block mode. 9 . The memory device according to claim 8 , wherein after receiving the initial logical block address, the controller sequentially receives a series of data units representing the write data. 10. The memory device according to claim 9, wherein, after receiving the series of data units, the controller receives a stop transmission command issued by the host to indicate that the data corresponding to the write command Write data has been transferred. 11. The memory device according to claim 10, wherein the first time period is used to represent a period of time after a first data unit is received and before a second data unit is received. 12 . The memory device according to claim 11 , wherein the second time period is used to indicate a period of time after receiving the predetermined command and before receiving a next command from the host. 13 . 13. The memory device according to claim 12, wherein, when the first parent block has not performed the pre-erase operation, the controller executes the first parent block in the first time period the pre-erase operation, and performing the post-erase operation of the first parent block in a third time period, Wherein, the third time period is after the first time period and before the second time period, and is used to represent an interval time for receiving two consecutive data units. 14. The memory device according to claim 8, wherein when the number of the parent blocks does not exceed the first critical value, the controller determines whether the update mode of the target parent block is A file allocation table block mode, when the update mode of the target parent block is the file allocation table block mode, obtain a data length of the written data, according to the initial logical block address and the data length , used to calculate an update block corresponding to the target parent block, an end logical block address after executing the write data programming program, according to the end logical block address and the size of the update block, obtain A number of available pages of the update block, judging whether the number of available pages is less than a second critical value, when the number of available pages is less than the second critical value, marking the target parent block as the block to be cleared, and performing the pre-erase operation of the target parent block during the second time period.

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