CN102087509B

CN102087509B - Integrated circuit and control method thereof

Info

Publication number: CN102087509B
Application number: CN 201010528592
Authority: CN
Inventors: 陈庆宇
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2010-11-01
Filing date: 2010-11-01
Publication date: 2013-02-20
Anticipated expiration: 2030-11-01
Also published as: CN102087509A

Abstract

An integrated circuit and a control method thereof are provided, the integrated circuit is used for controlling a plurality of slave components, wherein each slave component is provided with a clock input pin, a data input pin and an address selection pin. The integrated circuit includes a processing unit and a controller. The processing unit provides information to be transmitted to at least one of the plurality of slave devices. The controller is coupled to the processing unit, and is configured to provide the information to the clock input pin and the data input pin of each slave device according to an inter-integrated circuit bus protocol, and provide a selection signal to the address selection pin of the at least one slave device according to the information. The invention can quickly control a plurality of slave elements.

Description

Integrated circuit and control method thereof

Technical field

The present invention is particularly to control the integrated circuit of a plurality of subordinate elements relevant for integrated circuit.

Background technology

Internal integrated circuit (Inter Integrated Circuit, I2C) bus is the string type transfer bus standard that Philip (PHILIPS) company develops, be used as a kind of communication agreement between the integrated circuit, for example microcontroller and peripherals thereof.Generally speaking, master control (Master) element that is positioned on the internal integrate circuit bus can send first the exclusive subordinate element addresses of receiving end, wants to link up with which subordinate (Slave) element in order to represent master element.Then, master element just can be sent data, only has this subordinate element meeting receive data this moment.Therefore, master element can be inquired about and control each subordinate element.Yet when the quantity of subordinate element increased, master element need to be controlled each subordinate element with the more time.

Summary of the invention

The invention provides a kind of integrated circuit, in order to control a plurality of subordinate elements, wherein each above-mentioned subordinate element has clock pulse input pin, data input pin and an address selection pin.Said integrated circuit comprises: a processing unit, and in order to being provided, tendency to develop delivers to an information of at least one the subordinate element in above-mentioned a plurality of subordinate element; And, one controller, be coupled to above-mentioned processing unit, in order to according to internal integrated circuit (Inter Integrated Circuit, I2C) bus protocol and above-mentioned clock pulse input pin and the above-mentioned data input pin of above-mentioned information to each above-mentioned subordinate element is provided, and provide one to select signal to the address above mentioned of above-mentioned at least one subordinate element to select pin according to above-mentioned information.

Moreover, the invention provides a kind of control method, be applicable to control an integrated circuit of a plurality of subordinate elements, wherein each above-mentioned subordinate element has clock pulse input pin, data input pin and an address selection pin.Above-mentioned control method comprises: receive the information that one or more subordinate element in above-mentioned a plurality of subordinate element is delivered in tendency to develop; According to internal integrated circuit (I2C) bus protocol, provide above-mentioned clock pulse input pin and the above-mentioned data input pin of above-mentioned information to each above-mentioned subordinate element; And, according to above-mentioned information, provide one to select signal to the address above mentioned of above-mentioned one or more subordinate element to select pin.

The present invention can control a plurality of subordinate elements rapidly.

Description of drawings

Fig. 1 shows the application schematic diagram that different sound channels are provided with integrated circuit;

Fig. 2 shows the application schematic diagram that different sound channels are provided with another integrated circuit;

Fig. 3 shows the application schematic diagram according to the described integrated circuit of one embodiment of the invention, and it can provide different sound channels by controlling a plurality of subordinate elements;

Fig. 4 shows according to the described control method that is applicable to an integrated circuit of one embodiment of the invention.

Embodiment

For above and other purpose of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below.

Embodiment:

Fig. 1 shows the application schematic diagram that different sound channels are provided with integrated circuit 100.In Fig. 1, integrated circuit 100 can be used as master control (Master) element and controls four stereo digital/analog converters (Digital to Analog Converter, DAC) 110A-110D, be that digital/analog converter 110A-110D is subordinate (slave) element, in order to the effect of 7.1 sound channels is provided.For example, digital/analog converter 110A-110D can provide respectively preposition sound channel, surround channel, central authorities/low frequency special efficacy sound channel and side ring around different sound channels such as sound channels.In Fig. 1, integrated circuit 100 can be linked up by internal integrated circuit (I2C) bus protocol and peripheral subordinate element.For instance, for integrated circuit 100, each digital/analog converter 110A-110D has subordinate element addresses separately.Therefore, by serial clock pulse line (Serial Clock Line, SCL) signal and serial data address (Serial Data Address, SDA) signal, integrated circuit 100 can transmit the subordinate element addresses corresponding to the digital/analog converter of wish control, so that addressing is to this digital/analog converter, and then this digital/analog converter controlled.When supposing that digital/analog converter 110A-110D is the integrated circuit of same model, integrated circuit 100 still can't while control figure/analog converter 110A-110D.For example, the whole digital/analog converter 110A-110D of simultaneously activation of integrated circuit 100.In other words, although integrated circuit 100 can come activation digital/analog converter 110A-110D with identical steering order, yet because digital/analog converter 110A-110D has respectively different subordinate element addresses, therefore integrated circuit 100 still needs sequentially to transmit identical activation instruction to digital/analog converter 110A-110D by different subordinate element addresses, in order to respectively digital/analog converter 110A-110D is controlled.

Fig. 2 shows the application schematic diagram that different sound channels are provided with another integrated circuit 200.In Fig. 2, digital/analog converter 210A-210D is particular element, and it can have different subordinate element addresses and can select pin SADDR to set by element addresses.For instance, if when the element addresses of digital/analog converter selected pin SADDR to be set to logic level " 0 ", the subordinate element addresses that then can set this digital/analog converter was ADD0.Otherwise, if when the element addresses of digital/analog converter selected pin SADDR to be set to logic level " 1 ", the subordinate element addresses that then can set this digital/analog converter was ADD1.As shown in Fig. 2, integrated circuit 200 comprises processing unit 220, demoder 230 and two internal integrated circuit interface units 240 and 250.Internal integrated circuit interface unit 240 can provide serial data signal SDA0 and serial clock signal SCL0 data input pin SDIN and the clock pulse input pin SCLK to digital/analog converter 210A and 210B, and internal integrated circuit interface unit 250 can provide serial data signal SDA1 and serial clock signal SCL1 to input pin SCLK to data input pin SDIN and the clock pulse of digital/analog converter 210C and 210D.In addition, because the element addresses that the element addresses of digital/analog converter 210A and 210C selects pin SADDR to be set to logic level " 0 " and digital/analog converter 210B and 210D selects pin SADDR to be set to logic level " 1 ", so the subordinate element addresses of digital/analog converter 210A and 210C is ADD0, and the subordinate element addresses of digital/analog converter 210B and 210D is ADD1.Therefore, in integrated circuit 200, by demoder 230, internal integrated circuit interface unit 240 and internal integrated circuit interface unit 250, processing unit 220 can be simultaneously controlled digital/analog converter 210A and two of 210C or digital/analog converter 210B and two of 210D.In addition, processing unit 220 also can be controlled each digital/analog converter 210A-210D respectively.It should be noted that in Fig. 2, integrated circuit 200 still can't be controlled whole digital/analog converter 210A-210D simultaneously.

Fig. 3 shows the application schematic diagram according to the described integrated circuit 300 of one embodiment of the invention, and it can provide different sound channels by controlling a plurality of subordinate elements.As described previously, integrated circuit 300 can be used as master element and controls four stereo digital/analog converter 310A-310D, reaches the effect of 7.1 sound channels around different sound channels such as sound channels so that preposition sound channel, surround channel, central authorities/low frequency special efficacy sound channel and side ring to be provided respectively.In Fig. 3, integrated circuit 300 comprises processing unit 320 and controller 360, and its middle controller 360 comprises demoder 330, interface unit 340 and selected cell 350.Interface unit 340 can provide the data input pin SDIN of serial data signal SDA to each digital/analog converter 310A-310D by pin PIN1, and can provide the clock pulse input pin SCLK of serial clock signal SCL to each digital/analog converter 310A-310D by pin PIN2.In addition, selected cell can provide respectively by pin PIN3_0, PIN3_1, PIN3_2 and PIN3_3 and select signal SEL0, SEL1, SEL2 and SEL3 to the element addresses selection pin SADDR of digital/

analog converter

310A, 310B, 310C and 310D.

In Fig. 3, processing unit 320 can provide at least one information INFO that tendency to develop delivers to digital/analog converter 310A-310D to demoder 330.Then, demoder 330 can be decoded to the information INFO from processing unit 320, and to obtain the identification code ID of information INFO, wherein identification code ID indication information INFO wants to be transferred into the whichever of digital/analog converter 310A-310D.Then, interface unit 340 receives information INFO by demoder 330, and produces serial data signal SDA and serial clock signal SCL corresponding to information INFO according to the internal integrate circuit bus agreement.Then, interface unit 340 can provide respectively serial data signal SDA and serial clock signal SCL to digital/analog converter 310A-310D via pin PIN1 and pin PIN2.Side by side, selected cell 350 can provide suitable selection signal to digital/analog converter 310A-310D according to the identification code ID that receives.For instance, when digital/analog converter 310A wants to be transferred in identification code ID indication information INFO system, then selected cell 350 can provide the selection signal SEL0 with first logic level to digital/analog converter 310A, and provide selection signal SEL1, SEL2 with second logic level and SEL3 to digital/analog converter 310B-310D, so that notice digital/analog converter 310A receives serial clock signal SCL and serial data signal SDA.It should be noted that and select the logic level of signal SEL0-SEL3 to determine according to the specification of digital/analog converter 310A-310D.For another example, when digital/

analog converter

310A and 310B want to be transferred in identification code ID indication information INFO system, then selected cell 350 can provide the selection signal SEL0 with first logic level and select signal SEL1 to digital/

analog converter

310A and 310B, and provide selection signal SEL2 with second logic level and SEL3 to digital/analog converter 310C-310D, so that notice digital/

analog converter

310A and 310B receive serial clock signal SCL and serial data signal SDA.In one embodiment, the selection signal of the selection signal of the first logic level and the second logic level can be the logical complement signal.

In addition, for integrated circuit 300, digital/analog converter 310A-310D has identical subordinate element addresses.Therefore, according to embodiments of the invention, integrated circuit 300 can be controlled digital/analog converter 310A-310D simultaneously.For example, when integrated circuit 300 was wanted simultaneously digital/analog converter 310A-310D to be controlled, processing unit 320 can provide information INFO that wish is sent to digital/analog converter 310A-310D simultaneously to demoder 330.Then, demoder 330 can be decoded to the information INFO from processing unit 320, and obtains the identification code ID of information INFO, and wherein identification code ID can want to be transferred into whole digital/analog converter 310A-310D by indication information INFO.Then, interface unit 340 can produce corresponding to serial data signal SDA and the serial clock signal SCL of information INFO and is sent to digital/analog converter 310A-310D according to the internal integrate circuit bus agreement.Side by side, selected cell 350 can provide respectively selection signal SEL0, SEL1, SEL2 and SEL3 with first logic level to digital/analog converter 310A-310D, in order to notify whole digital/analog converter 310A-310D to receive serial clock signal SCL and serial data signal SDA, and carry out down-stream.In one embodiment, above-mentioned information INFO leaves in the working storage with the form of comparison list (lookup table), uses for demoder.In one embodiment, when above-mentioned a plurality of digital/analog converter 310A-310D had identical subordinate element addresses, then above-mentioned serial data signal comprised the address of above-mentioned digital/analog converter 310A-310D.

Moreover integrated circuit 300 also can provide the signal that meets Serial Peripheral Interface (Serial Peripheral Interface, SPI) bus protocol to peripheral subordinate element by controller 360.For instance, when integrated circuit 300 and subordinate element are linked up with the serial peripheral equipment interface bus agreement, interface unit 340 can receive information INFO from processing unit 320 by demoder 330, and produces serial data signal SDA and serial clock signal SCL corresponding to information INFO according to the serial peripheral equipment interface bus agreement.Side by side, selected cell 350 can provide suitable selection signal to digital/analog converter 310A-310D according to the identification code ID that receives, wherein select signal SEL0-SEL3 to can be considered chip selection (Chip Select, the CS) signal of digital/analog converter 310A-310D.Therefore, if digital/analog converter 310A-310D supports Serial Peripheral Interface (serial peripheralinterface simultaneously, SPI) during bus protocol, then integrated circuit 300 can be controlled digital/analog converter 310A-310D according to the selected bus protocol of digital/analog converter 310A-310D, and need not further change relevant design and application on the printed circuit board (PCB).

Fig. 4 demonstration is according to the described control method that is applicable to an integrated circuit of one embodiment of the invention, and wherein integrated circuit can be controlled a plurality of subordinate elements, and each subordinate element has clock pulse input pin, data input pin and an address selection pin.At first, receive tendency to develop and deliver to one or more a information (step S402) in a plurality of subordinate elements.Then, according to the internal integrate circuit bus agreement, provide respectively corresponding to serial clock signal and serial data signal to clock pulse input pin and the data of each subordinate element of above-mentioned information and input pin (step S404).Then, the above-mentioned information that tendency to develop is sent is decoded, and obtain an identification code, wherein identification code is corresponding to a plurality of subordinate elements above-mentioned one or more (being that identification code indicates above-mentioned information to want to be transferred into the whichever of a plurality of subordinate elements) (step S406).Then, according to above-mentioned identification code, provide suitable selection signal to a plurality of subordinate elements above-mentioned one or more, in order to notify above-mentioned one or more of a plurality of subordinate elements to receive serial clock signal and serial data signal, and carry out subsequent operation (step S408).It should be noted that integrated circuit, each subordinate element has identical subordinate element addresses.

In one embodiment, if integrated circuit and peripheral subordinate element are one-way transmission, or the subordinate element is after the information that receives from integrated circuit, do not need further to send back induction signal (Acknowledge, ACK) or not back-signalling (Negative-Acknowledge, NAK) give integrated circuit, then can control the subordinate element more quickly according to the described integrated circuit of the embodiment of the invention.

The above only is preferred embodiment of the present invention; so it is not to limit scope of the present invention; any personnel that are familiar with the technology; without departing from the spirit and scope of the present invention; can do on this basis further improvement and variation, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.

Symbol in the accompanying drawing is simply described as follows:

100,200,300: integrated circuit

110A-110D, 210A-210D, 310A-310D: digital/analog converter

220,320: processing unit

230,330: demoder

240,250: the internal integrated circuit interface unit

340: interface unit

350: selected cell

360: controller

ID: identification code

INFO: information

PIN1, PIN2, PIN3_0, PIN3_1, PIN3_2, PIN3_3: pin

SCL, SCL0, SCL1: serial clock signal

SDA, SDA0, SDA1: serial data signal

SEL0-SEL3: select signal.

Claims

1. A master control element integrated circuit, characterized in that it is used to control a plurality of slave elements, each of the above-mentioned slave elements has a clock input pin, a data input pin and an address selection pin, and the above-mentioned master control element Integrated circuits include:

a processing unit for providing a message to be transmitted to at least one of the plurality of slave elements; and

a controller, coupled to the processing unit, for providing the above information to the above clock input pin and the above data input pin of each of the above slave elements according to the inter-integrated circuit bus protocol, and providing a selection according to the above information a signal to the address select pin of the at least one slave element;

Wherein, the plurality of slave elements correspond to the same slave element address, so that the integrated circuit of the master control element can control the plurality of slave elements at the same time;

Wherein, the address selection pin of each of the slave components is directly connected to a corresponding pin of the integrated circuit of the master control component.

2. The main control element integrated circuit according to claim 1, wherein the above-mentioned controller comprises:

a decoder, coupled to the processing unit, for receiving the information and decoding an identification code of the information, wherein the identification code corresponds to the at least one slave element; and

An interface unit, coupled to the above-mentioned decoder, is used to receive the above-mentioned information, and provide a serial clock signal and a serial data signal corresponding to the above-mentioned information to each of the above-mentioned slave components according to the inter-integrated circuit bus protocol The clock input pin and the data input pin.

3. The main control element integrated circuit according to claim 2, wherein the above-mentioned controller further comprises:

A selection unit, coupled to the decoder, for providing the selection signal to the at least one slave element according to the identification code of the information, so as to notify the at least one slave element to receive the serial clock signal and the serial clock signal data signal.

4. The master integrated circuit according to claim 2, wherein the serial data signal includes the address of the slave device.

5. The main control element integrated circuit according to claim 2, further comprising:

a first pin coupled to the data input pin of each of the slave elements for providing the serial data signal;

a second pin coupled to the clock input pin of each of the slave elements for providing the serial clock signal; and

A plurality of third pins are respectively coupled to the address selection pins of the corresponding slave elements.

6. The master control element integrated circuit according to claim 1, wherein said plurality of slave elements support the internal integrated circuit bus protocol and the serial peripheral device interface bus protocol, and the above-mentioned controller is also based on the serial peripheral device interface The bus protocol provides the above information to the clock input pin and the data input pin of each of the slave elements, and provides a chip select signal to the address selection pin of the at least one slave element according to the information.

7. The main control device integrated circuit according to claim 2, wherein the information is stored in a register in the form of a look-up table for use by the decoder.

8. A method for controlling a master control element, characterized in that it is suitable for a master control element integrated circuit for controlling a plurality of slave elements, wherein each of the above-mentioned slave elements has a clock input pin, a data input pin and An address selection pin, wherein the above-mentioned address selection pin of each of the above-mentioned slave components is directly connected to a corresponding pin of the integrated circuit of the above-mentioned main control component, and the control method of the above-mentioned main control component includes:

providing a message to be transmitted to one or more of the plurality of slave devices to the clock input pin and the data input pin of each of the slave devices according to an inter-integrated circuit bus protocol; and

providing a selection signal to the address selection pins of the one or more slave elements according to the information;

Wherein, the plurality of slave elements correspond to the same address of a slave element, so that the integrated circuit of the master control element can control the plurality of slave elements at the same time.

9. The method according to claim 8, wherein the step of providing said information to each of said slave components further comprises:

According to the inter-integrated circuit bus protocol, provide a serial clock signal and a serial data signal corresponding to the information to the clock input pin and the data input pin of each of the slave elements respectively.

10. The method according to claim 9, wherein the step of providing the selection signal to the one or more slave components further comprises:

decoding an identification code of the information, wherein the identification code corresponds to the one or more slave components; and

According to the identification code, provide the selection signal to the one or more slave components, so as to notify the one or more slave components to receive the serial clock signal and the serial data signal.

11. The method for controlling the master device according to claim 9, wherein the serial data signal includes the address of the slave device.

12. The control method of the main control element according to claim 9, wherein the integrated circuit of the above-mentioned main control element comprises:

13. The control method of the master control component according to claim 8, wherein the plurality of slave components support the IIC bus protocol and the SPI bus protocol.

14. The master control component control method according to claim 13, further comprising:

providing the above information to the above clock input pin and the above data input pin of each of the above slave elements according to the serial peripheral device interface bus protocol; and

Provide a chip select signal to the address selection pins of the one or more slave elements according to the above information.

15. The control method of the main control device according to claim 10, wherein the information is stored in a register in the form of a look-up table for subsequent decoding.