CN102063874B - Grid driving circuit - Google Patents
Grid driving circuit Download PDFInfo
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- CN102063874B CN102063874B CN 200910221750 CN200910221750A CN102063874B CN 102063874 B CN102063874 B CN 102063874B CN 200910221750 CN200910221750 CN 200910221750 CN 200910221750 A CN200910221750 A CN 200910221750A CN 102063874 B CN102063874 B CN 102063874B
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Abstract
The invention relates to a grid driving circuit for a liquid crystal display, which comprises a plurality of driving units, wherein each driving unit receives an input signal and generates an output signal to the next stage of driving unit. By utilizing the special coupling relation of the grid driving circuit and different clock signals in two or three pulse periods, the storage and displacement of the input signals are realized.
Description
Technical field
The present invention relates to a kind of gate driver circuit, and relate in particular to a kind of gate driver circuit that is used for LCD.
Background technology
The conventional ADS driving structure of LCD is as shown in Figure 1, and LCD 1 comprises array base palte 3, and it is mainly by m bar data line (D
1-D
m) and n bar data line (G
1-G
n) pel array divided constitutes, wherein m bar data line is driven by a plurality of data driving chip 5, and n bar gate line is driven by a plurality of grid drive chip 7, in addition, time schedule controller (not shown) control grid drive chip 7 and data driving chip 5.
For the demand of resolution, the number of pixels of pel array must improve; Therefore, the gate line of driving pixels and the number of data line, and the also necessary raising of the number of the data driving chip of responsible outputting drive voltage and grid drive chip cause the manufacturing cost of LCD too high.
As shown in Figure 2, in order to reduce cost, prior art with grid drive chip 7 by integrated gate drive circuitry (integrated gate driver; IGD) 9 replace, and this integrated gate drive circuitry 9 is made on the array base palte 3 with pel array simultaneously, can save the cost of parts of grid drive chip 7 by this; And; Integrated grid driver 9 is divided into the driver of a plurality of levels (stage); Through all different circuit topological design; The output signal that makes the input signal of n level equal the output signal of n-1 level, n level equals the input signal of n+1 level, produces with the notion of similar shift register (shift register) and outputs signal to each gate line with driving pixels.
The gate drivers of prior art or shift register (shift register) design example has U.S. Pat 5,222, and 082, U.S. Pat 5,410,583.Its shortcoming is some on-off element in its circuit, and its control end (for example grid) couples high voltage source or clock signal, and the long-term critical voltage that will cause switch down that uses squints, and makes that the stability of circuit and fiduciary level are not good.In addition, its power consumption of the circuit structure of prior art is bigger, and necessity of improvement is arranged in fact.
Therefore, needing badly provides a kind of new gate driver circuit, to improve above-mentioned defective.
Summary of the invention
The object of the present invention is to provide a kind of new gate driver circuit and driving method thereof, have good stable property and reliability, and power consumption is compared prior art and can significantly be reduced.
According to above-mentioned purpose, the embodiment of the invention provides a kind of gate driver circuit, comprises the driver element of a plurality of serial connections, and each driver element receives a plurality of clock signals to drive load, and each driver element comprises:
Signal input part, receiving inputted signal;
Signal output part, output signal output;
First switch has first end and couples that this signal input part, second end couple first node X, control end receives first clock signal;
Second switch has that first end and control end couple this signal input part, second end couples this first node;
The 3rd switch has first termination and receives that second clock signal, second end couple this signal output part, control end couples this first node;
The 4th switch, the 4th switch have first end and couple this first node, second end and couple low-voltage source, control end and receive from the output signal of two-stage drive unit down;
Wherein the signal output part of each driver element is coupled to the signal input part of next stage driver element,
Wherein each driver element still comprises mu balanced circuit and is coupled between said first node and the said output terminal, and wherein said mu balanced circuit comprises:
The 5th switch has first end and couples that Section Point, second end couple said low-voltage source, control end couples said signal input part;
The 6th switch has first end and couples that said Section Point, second end couple said low-voltage source, control end couples the 3rd clock signal; Minion is closed, and has first end and couples that said first node, second end couple said low-voltage source, control end couples said Section Point; And
Octavo is closed, and said octavo is closed has that second end, second end that first end couples said the 3rd switch couples said low-voltage source, control end couples said Section Point;
The 9th switch has that first end and control end receive said first clock signal, second end couples said Section Point.
Embodiments of the invention also provide another kind of gate driver circuit, comprise the driver element of a plurality of serial connections, and each driver element receives a plurality of clock signals to drive load, and each driver element comprises:
Signal input part, receiving inputted signal;
Signal output part, output signal output;
First switch has first end and couples that said signal input part, second end couple first node, control end receives first clock signal;
Second switch has that first end and control end couple said signal input part, second end couples said first node;
The 3rd switch has first termination and receives that second clock signal, second end couple said signal output part, control end couples said first node; And
The 4th switch, said the 4th switch have first end and couple said first node, second end and couple low-voltage source, control end and receive from the output signal of two-stage drive unit down;
Wherein the signal output part of each driver element is coupled to the signal input part of next stage driver element,
Wherein each driver element still comprises mu balanced circuit and is coupled between said first node and the said output terminal, and wherein said mu balanced circuit comprises:
The 5th switch; Have that control end, second end that first end couples second end that octavo closes and the 6th switch couples low-voltage source, control end couples said signal input part; Said the 6th switch still has first termination to be received first end, second end that said first clock signal and said octavo close and couples Section Point, and first end and control end that said octavo is closed receive said first clock signal simultaneously; And
Minion is closed, and has first end and couples that said first node, second end couple said low-voltage source, control end couples said Section Point.
Description of drawings
Fig. 1 is the block diagram of available liquid crystal display;
Fig. 2 is the block diagram of another available liquid crystal display, and wherein the gate driver circuit of LCD is a gate driver circuit;
Fig. 3 A is the block diagram of the gate driver circuit of the embodiment of the invention, and it uses 4 clock signals;
Fig. 3 B is the clock figure of the clock signal that clock generator produced among Fig. 3 A;
Fig. 4 is the circuit diagram of second driver element of first embodiment of the invention;
Fig. 5 A is the clock figure of each signal in second driver element of Fig. 4;
Fig. 5 B is the running synoptic diagram according to each switch of Fig. 5 A;
Fig. 6 is the circuit diagram of second driver element of another embodiment of the present invention;
Fig. 7 A is the clock figure of each signal in second driver element of Fig. 6;
Fig. 7 B is the running synoptic diagram according to each switch of Fig. 7 A;
Fig. 8 is the circuit diagram of second driver element of another embodiment of the present invention;
Fig. 9 A is the clock figure of each signal in second driver element of Fig. 8;
Fig. 9 B is the running sketch map based on each switch of Fig. 9 A; And
Fig. 9 C is the clock figure of each signal in Fig. 8 second driver element of another embodiment.
Embodiment
Each embodiment of this case below will be detailed, and in conjunction with the accompanying drawings.Except these were described in detail, the present invention can also be implemented among other the embodiment widely, the substituting easily of any said embodiment, revise, equivalence changes and is included in the scope of this case, and be as the criterion with appended claim.In the description of instructions, in order to make the reader the present invention there is more complete understanding, many specific detail are provided; Yet the present invention possibly still can implement at clipped or all under the prerequisite of these specific detail.In addition, well-known step or element are not described in the details, with the restriction of avoiding causing the present invention unnecessary.
Fig. 3 A shows the block diagram of the gate driver circuit 10 of the embodiment of the invention.Gate driver circuit 10 comprises the driver element 11 of a plurality of serial connections; First driver element shown in for example scheming, second driver element, the 3rd driver element, 4 wheel driven moving cell or the like; Wherein each driver element 11 receiving inputted signal, feedback signal and three clock signals; Wherein clock signal C K1 to CK4 is provided by 20 of clock generators, and this clock generator 20 can comprise or is not contained in this gate driver circuit 10.
Each driver element comprises signal input part 12, feedback signal input end 14 and signal output part 13 with receiving inputted signal and feedback signal and output signal output.The signal output part 13 of each driver element 11 is coupled to the signal input part 12 of next driver element and the feedback signal input end 14 of preceding two-stage drive unit; For example; If second driver element is a n level driver element; Its signal output part 13 is coupled to the signal input part 12 of the 3rd driver element (n+1 level driver element), and the signal output part 13 of 4 wheel driven moving single (n+2 level driver element) unit is coupled to the feedback signal terminal 14 of second driver element; Therefore; The input signal of each grade driver element 11 is output signals of previous stage driver element, and the output signal of n+2 level driver element is the feedback signal of n level driver element, still; Because first driver element 11 is the first order driver element of this serial connection driver element; Its signal input part 12 receives the input signal that gate driver circuit 10 is received, for example, and start signal.
Fig. 3 B shows the sequential chart of the clock signal that the gate driver circuit 10 of the embodiment of the invention is received; Clock generator 20 common properties are given birth to four clock signal C K1, CK2, CK3, CK4; And this clock signal has phase differential in regular turn to each other, for example differs a pulse width W, but not as limit.In other words; Shown in Fig. 3 B; Clock signal C K2 falls behind the phase differential (or CK2 and CK1 differ the phase differential of a pulse width) of a pulse width of CK1; And clock signal C K3 also falls behind the phase differential (or clock signal C K2 and CK3 differ the phase differential of a pulse width) of a pulse width of CK2, and the rest may be inferred, and it is poor that promptly two adjacent clock signals differ a same phase to each other.In addition, in said each embodiment in the present invention back, when not specifying, each clock signal will have identical pulse width.
Fig. 4 shows the circuit diagram of a driver element of the gate driver circuit 10 of the embodiment of the invention, and present embodiment is that example is done explanation with second driver element, and supposes that it is a n level driver element.
Wherein second driver element 11 is to be used for a row pixel, the particularly thyristor of this row pixel in the driving pixels array, among the figure with resistance R
LOADAnd capacitor C
LOADEquivalence one row pixel.In addition, explanation hereinafter abbreviates " nodes X " as with " first node X ", " Section Point Z " abbreviates " node Z " as for ease; For example, " the first switch M
1" abbreviate " switch M as
1", " the first clock signal C K1 " abbreviate " clock signal C K1 " as, other is also by that analogy.
As previously mentioned, second driver element, 11 receiving inputted signals (Input) and output signal output (Output) are with the row pixel in the driving pixels array and export the input signal of next stage driver element as the next stage driver element to.
Each switch has control end, first end, second end.Switch M
1First end couple signal input part 12 with receiving inputted signal (Input), second end couple nodes X, control end couples clock signal C K1.Switch M
2First end and control end couple signal input part 12 and couple nodes X with receiving inputted signal (Input), second end.Switch M
3First end couple first end, the control end that clock signal C K2, second end couple signal output part 13 and switch M8 and couple nodes X.Switch M
4First end couple nodes X, second end couples low-voltage source V
SS(the tool electronegative potential, for example-10V), control end couples the feedback signal from N+2 level driver element, that is, the output signal of N+2 level driver element.
Fig. 5 A and 5B show the driving method of the gate driver circuit 10 of the embodiment of the invention; Wherein Fig. 5 A shows the driver element of gate driver circuit 10 according to Fig. 4; The sequential chart of the current potential of the input signal Input in second driver element 11, clock signal C K1-CK2, nodes X, feedback signal N+2, output signal Output for example, Fig. 5 B then is the switch M with respect to Fig. 5 A
1To switch M
4Mode of operation.In addition, for ease of explanation, this sentences resistance R
LOADAnd capacitor C
LOADThe load that equivalence second driver element 11 is coupled.Moreover in description, high levle for example can be 15 volts; Low level for example can be-10 volts, but it is not in order to limit the present invention.
At first during T1, the input signal Input that signal input part 12 received is that high levle and clock signal C K1 also are high levle, so switch M
1, M
2Conducting, this input signal Input is coupled to nodes X and also the current potential of this nodes X is charged to high levle.Feedback signal N+2 is that low level makes switch M
4Close, nodes X remains on high levle.By this, switch M
3Conducting, clock signal C K2 is coupled to output terminal 13.At this moment, because clock signal C K2 is a low level, the output signal Output of output terminal 13 output low levels.
During T2, input signal Input and clock signal C K1 are low level, so switch M
1, M
2Close.Feedback signal N+2 is a low level, switch M
4Close; Therefore, by switch M
3Stray capacitance, the current potential of nodes X still remains in high levle, makes switch M
3Still be in conducting state.At this moment, because clock signal C K2 is a high levle, so the output signal Output of output terminal 13 output high levles is to load capacitance C
LOADAnd resistance R
LOAD, it has phase delay with respect to input signal Input, the for example delay of the pulse width of a clock signal this output signal Output.
During T3, input signal Input and clock signal CK1 are low level, switch M
1, M
2Keep and close.Feedback signal N+2 is a low level, switch M
4Keep and close.Therefore, by the 3rd switch M
3Stray capacitance, the current potential of nodes X still maintains high levle, switch M
3Still be in conducting state.At this moment, because clock signal C K2 is a low level, output terminal 13 is through switch M
3The output signal Output of output low level.
During T4, input signal Input and clock signal CK1 are low level, switch M
1, M
2Keep and close.Feedback signal N+2 is a high levle, switch M
4Conducting makes the current potential of nodes X be discharged to low level, so switch M
3Close the output signal Output of output terminal 13 output low levels.
During T5, clock signal C K1 is a high levle, switch M
1Conducting.Input signal Input is a low level, switch M
2Close.Nodes X maintains electronegative potential with the output signal.
During T6, input signal Input, clock signal C K1, feedback signal N+2 are low level, switch M
1, M
2, M
4Close.The current potential of nodes X maintains low level, switch M
3Close, the high levle of clock signal C K2 can't be coupled to the output signal, and output signal Output maintains low level.
During T7 to T8, input signal Input, clock signal C K1, clock signal C K2, feedback signal N+2 are low level, switch M
1, M
2, M
4Close.The current potential of nodes X maintains low level, switch M
3Close, output signal Output maintains low level.
According to described gate driver circuit of the embodiment of the invention and driving method, be responsible for the switch M of output signal output
3, its opening time is elongated, and adds during the T1 by prior art between charge period during the T2, increases to during T1 adds T2 and add T3, can guarantee switch M
3The sufficient activity duration is arranged.In addition, because switch M
1After long period of operation, may produce the critical voltage offset problem, add switch M
2Design can improve this offset problem, with the voltage of guaranteeing high levle via switch M
2Be recharged to nodes X, and switch M
4Be designed for during the T4 time, the current potential of nodes X is via switch M
4Be discharged to low level.In addition, each driver element only uses two clock signals, and the clock signal work period (duty cycle) be merely 1/4, so can reduce power consumption, save the energy.
Fig. 6 shows the circuit diagram of a driver element of the gate driver circuit 10 of another embodiment of the present invention; Present embodiment is that example is done explanation with second driver element; And suppose that it is a n level driver element, with Fig. 4 embodiment different be in, each driver element 11 has increased by the 5th switch M
5, the 6th switch M
6, minion closes M
7, octavo closes M
8, the 9th switch M
9
Switch M
9First end and control end couple first end that clock signal C K1, second end couple node Z and switch M5.Switch M
5First end couple switch M
4Second end and node Z, second end couple low-voltage source V
SS, control end couples signal input part 12 with receiving inputted signal (Input).Switch M
6First end couple node Z, second end couples low-voltage source V
SS, control end couples clock signal C K3.Switch M
7First end couple nodes X, second end couples low-voltage source V
SS, control end couples node Z.Switch M
8First end couple switch M
3Second end, second end couple low-voltage source V
SS, control end couples node Z.
Fig. 7 A and 7B show the driving method of the gate driver circuit 10 of the embodiment of the invention; Wherein Fig. 7 A shows the driver element of gate driver circuit 10 according to Fig. 6; The sequential chart of the current potential of the current potential of the input signal Input in second driver element 11, clock signal C K1-CK3, nodes X, node Z, feedback signal N+2, output signal Output for example, Fig. 7 B then is the switch M with respect to Fig. 7 A
1To switch M
9Mode of operation.At first during T1, the input signal Input that signal input part 12 received is that high levle and clock signal C K1 also are high levle, so switch M
1, M
2, M
9, M
5Conducting, this input signal Input is coupled to nodes X and also the current potential of this nodes X is charged to high levle.And switch M
9, M
5Conducting makes the current potential of node Z be equal to low-voltage source Vss, so switch M
7, M
8All close, and because of feedback signal N+2 be that low level makes switch M
4Close, so nodes X remains on high levle.By this, switch M
3Conducting, clock signal C K2 is coupled to output terminal 13.At this moment, because clock signal C K2 is a low level, the output signal Output of output terminal 13 output low levels.
During T2, input signal Input and clock signal C K1 are low level, so switch M
1, M
2, M
9, M
5Close.Clock signal C K3, feedback signal N+2 are low level, so switch M
6, M
4Close, in addition switch M
7, M
8Keep and close; Therefore, by switch M
3Stray capacitance, the current potential of nodes X still remains in high levle, makes switch M
3Still be in conducting state.At this moment, because clock signal C K2 is a high levle, so the output signal Output of output terminal 13 output high levles is to load capacitance C
LOADAnd resistance R
LOAD, it has phase delay with respect to input signal Input, the for example delay of a pulse width this output signal Output.
During T3, input signal Input and clock signal CK1 are low level, switch M
1, M
2, M
9, M
5Keep and close.Clock signal C K3 is a high levle, makes node Z be coupled to electronegative potential switch M
7, M
8Keep and close.Feedback signal N+2 is a low level, switch M
4Keep and close.Therefore, by the 3rd switch M
3Stray capacitance, the current potential of nodes X still maintains high levle, switch M
3Still be in conducting state.At this moment, because clock signal C K2 is a low level, output terminal 13 is through switch M
3The output signal Output of output low level.
During T4, input signal Input and clock signal CK1, clock signal C K3 are low level, switch M
1, M
2, M
9, M
5, M
6, M
7, M
8Keep and close.Feedback signal N+2 is a high levle, switch M
4Conducting makes the current potential of nodes X be discharged to low level, so switch M
3Close, and because load capacitance C
LOADIn being discharged to low level during the T3 and during T4, not being recharged once again, so the output signal Output of output terminal 13 output low levels.
During T5, clock signal C K1 is a high levle, so switch M
1, M
9Conducting.Input signal Input, clock signal C K3 are low level, so switch M
2, M
5, M
6Close.The high levle of CK1 is via switch M by this
9Be coupled to node Z, make switch M
7, M
8Conducting is so the current potential of nodes X and output signal all is discharged to electronegative potential, makes switch M
3Close, the output signal maintains electronegative potential.
During T6, input signal Input, clock signal C K1, clock signal C K3, feedback signal N+2 are low level, switch M
1, M
2, M
4, M
5, M
6, M
9Close.The current potential of node Z is a high levle during T5, during T6 because switch M
7, M
8Stray capacitance, in other words because there is not a discharge path, therefore remain on high levle, make switch M
7, M
8Conducting, the current potential of nodes X maintains low level, so switch M
3Close, the high levle of clock signal C K2 can't be coupled to the output signal, and output signal Output maintains low level.
During T7, clock signal C K3 is a high levle, switch M
6Conducting makes the current potential of node Z be discharged to low level.Input signal Input, clock signal C K1, clock signal C K2, feedback signal N+2 are low level, switch M
1, M
2, M
4, M
5, M
7, M
8, M
9Close.The current potential of nodes X maintains low level, switch M
3Close, output signal Output maintains low level.
During T8, input signal Input, clock signal C K1, clock signal C K2, clock signal C K3, feedback signal N+2 are low level, switch M
1To M
9Close.The current potential of nodes X maintains low level, and output signal Output maintains low level.
The embodiment of Fig. 6 to Fig. 7 B has kept the identical advantage of Fig. 4 to Fig. 5 B embodiment, repeats no more.Both difference are that the former stability is better, and its characteristics that have comprise: the current potential of nodes X is the controlled switch M that is formed on
7, M
4, when both have the one of which conducting then the current potential of nodes X can be discharged to low level, M
4Be used for nodes X discharge, M during the T4
7Be used for the nodes X discharge during the T5; Node Z CS M
7, M
8, and switch M
9, M
5, M
6The current potential of Control Node Z; Switch M8 is used for guaranteeing to export signal during the T5 and is discharged to low level.Above-mentioned switch M
5To M
9Function be as mu balanced circuit, the stability when increasing circuit operation in other embodiments, can be omitted one of them or several switches or do the variation of equivalence.In addition; Used three clock signals at each driving circuit of present embodiment, than the embodiment of Fig. 4 to Fig. 5 B many a clock signal, but since the work period of each clock signal be merely 1/4; Frequency is lower than 1/2 of prior art, makes present embodiment equally have the effect of power saving.
Fig. 8 shows the circuit diagram of a driver element of another embodiment of the present invention gate driver circuit 10, is in, switch M with embodiment before different
6Couple the position difference, capacitor C 1 replaces original switch M
8Function to omit original switch M
8, in addition, the switch M of present embodiment
8' be equivalent to before the switch M of embodiment
9
Each element annexation is described below.Switch M
1First end couple signal input part 12 with receiving inputted signal (Input), second end couple nodes X, control end couples clock signal C K1.Switch M
2First end and control end couple signal input part 12 and couple nodes X with receiving inputted signal (Input), second end.Switch M
3First end couple first end, the control end that clock signal C K2, second end couple signal output part 13 and capacitor C 1 and couple nodes X.Switch M
8' first end and control end couple clock signal C K1, second end couples switch M
6Control end.Switch M
5First end couple switch M
4Second end and switch M
6Control end, second end couple low-voltage source V
SS(the tool electronegative potential, for example-10V), control end couples signal input part 12 with receiving inputted signal (Input).Switch M
6First end couple that clock signal C K1, the second end coupling couple node Z, control end couples switch M
4Second end and switch M
5First end.Switch M
7First end couple nodes X, second end couples low-voltage source V
SS, control end couples node Z.Switch M
4First end couple nodes X, second end couples low-voltage source V
SS, control end couples the feedback signal from N+2 level driver element, that is, the output signal of N+2 level driver element.In addition, this gate driver circuit 10 can comprise capacitor C 1 in addition and be coupled between this nodes X and the output terminal 13, uses and reduces this switch M
1And switch M
2Stray capacitance and the coupling effect between signal.
Fig. 9 A and 9B show the driving method of the gate driver circuit 10 of the embodiment of the invention; Wherein Fig. 9 A shows the driver element of gate driver circuit 10 according to Fig. 8; The signal timing diagram of the current potential of the current potential of the input signal Input in second driver element 11, clock signal C K1-CK2, nodes X, node Z, feedback signal N+2, output signal Output for example, Fig. 9 B then is the switch M with respect to Fig. 9 A
1To switch M
9Mode of operation.Notice that the work period of the first clock signal C K1 and second clock signal CK2 is different from the work period of Fig. 4 to Fig. 5 B embodiment in the present embodiment, the work period of present embodiment is 1/3 and preceding embodiment is 1/4.
During the T1 with T2 during operation, identical with Fig. 5 B embodiment, repeat no more.
During T3, input signal Input and clock signal CK1, CK2 are low level, switch M
1, M
2, M
8', M
5Close.M
6Keep close, node Z maintains electronegative potential, switch M
7Close.Feedback signal N+2 is a low level, switch M
4Keep and close.Therefore, by the 3rd switch M
3Stray capacitance, the current potential of nodes X still maintains high levle, switch M
3Still be in conducting state.At this moment, because clock signal C K2 is a low level, output terminal 13 is through switch M
3The output signal Output of output low level.
During T4, clock signal C K1 is a high levle, and input signal Input and clock signal C K2 are low level, switch M
1, M
8' conducting, switch M
2, M
5Close, and switch M
6Conducting makes that node Z is noble potential, switch M because the noble potential of clock signal C K1 is coupled to its control end
7The current potential of conducting, nodes X is discharged to electronegative potential.Feedback signal N+2 is a high levle, switch M
4Conducting makes the current potential of nodes X be discharged to low level, so switch M
3Close, and because load capacitance C
LOADIn being discharged to low level during the T3 and during T4, not being recharged once again, so the output signal Output of output terminal 13 output low levels.
During T5, input signal Input, clock signal C K1, feedback signal N+2 are low level, switch M
1, M
2, M
4, M
5, M
8' close, node Z is because switch M
7Stray capacitance maintain high levle and make switch M
6Conducting, and clock signal C K1 is low level, so the current potential of node Z is via switch M
6Be discharged to low level, make switch M
7Close.The current potential of nodes X maintains low level, switch M
3Close, the output signal maintains electronegative potential.
During T6, input signal Input, clock signal C K1, clock signal C K2, feedback signal N+2 are low level, switch M
1, M
2, M
4, M
5, M
8' close.Node Z maintains low level, makes switch M
6, M
7Close.The current potential of nodes X maintains low level, so switch M
3Close, output signal Output maintains low level.
During T7, clock signal C K1 is a high levle, and input signal Input and clock signal C K2 are low level, switch M
1, M
8' conducting, switch M
2, M
5Close, and switch M
6Because the noble potential of clock signal C K1 is via M
4Be coupled to its control end and conducting makes that node Z is noble potential, switch M
7The current potential of conducting, nodes X is discharged to electronegative potential.Feedback signal N+2 is a high levle, switch M
4Conducting makes the current potential of nodes X be discharged to low level, so switch M
3Close, output signal Output maintains low level.
During T8, input signal Input, clock signal C K1, feedback signal N+2 are low level, and clock signal C K2 is a high levle, switch M
1, M
2, M
4, M
5, M
8' close.Node Z is because switch M
7Stray capacitance maintain high levle and make switch M
6Conducting, and clock signal C K1 is low level, so the current potential of node Z is via switch M
6Be discharged to low level, make switch M
7Close.The current potential of nodes X maintains low level, so switch M
3Close, output signal Output maintains low level.
This gate driver circuit 10 can comprise in addition electric capacity be coupled to this first node X and this output terminal 13 between, use and reduce this first switch M
1And this second switch M
2Stray capacitance and the coupling effect between signal.
Above-mentioned M
5To M
8' mu balanced circuit that constituted, with embodiment before different be in: because switch M
8' the permanent problem that has the critical voltage skew, the switch M of using
6The noble potential that can guarantee clock signal C K1 is chargeable to node Z, also provides the path to supply node Z to be discharged to electronegative potential simultaneously.Yet, in other embodiment of the present invention, switch M
8' and M
6Connected mode can with switch M among Fig. 6
9With switch M
6Connected mode identical, and also need this moment shown in Fig. 6 embodiment, introduce extra clock signals CK3 to control M
6In addition, in the present embodiment, capacitor C 1 can reduce switch M
1, M
2With this switch M
3Stray capacitance and the coupling effect between signal.
Fig. 9 C shows the driving method of the gate driver circuit 10 of another embodiment of the present invention, and it shows the driver element of gate driver circuit 10 according to Fig. 8, for example each signal timing diagram in second driver element 11; The difference of itself and Fig. 9 A is; All input signals (like input signal, CK1, CK2, N+2... etc.), and comprise the start signal that receives from first driver element, widen length-adjustable pulse width T all in advance; Promptly after the adjustment; The pulse width of each signal will be (T+W), and have the overlapping period of T width between the two adjacent clock signals, and wantonly in addition two adjacent clock signals differ stationary phase to each other.What deserves to be mentioned is that above-mentioned each input signal is after adjusting length-adjustable pulse width T, it is (overlapping like CK1 and CK2 segment pulse that two adjacent clock signals are overlapped; And overlapping width is T), but not all overlapping, wherein; Preferably; Length-adjustable pulse width T less than or be not more than 1/2 of adjusted single pulse width (T+W), that is two adjacent in regular turn clock signals are like clock signal C K1 and CK2; The width T of lap less than or be not more than 1/2 of single pulse width (T+W), but not as limit.It is better that present embodiment has operational stability, can eliminate the advantage of output voltage ripple (ripple).For example, can guarantee to export signal Output during T3 to T8, not the influence of subject clock signal CK2 and make switch M
3Have voltage ripple because of the doubt that has leakage current makes the output signal, its principle is that the current potential of nodes X can be via switch M as the overlapping period T of clock signal CK2 and CK1
1Be coupled to the low level of input signal Input, guarantee switch M
3For closing, can not produce leakage current.
In like manner, the driving method of Fig. 9 C also can be applicable among the embodiment like Fig. 6 and Fig. 8; That is in the driving method shown in Fig. 7 A and Fig. 9 A; With all input signals (like CK1, CK2, CK3, N+2 etc.), comprise the start signal that receives from first driver element, widen length-adjustable pulse width T all in advance; Promptly after the adjustment; The pulse width of each signal will be (T+W), and have the overlapping period of T width between the two adjacent clock signals, and two adjacent clock signals differ stationary phase to each other.And input signal only makes two adjacent clock signals overlap after adjustment can be adjusted the pulse width T of width, but not all overlapping; Wherein, Preferably, length-adjustable pulse width T less than or be not more than 1/2 of adjusted single pulse width (T+W), but not as limit.It is better to have operational stability thus, and can eliminate the advantage of output voltage ripple (ripple).
More than; Gate driver circuit and driving method according to the embodiment of the invention; Not only good in operational degree of stability, fiduciary level, each driver element is only used two or three clock signals simultaneously, and the work period of each clock signal (duty cycle) is 0.25, is 0.33 for the embodiment of Fig. 8 for the embodiment of Fig. 4 and Fig. 6; Compared to work period of the clock signal of prior art is 0.5 can reduce half frequency at the most, so the power consumption of whole driving circuit can significantly reduce.In addition, special one what carry is that the various gate driver circuits described in the embodiment of the invention all can (Integrated gate drive, form IGD) directly be made on the substrate of display panels, but not as limit like integrated grid circuit.
The above is merely the preferred embodiments of the present invention, is not in order to limit claim scope of the present invention; All other do not break away from the equivalence of being accomplished under the spirit that invention discloses and changes or modify, and all should be included in the appended claim scope.
Claims (17)
1. gate driver circuit comprises the driver element of a plurality of serial connections, and each driver element receives a plurality of clock signals to drive load, and each driver element comprises:
Signal input part, receiving inputted signal;
Signal output part, output signal output;
First switch has first end and couples that said signal input part, second end couple first node, control end receives first clock signal;
Second switch has that first end and control end couple said signal input part, second end couples said first node;
The 3rd switch has first termination and receives that second clock signal, second end couple said signal output part, control end couples said first node; And
The 4th switch, said the 4th switch have first end and couple said first node, second end and couple low-voltage source, control end and receive from the output signal of two-stage drive unit down;
Wherein the signal output part of each driver element is coupled to the signal input part of next stage driver element,
Wherein each driver element still comprises mu balanced circuit and is coupled between said first node and the said output terminal, and wherein said mu balanced circuit comprises:
The 5th switch has first end and couples that Section Point, second end couple said low-voltage source, control end couples said signal input part;
The 6th switch has first end and couples that said Section Point, second end couple said low-voltage source, control end couples the 3rd clock signal; Minion is closed, and has first end and couples that said first node, second end couple said low-voltage source, control end couples said Section Point; And
Octavo is closed, and said octavo is closed has that second end, second end that first end couples said the 3rd switch couples said low-voltage source, control end couples said Section Point;
The 9th switch has that first end and control end receive said first clock signal, second end couples said Section Point.
2. gate driver circuit as claimed in claim 1, wherein said the first, second, third, fourth, the 5th, the 6th, the 7th, the 8th and the 9th switch is a thin film transistor (TFT).
3. gate driver circuit as claimed in claim 1, the dutycycle of wherein said first clock signal, said second clock signal, said the 3rd clock signal is 1/4.
4. gate driver circuit as claimed in claim 3, when wherein said input signal was high levle, said first clock signal also was a high levle.
5. gate driver circuit as claimed in claim 1, said second clock signal falls behind said first clock signal, one phase differential, and said the 3rd clock signal falls behind the said phase differential of said second clock signal.
6. gate driver circuit as claimed in claim 5, the pulse of wherein said second clock signal and said first clock signal has lap, and the pulse of said the 3rd clock signal and said second clock signal also has lap.
7. gate driver circuit as claimed in claim 6, the length of wherein said lap be not more than clock signal single pulse width 1/2.
8. gate driver circuit as claimed in claim 7, the length of wherein said lap is less than 1/2 of the single pulse width of clock signal.
9. gate driver circuit comprises the driver element of a plurality of serial connections, and each driver element receives a plurality of clock signals to drive load, and each driver element comprises:
Signal input part, receiving inputted signal;
Signal output part, output signal output;
First switch has first end and couples that said signal input part, second end couple first node, control end receives first clock signal;
Second switch has that first end and control end couple said signal input part, second end couples said first node;
The 3rd switch has first termination and receives that second clock signal, second end couple said signal output part, control end couples said first node; And
The 4th switch, said the 4th switch have first end and couple said first node, second end and couple low-voltage source, control end and receive from the output signal of two-stage drive unit down;
Wherein the signal output part of each driver element is coupled to the signal input part of next stage driver element,
Wherein each driver element still comprises mu balanced circuit and is coupled between said first node and the said output terminal, and wherein said mu balanced circuit comprises:
The 5th switch; Have that control end, second end that first end couples second end that octavo closes and the 6th switch couples low-voltage source, control end couples said signal input part; Said the 6th switch still has first termination to be received first end, second end that said first clock signal and said octavo close and couples Section Point, and first end and control end that said octavo is closed receive said first clock signal simultaneously; And
Minion is closed, and has first end and couples that said first node, second end couple said low-voltage source, control end couples said Section Point.
10. gate driver circuit as claimed in claim 9, wherein said mu balanced circuit still comprise first electric capacity and are coupled between said first node and the said signal output part.
11. gate driver circuit as claimed in claim 9, wherein said first, second, third, fourth, the the 5th, the 6th, the 7th, and octavo close and be thin film transistor (TFT).
12. gate driver circuit as claimed in claim 9, it receives said first clock signal and said second clock signal, and wherein said second clock signal falls behind phase differential of said first clock signal.
13. gate driver circuit as claimed in claim 12, it receives said first clock signal and said second clock signal, and the pulse of wherein said second clock signal and said first clock signal has lap.
14. gate driver circuit as claimed in claim 13, the length of wherein said lap be not more than clock signal single pulse width 1/2.
15. gate driver circuit as claimed in claim 14, the length of wherein said lap is less than 1/2 of the single pulse width of clock signal.
16. like claim 13 or 14 described gate driver circuits, the dutycycle of wherein said first clock signal, said second clock signal is 1/3.
17. gate driver circuit as claimed in claim 16, when wherein said input signal was high levle, said first clock signal also was a high levle.
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| CN 200910221750 CN102063874B (en) | 2009-11-16 | 2009-11-16 | Grid driving circuit |
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| CN 200910221750 CN102063874B (en) | 2009-11-16 | 2009-11-16 | Grid driving circuit |
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| CN102063874B true CN102063874B (en) | 2012-12-19 |
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| CN104167188B (en) * | 2013-05-16 | 2016-07-20 | 瀚宇彩晶股份有限公司 | Driver element and gate driver circuit |
| CN104347044B (en) * | 2013-08-06 | 2017-07-21 | 瀚宇彩晶股份有限公司 | Gate driving circuit |
| CN105304011B (en) * | 2015-12-09 | 2019-11-19 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| CN106991984B (en) * | 2017-05-12 | 2018-05-18 | 惠科股份有限公司 | Shift register circuit and display panel using the same |
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| CN1536580A (en) * | 2003-04-04 | 2004-10-13 | 胜园科技股份有限公司 | Shift register |
| CN1959848A (en) * | 2005-11-04 | 2007-05-09 | 三星Sdi株式会社 | Shift register circuit |
| CN101510443A (en) * | 2009-04-08 | 2009-08-19 | 友达光电股份有限公司 | Shift register capable of reducing coupling effect |
| CN101552040A (en) * | 2009-04-28 | 2009-10-07 | 友达光电股份有限公司 | Shift register of LCD |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1536580A (en) * | 2003-04-04 | 2004-10-13 | 胜园科技股份有限公司 | Shift register |
| CN1959848A (en) * | 2005-11-04 | 2007-05-09 | 三星Sdi株式会社 | Shift register circuit |
| CN101510443A (en) * | 2009-04-08 | 2009-08-19 | 友达光电股份有限公司 | Shift register capable of reducing coupling effect |
| CN101552040A (en) * | 2009-04-28 | 2009-10-07 | 友达光电股份有限公司 | Shift register of LCD |
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