CN102034409B - Method for transmitting data and display using the method - Google Patents

Abstract

A method for transmitting data between a timing controller and a source driver of a display and a display using the data transmission method. In the data transmission method, the beginning of a blank period of a frame period is first confirmed. Then, in the blank period, de-skew data in a data bus is sampled based on a data frequency signal. Then, the de-skew function is performed by comparing the sampled de-skew data with a preset de-skew code and adjusting the data frequency signal. Then, the beginning of a data input period of a frame period is confirmed. Then, in the data input period, pixel data in the data bus is sampled based on the adjusted data frequency signal.

Description

Method for transmitting data and display using the method

technical field

The invention relates to a data transmission method and a display using the method, in particular to a method for transmitting data between a timing controller and a source driver of the display and a display using the method.

Background technique

A liquid crystal display (Liquid Crystal Display; LCD) system includes a timing controller, a driver, and an LCD array composed of rows and columns. The timing controller receives image data and generates timing signals required by the driver to selectively drive pixels in the LCD system. The drivers include at least one source driver and at least one gate driver.

In order to improve the image quality of the LCD, the resolution and update rate of the display are getting higher and higher, however, the higher the transmission speed, the easier it is to cause the problem of signal skew.

Contents of the invention

Therefore, one aspect of the present invention is to provide a data transmission method and a display using the method.

According to an embodiment of the present invention, in the data transmission method, firstly, the start of the blank period of the frame period is confirmed. Next, during the blank period, the de-skew data in the data bus is sampled based on the data clock signal. Then, the de-biasing function is performed by comparing the sampled de-biasing data with a preset de-biasing code, and adjusting the data clock signal. Next, the start of the data input period of the frame period is confirmed. Then, in the data input period, the pixel data in the data bus is sampled based on the adjusted data clock signal.

According to an embodiment of the present invention, the display includes: a timing controller data bus and a source driver. The source driver is electrically connected to the timing controller through the data bus. The source driver is used to perform the following steps: First, the start of the blank period of the frame period is confirmed. Next, in the blank period, the de-skew data in the data bus is sampled based on the data clock signal, so as to perform the de-skew function. Then, in the data input period, the pixel data in the data bus is sampled, wherein the timing controller performs the function of eliminating signal deviation by comparing the sampled signal deviation eliminating data with a preset signal eliminating code.

Description of drawings

In order to make the above-mentioned and other objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is specifically cited above, and in conjunction with the accompanying drawings, the detailed description is as follows:

FIG. 1 is a schematic diagram illustrating the structure of a display according to an embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating the timing of data transmitted from the timing controller to the source driver according to an embodiment of the present invention;

FIG. 3 is a schematic timing diagram illustrating a blank period as shown in FIG. 2;

FIG. 4 is a timing diagram illustrating the data input cycle shown in FIG. 2;

FIG. 5 is a schematic flowchart illustrating a method for transmitting data between a source driver and a timing controller of a display according to an embodiment of the present invention.

Explanation of main component symbols

100: display

102: Source driver

104: Gate driver

106: Timing controller

108: Brightness reference value generator

110: panel

205: Pixel data

210: cycle

220a: Eliminate signal deviation data

220b: buffer data

400: Data Transfer Method

410: Steps

420: Steps

430: Steps

440: Steps

450: Steps

POL: polarity signal

TP: Latch signal

D: data bus

CLK: data frequency signal

F ₁ : frame period

F ₂ : frame period

T _B : blank period

T _D : Data input period

T _R : reset period

Detailed ways

In order to make the illustration of the present invention more clear and complete, the following description will be described with reference to FIG. 1 to FIG. 5 .

Please refer to FIG. 1 , which is a schematic diagram illustrating the structure of a display 100 according to an embodiment of the present invention. The display 100 includes at least one source driver 102 , at least one gate driver 104 , a timing controller 106 , a brightness reference value generator 108 and a panel 110 . The timing controller 106 sends display signals and control signals to the source driver 102 through transmission lines. The control signal includes a polarity signal POL, which is used to control the polarity of the pixels of the panel 110 . The control signal further includes a latch signal TP, and the latch signal TP is used to control the source driver to output the driving signal to the panel 110 . It is worth mentioning that at least one data bus D is used to transmit the pixel data 205 , and the data bus D can be a differential signal line or a single transmission line. In addition, the control signal includes a data clock signal CLK.

Please refer to FIG. 2 , which is a schematic diagram illustrating the timing sequence of data transmitted from the timing controller 106 to the source driver 102 according to an embodiment of the present invention, wherein the data is transmitted in the first frame period F ₁ . In this embodiment, each of the first frame period F ₁ and the second frame period F ₂ includes a blank period _TB and a data input period T _D . During the blank period _TB , the timing controller 106 transmits setting data through the data bus D, wherein the blank period _TB can also be called a vertical blank period (Vertical Blank Period; VBI). The setting data is, for example, the register data 220b for setting the register of the source driver 102 and the de-skew data 220a for the source driver 102 to eliminate the signal skew. The timing controller 106 transmits the pixel data 205 through the data bus D during the data input period T _D . In this embodiment, the setting data is transmitted through the data bus D by using the blank period _TB , so that the number of transmission lines between the timing controller 106 and the source controller can be reduced.

It should be noted that the data clock signal CLK shown in FIG. 2 is just an example for illustrating the embodiment of the present invention. In fact, the frequency of the data clock signal CLK can be several times that shown in FIG. 2 .

Please refer to FIG. 3 , which is a schematic timing diagram illustrating the blank period _TB shown in FIG. 2 . The start of the blank period _TB is confirmed, for example, by checking the states of the polarity signal POL and the latch signal TP. In this embodiment, the blank period _TB is confirmed by the pull-high latch signal TP and the toggled polarity signal POL in the period 210 . After confirming the blank period _TB , the source driver 102 starts to receive setting data. In this embodiment, the setting data are, for example, setting data 220b and signal deviation elimination data 220a.

The source driver 102 receives the setting data 220b to set its own parameters. Since the function of eliminating signal deviation has not been performed, the setting data 220b can be transmitted by another frequency signal with a lower frequency than the data signal clock CLK, and then the source driver 102 can set the device based on the higher frequency data clock signal. The setting data 220b is sampled to ensure the correctness of the sampling of the setting data 220b.

It should be noted that the signal deviation elimination data 220a in this embodiment is transmitted through the data bus during the blank period _TB , and the source driver 102 performs the signal deviation elimination function at the same time. Both the timing controller 106 and the source controller 102 know the preset code for eliminating signal deviation. The timing controller 106 transmits the signal deviation elimination data 220a to the source driver 102 during the blank period _TB . Then, the source driver 102 samples the debiased data 220a to check whether the sampled debiased data 220a corresponds to a preset debiased code. If the DSOD data 220a does not correctly correspond to the preset DSOD code, the source driver 102 will fine-tune the data clock signal. The source driver 102 may perform the above-mentioned function of eliminating signal deviation during the initialization phase after the power of the display 100 is turned on or selectively in each or some blank periods. Furthermore, the source driver 102 may include a memory for storing a preset signal deviation code.

Please refer to FIG. 4 , which is a timing diagram illustrating the data input period T _D shown in FIG. 2 . In this embodiment, the data input period T _D can be confirmed by counting the number of clock pulses and detecting the pull-up signal in the data bus for the reset period T _R . After the data input period T _D is confirmed, the source driver 102 receives the pixel data 205 to drive the panel 110 .

Please refer to FIG. 5 , which is a schematic flowchart illustrating a method 400 for transmitting data between the source driver 102 and the timing controller 106 of the display 100 according to an embodiment of the present invention. In the data transmission method 400, the start of the blank period _TB is first confirmed in step 410, for example, by checking the latch signal TP and the polarity signal POL to confirm the start of the blank period _TB . Then, in step 420, during the blank period _TB , the de-biased data in the data bus is sampled based on the data clock signal CLK. Next, in step 430, the de-bias function is performed by comparing the sampled de-bias data with a preset de-bias code and adjusting the data clock signal CLK. Then, in step 440, the start of the data input period _TD of the frame period _F1 is confirmed. Next, in step 450 , during the data input period T _D , the pixel data 205 in the data bus is sampled based on the adjusted data clock signal.

It should be noted that a step can be performed between steps 410 and 420 to re-sample the register data 220 b in the blank period _TB to initialize the source driver 102 .

According to the above, the embodiment of the present invention utilizes the data bus to transmit the setting data and the signal deviation elimination data in the vertical blank interval, so the embodiment of the present invention does not need an additional transmission line to transmit the setting data and the signal deviation elimination data . In addition, because the data for eliminating signal deviation is transmitted through another clock signal with a lower frequency than the original clock signal, the function of eliminating signal deviation becomes more reliable.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the appended claims.

Claims (13)

1. A data transmission method for transmitting data between a timing controller and a source driver of a display, wherein the data transmission method comprises: Confirming the start of the blank period of the frame period; wherein, the step of confirming the start of the blank period includes: detecting the state of the latch signal and the polarity signal, and confirming that the latch signal is pulled up and is in a binary state said polarity signal of thixotropy; During the blank period, sampling the signal offset data in the data bus based on the data clock signal; Performing the function of eliminating signal deviation by comparing the sampled signal deviation elimination data with the preset signal deviation elimination code, and adjusting the data clock signal; confirming the start of a data entry period for said frame period; and In the data input period, the pixel data in the data bus is sampled based on the adjusted data clock signal. 2. The data transmission method according to claim 1, further comprising: sampling the buffer data in the data bus during the blank period to initialize the source driver. 3. The data transmission method according to claim 2, wherein the timing controller transmits the register data through a clock signal, and the frequency of the clock is lower than the data clock signal. 4. The data transmission method according to claim 3, wherein the source driver samples the buffer data based on the data clock signal. 5. The data transmission method according to claim 1, wherein the blank period is a vertical blank period. 6. The data transfer method of claim 1 , wherein the step of confirming the start of the data entry period comprises: calculating the number of adjusted data clock signals; and Acknowledgment is made by detecting a pulled-up signal in the data bus corresponding to a reset cycle. 7. A display comprising: timing controller; data bus; and a source driver electrically connected to the timing controller through the data bus, wherein the source driver is used to perform the following steps: Acknowledging the start of the blank period of the frame period; wherein the source driver detects the state of the latch signal and the polarity signal, and by acknowledging the latch signal being pulled up and all the the polarity signal to confirm the start of the blanking period; During the blank period, sampling the de-skew data in the data bus based on the data clock signal to perform the de-skew function; and In the data input period of the frame period, sampling the pixel data in the data bus; Wherein, the source driver executes the signal deviation elimination function by comparing the sampled signal deviation elimination data with a preset signal deviation elimination code, and adjusting the data clock signal. 8. The display according to claim 7, wherein the source driver adjusts the data clock signal according to the comparison result, and samples the pixel data based on the adjusted data clock signal . 9. The display of claim 7 , wherein the source driver is pulled up by acknowledging the calculated amount of the data clock signal adjusted and detecting a corresponding reset period in the data bus. signal to confirm the start of the data input period of the frame period. 10. The display as claimed in claim 7, wherein the source driver further samples buffer data in the data bus during the blank period to initialize the source driver. 11. The display as claimed in claim 10, wherein the timing controller transmits the register data through a clock signal, and the frequency of the clock is lower than that of the data clock signal. 12. The display of claim 11, wherein the source driver samples the buffer data based on the data clock signal. 13. The display of claim 7, wherein the blank period is a vertical blank period.

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