[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN101978483A - 原位空腔集成电路块 - Google Patents

原位空腔集成电路块 Download PDF

Info

Publication number
CN101978483A
CN101978483A CN2008801255424A CN200880125542A CN101978483A CN 101978483 A CN101978483 A CN 101978483A CN 2008801255424 A CN2008801255424 A CN 2008801255424A CN 200880125542 A CN200880125542 A CN 200880125542A CN 101978483 A CN101978483 A CN 101978483A
Authority
CN
China
Prior art keywords
nude film
matrix
barrier
flip
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2008801255424A
Other languages
English (en)
Other versions
CN101978483B (zh
Inventor
S·X·梁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Skyworks Solutions Inc
Original Assignee
Skyworks Solutions Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Skyworks Solutions Inc filed Critical Skyworks Solutions Inc
Publication of CN101978483A publication Critical patent/CN101978483A/zh
Application granted granted Critical
Publication of CN101978483B publication Critical patent/CN101978483B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/0077—Other packages not provided for in groups B81B7/0035 - B81B7/0074
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0504—Holders; Supports for bulk acoustic wave devices
    • H03H9/0514—Holders; Supports for bulk acoustic wave devices consisting of mounting pads or bumps
    • H03H9/0523—Holders; Supports for bulk acoustic wave devices consisting of mounting pads or bumps for flip-chip mounting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/058—Holders; Supports for surface acoustic wave devices
    • H03H9/059—Holders; Supports for surface acoustic wave devices consisting of mounting pads or bumps
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0109—Bonding an individual cap on the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0118—Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0172—Seals
    • B81C2203/019—Seals characterised by the material or arrangement of seals between parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10135—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81139—Guiding structures on the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81205—Ultrasonic bonding
    • H01L2224/81207—Thermosonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/81464—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8182—Diffusion bonding
    • H01L2224/8183—Solid-solid interdiffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Acoustics & Sound (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Micromachines (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

在倒装芯片裸片粘结工艺期间在选定的裸片部分下面就地形成空腔的倒装芯片半导体封装装置和方法。倒装芯片半导体元件的封装方法包括提供有第一表面的裸片；在裸片的第一表面上形成屏障，该屏障至少部份地在裸片的第一表面上围住某个指定位置；把裸片按倒装芯片配置粘结到基体上，以及让模塑料在裸片上以及至少在一部分基体上流动。把裸片粘结到基体上包括使屏障和基体之间这样接触，以致模塑料的流动被该屏障阻挡在裸片和基体之间提供空腔，该空腔接近裸片第一表面上的指定位置。

Description

原位空腔集成电路块
发明领域
本发明一般地涉及半导体器件及其制造方法。更具体地说，至少一些实施方案指向倒装芯片半导体包和合并裸片下空腔的封装程序。
背景技术
射频集成电路(RFIC)被广泛地用于无线装置，例如，蜂巢式电话。RFIC在基体上把传输线、匹配网络和电感线圈、电阻、电容器和晶体管之类的分立元件结合在一起提供能够传输和接收高频信号的子系统，举例来说，在大约0.1到100千兆赫(GHz)的范围内。RFIC的封装明显地不同于数字集成电路的封装，因为该封装往往是射频电路的一部份这一事实而且因为RFIC的复杂的射频电场和/或磁场能与任何附近的绝缘体和导体相互作用。为了符合无线工业日益增加的需求，RFIC封装发展设法提供更小巧、更廉价、性能更高的能适应多裸片射频模块的装置，同时提供高的可靠性和使用无铅焊剂和其它“绿色的”材料。单或多裸片RFIC被个别封装的单一芯片封装是解决RFIC的小尺寸和低成本需求的直接解决办法，而且现在被用于大多数RFIC。
微电子机械系统(MEMS)准许微小尺度机械运动和指定的电信号之间的受控转换，举例来说，与指定的频率一致。MEMS正在广泛地用于RFIC。基于机械运动，射频MEMS就射频频带滤波器(包括表面声波(SAW)滤波器、体积声波(BAW)滤波器和高频RF开关)而言能实现极好的信号品质因数。举例来说，SAW滤波器把电信号转换成机械波，后者在它转换回电信号之前沿着压电晶体基体传播的时候被延迟。BAW滤波器使用体积整体运动实现预期的特殊共振，而在RF开关中，电信号用来控制微电极的运动，打开或关闭开关。现在的MEMS技术已经从半导体制造工艺发展起来。然而，独特地与MEMS相关联的机械运动要求完全不同于传统的半导体集成电路的封装构造和要求。具体地说，在所有的MEMS集成电路内部，一些材料必须不受干扰地自由移动，因此，MEMS集成电路必须被遮蔽在运动材料周围形成小的真空或气穴以便在允许它们运动同时保护它们。
用于Infineon Technologies，AG研发的射频MEMS装置的封装的一个范例使用复杂的钝化结构在SAW/BAW滤波器裸片的下面形成气穴。光刻聚合物用来产生为每个共振腔形成空腔的迷宫结构。反面的焊线用来形成滤波器裸片和基体之间的互连。硅制盖子(例如，通常平坦的硅晶片)用B-级粘接剂附着在迷宫结构的顶端，“遮蔽”集成电路并且完成封闭的空腔。这种封装已经是相对有效的MEMS封装，因为它使用标准的裸片粘结和引线接合组装技术。然而，它限制封装尺寸减少，而且迷宫仿形和盖子附着的附加处理步骤增加相当多的复杂性和封装成本，这将降低封装效率和增加成本。
发明内容
至少一些方面和实施方案指向半导体封装和提供MEMS装置所需要的裸片下空腔的封装工艺而且没有传统的组装和封装程序复杂。在一个实施方案中，热超声裸片粘结程序被用于倒装芯片封装程序把裸片粘结到载体基体上，下面将进一步讨论。裸片和/或基体具有绝缘壁，一旦裸片粘结到基体上，该绝缘壁在指定位置周围形成屏障，防止模塑料流进该指定位置。以这种方式，能在裸片的选定部分下面(举例来说，在MEMS装置下面)形成空腔或气隙。依照至少一个实施方案，空腔形成是就地完成的，发生在裸片粘结工艺期间，而且不需要传统的封装程序所需要的复杂的仿形或盖子附着的附加步骤。
依照一个实施方案，倒装芯片半导体元件的封装方法包括提供有第一表面的裸片、在裸片的第一表面上形成屏障，该屏屏障至少部份地在裸片的第一表面上围住某指定位置，把裸片按倒装芯片配置粘结到基体上，以及让模塑料在裸片上和至少在一部分基体上流动。把裸片粘结到基体上包括引起在屏障和基体之间的接触，而模塑料的流动被屏障阻挡在裸片和基体之间提供空腔，该空腔在裸片的第一表面上接近该指定位置。
在一个范例中，该方法进一步包括裸片植球的行为。裸片植球可能包括在裸片的第一表面上形成金凸块或柱状铜凸块。就金凸块而言，把裸片粘结到基体上可能是使用金-金互连工艺在裸片上的金凸块和基体上的镀金传导性焊盘之间形成粘结实现的。就柱状铜凸块而言，把裸片粘结到基体上可能包括使用热超声粘结程序在裸片上的柱状铜凸块和基体上的传导性焊盘之间形成粘结。形成屏障可能包括形成绝缘屏障，举例来说，SU8聚合物组成的屏障。
依照另一个实施方案，封装倒装芯片的元件包括有第一表面的基体，该基体包括安排在该第一表面上的众多传导性焊点；有第二表面的裸片，该裸片包括安排在第二表面上的众多凸块，众多凸块之中的每个凸块被分别粘结到相应的传导性焊点上；接在基体和裸片之间的并且至少部份地安排在裸片上的指定位置周围定义裸片和基体之间的空腔的绝缘屏障；以及覆盖裸片和至少一部分裸片的模塑料，其中模塑料是没有空穴的。
众多凸块可能包括，举例来说，众多柱状铜凸块或众多金凸块。在一个范例中，裸片包括安排在指定位置里面的电路。这种裸片可能包含安排在指定位置里面的MEMS装置。在另一个范例中，空腔是谐振腔。绝缘屏障可能包含SU8聚合物。在一个范例中，在屏障和基体之间以及在屏障和裸片之间有零缝隙。在另一个范例中，屏障完全包围裸片第二表面上的指定位置。
另一个实施方案指向倒装芯片半导体元件的封装方法，该方法包括提供已在其第一表面上形成众多连接凸块的裸片；提供已在其第二表面上形成对应的众多传导性焊盘的基体；在裸片的第一表面上形成绝缘屏障，该绝缘屏障至少部份地围住裸片第一表面上的某个指定位置；用热超声法把裸片粘结到基体上；以及在粘结期间压缩该绝缘屏障消除屏障和基体之间的任何缝隙并且在裸片和基体之间形成空腔，该空腔是由该屏障定义的。用热超声法把裸片粘结到基体上可能包括使用金-金互连程序把众多连接凸块粘结到对应的众多传导性焊盘上。提供裸片可能包括提供包含MEMS装置的裸片，该MEMS装置至少被部份地安排在裸片上的指定位置之内。在一个范例中，形成绝缘屏障包括形成在裸片的第一表面上完全包围指定位置的绝缘屏障。在另一个范例中，该方法进一步包括使模塑料在裸片上以及至少在一部分基体上流动的行为，其中模塑料的流动被阻止模塑料进入空腔的屏障阻挡。形成绝缘屏障可能包括形成用SU8聚合物制成的屏障。
依照另一个实施方案，倒装芯片半导体元件的封装方法包括提供在其第一表面上已形成众多连接凸块的裸片，提供在其第二表面上已形成对应的众多传导性焊盘的基体，在基体的第二表面上形成绝缘屏障，把裸片用热超声法粘结到基体上，以及在粘结期间压缩绝缘屏障清除屏障和裸片之间的任何缝隙并且在裸片和基体之间形成空腔，该空腔是用屏障定义的。在一个范例中，形成绝缘屏障包括形成用SU8聚合物制成的屏障。把裸片用热超声法粘结到基体上可能包括使用金-金互连工艺把众多连接凸块粘结到对应的众多传导性焊盘上。在一个范例中，提供裸片包括提供包含MEMS装置的裸片，该MEMS装置至少被部份地安排在裸片上的指定位置之内。在另一个范例中，形成绝缘屏障包括形成完全包围裸片第一表面上的指定位置的绝缘屏障。该方法可能进一步包括让模塑料在裸片上以及至少在一部分基体上流动，其中模塑料的流动被防止模塑料进入空腔的屏障阻挡。
另一些方面、实施方案和这些可仿效的方面和实施方案的好处将在下面详细地讨论。另外，人们将理解前面的信息和下面的详细描述都只是各种不同的方面和实施方案的说明性范例，而且倾向于提供用来了解权力要求的诸方面和各个实施方案的特性和特征的综述或架构。为了提供例证和进一步理解各种不同的方面和实施方案，附图被包括在内并且被并入和构成这份说明书的一部份。这些附图连同说明书的其余部分一起用来解释所描述的并提出权利要求的各个方面和实施方案的原则和操作。
附图说明
下面参照附图讨论至少一个实施方案的各种不同的方面。在这些不打算依比例绘制的附图中，在各种不同的附图中列举的每个同一的或者几乎同一的元件是用相似的数字表示的。为了清楚，可能并非把每个元件标注在每幅附图中。这些附图是为举例说明和解释准备的，不倾向于作为本发明的极限的定义。在附图中：
图1是依照本发明的诸方面举例说明封装程序的一个范例的流程图；
图2是RFIC裸片的一个范例的剖视图；
图3是依照本发明的诸方面包含绝缘壁的裸片的剖视图；
图4是植球之后图3所示裸片的剖视图；
图5是传统镀金基体的一个范例的剖视图；
图6是依照本发明的诸方面图4所示裸片粘结到图5所示镀金基体上的剖视图；
图7是依照本发明的诸方面封装的装置的剖视图；
图8是依照本发明的诸方面其上已形成BAW滤波器的半导体基体部分的图像；而
图9是图8所示BAW滤波器部分的放大图像，举例说明绝缘壁阻阻止模塑料进入空腔。
具体实施方式
一种广泛用于射频集成电路(RFIC)的半导体封装技术被称为“倒装芯片”封装，其中裸片(包含射频电路)和基体(提供结构支持)之间的互连是通过直接放在裸片表面上的传导性“凸块”形成的。植球的裸片然后被“翻转”并且被正面朝下地放在基体上，凸块把裸片直接连接到基体上。依照前面的讨论，倒装芯片的RFIC(具体地说，包含MEMS装置的那些)需要(或者大大受益于)安排在MEMS电路和基体之间的空腔。然而，用来提供这些空腔的传统技术需要复杂的组装程序，包括附上平坦“盖子”晶片完成空腔。相反，至少一些方面和实施方案指向倒装芯片的封装方法，该方法在倒装芯片裸片粘结程序期间在选定的裸片部分下面就地形成空腔。
空腔(例如，气隙)在裸片下面的就地形成可能是通过选择传导性材料(例如，铜)和绝缘材料(例如，焊料掩模和聚合物)在裸片和/或基体上的图案结构和使用受控的二次模塑(overmolding)程序完成的。依照下面的讨论，依照至少一个实施方案，可能在裸片或基体上提供电介体的围墙，当裸片粘结到基体上的时候在指定位置周围形成屏障。实质上允许在围墙和裸片/基体之间没有缝隙，以致围墙在二次模塑(overmolding)程序期间阻止模塑料流进指定位置。本发明的实施方案提供减少或取消传统的空腔成形术所需要的附加程序步骤(例如，盖子附着、无边帽晶片粘结，等等)的利益。因此，本发明的实施方案可能促成简单的组装程序流程和诸如BAW或SAW滤波器之类RFIC或其它MEMS装置的低成本封装。除此之外，依照下面的讨论，热超声裸片粘结程序可能连同低成本金凸块或铜柱的植球技术一起进一步促成将污染减到最少的低成本封装和无焊剂粘结。
人们将领会到在此讨论的方法和装置的实施方案在应用方面不局限于在下面的描述中陈述的或在附图中列举的元件的构造和安排的细节。这些方法和装置能够在其它的实施方案中以各种不同的方式落实、实践或完成。在此提供特定落实的范例仅仅是为了举例说明而不打算作为限制。具体地说，结合任何一个或多个实施方案讨论的行为和特征不倾向于在任何其它的实施方案中排除在相似的角色之外。另外，在此使用的措辞和术语是为了描述，不应该被视为限制。
图1举例说明封装半导体装置的方法的一个范例的流程图。该封装方法的各个方面和实施方案将下面继续参照图1进行讨论。
参照图2，举例说明裸片200的一个范例的剖视图。裸片200可能是RFIC，而且在至少一个范例中，包括电路202所指定的微电子机械系统(MEMS)装置。然而，本发明不局限于MEMS装置，电路202可能包含不同于射频电路和不同于MEMS装置的电路。裸片200还包含焊盘204，为了允许将裸片200以倒装芯片的方式装到基体上，凸块将粘结到所述的焊盘上，下面将进一步讨论。
依照一个实施方案，该封装方法的步骤100包括在裸片200上的指定位置周围(电路202周围)形成屏障。这个屏障将在裸片200粘结到基体上之后提供接近电路202的空腔，下面将进一步讨论。该屏障是通过在裸片上形成围住或至少部份地围住电路202的围墙206提供的。在一个范例中，这些围墙206是由聚合物(例如，SU8)形成的。步骤100可能包括在裸片上沉积一层聚合物然后有选择地除去聚合物以便形成围墙206。作为替代，聚合物可能是选择性地沉积的以便直接地形成围墙206。聚合物沉积(和选择性的除去)有成为可以使用已知的制造技术完成的简单的制造方法的优势。然而，本发明不局限于使用聚合物形成围墙206，而且可能改为使用不同于聚合物的其它材料，例如，电介体。
依照前面的讨论，在倒装芯片封装中，裸片经由安排在裸片上的“凸块”直接粘结到基体上。所以，再一次参照图1，步骤102包括为粘结准备裸片200的裸片植球程序。包含凸块208的裸片200是用图4举例说明的。有几种类型的凸块和用于倒装芯片装置的植球程序。一个范例包括通过用标准的金丝焊线造成立柱状凸块在裸片200上形成金凸块208。在另一个范例中，金凸块可能是通过在预期的凸块位置沉积一层金或通过给用另一种材料(例如，镍)形成的焊盘204镀金形成的。金凸块在许多应用中是有利的，因为金键有良好的键合强度、优异的高频性能和低阻抗。在另一个范例中，植球程序102可能包括在裸片200上形成柱状铜凸块208。柱状铜凸块包括附着到焊盘204上的铜柱和安排在铜柱顶端的粘结帽(未展示)。柱状铜凸块由于铜的传导性好以改良的热特性提供一些利益，例如优良的电连接。除此之外，柱状铜凸块由于铜呈圆筒形可以比同样高度的球形焊接剂凸块狭窄，并因此可能促成更纤细的连接栅格。为了制造柱状铜凸块，植球步骤100可能包含双阶段电镀程序，在该程序中先将铜柱电镀到焊点204上，然后在铜柱的顶端沉积粘结帽(它通常可能包含焊接剂或金)。
人们将领会到虽然形成屏障206的步骤100在图1中被举例说明为在裸片植球程序102之前，但是本发明不受这样的限制，完成这些步骤的次序可以颠倒。除此之外，步骤100和102之一或两者可以在个别裸片水平或在晶片水平完成。举例来说，晶片可能包含众多裸片，通常有成千上万个裸片。在植球和/或形成屏障之后，晶片可能被单独挑出成为个别的裸片200。
仍然参照图1，在一个实施方案中，该封装程序包括为裸片粘结程序106准备基体的步骤104。参照图5，举例说明基体的范例。基体210包含可以附着到裸片的凸块上的传导性焊点212。普通的基体材料用有机树脂制成的印刷电路板。然而，作为替代，基体210可能包含陶瓷、硅或另一种绝缘材料。在一个范例中，基体是用金涂装的层压基体，例如，FR4，以致焊点212是由金形成的(或者至少是镀金的)。作为替代，在其它的范例中，焊点可能包含除了金之外的传导性材料或金属，例如，铜、银、钯或焊接剂。在粘结裸片之前，传导性焊点212可能被清理(作为步骤104的一部份)，举例来说，使用熟悉这项技术的人已知的等离子体清洁程序。准备步骤104也可能包括沉积绝缘层214(例如，焊接剂掩模)。人们将领会到虽然步骤104在图1中被举例说明为跟在步骤100和102之后，但是本发明没有这样的限制，步骤104可以在粘结(即，步骤106)之前的任何时候完成。
再一次参照图1，步骤106包括把一个或多个裸片200粘结到基体210上。依照一个实施方案，裸片粘结程序106包括热超声程序，在该程序中将热能和机械压力施加到裸片200上在基体210上的焊点212和凸块208之间形成粘结。依照前面的讨论，在一个范例中，凸块208可能是金凸块。在这种情况下，可以使用标准的金-金互连(GGI)粘结程序。GGI是使用叫做GGI粘结器的机器使金凸块和金焊盘借助热能和超声波能量在压头作用下结合在一起的热超声程序。热超声程序连接是借助两个金层之间的固态粘结完成的。在负荷和超声波能量的作用下金的散布(微焊接)产生作为无空隙的完整的粘结层的金-金连接。GGI粘结是成本较低的技术，也是无焊剂的粘结方法，是对环境友好的而且将装置的污染减到最少。超声波GGI程序有大约±10μm的安装精度而且能以如同100μm那样薄的厚度可靠地粘结裸片。在另一个范例中，依照前面的讨论，凸块208可能是的柱状铜凸块，而热超声程序可能用来把裸片200粘结到基体210上。可能使用的热超声粘结程序的范例是在2007年12月17日以为“Thermal Mechanical Flip ChipBonding”题申请的共同拥有且共同未审的美国专利申请第11/957,730号中描述的，在此通过引证将该申请并入。
参照图6，举例说明裸片200粘结到基体210上的剖视图。在一个实施方案中，围墙206的高度h是受控制的，以致当裸片200粘结到基体210上的时候，围墙206被略微压缩，以便在围墙206和基体210之间留下本质上为零的缝隙。因此，围墙206形成围住电路202的屏障并且在裸片下面形成空腔216。这个空腔(或气隙)216是在裸片粘结程序106期间就地形成的，不需要如同采用传统的形成空腔的方法的情况将独立的“盖帽”附着上去完成空腔。虽然在图7中只画出左边和右边的围墙，但是人们应该领会到为了部份地或完全地围住电路202可能提供附加的围墙(例如，在图7的前面和背面)。人们应该进一步领会到围墙可以有只由电路的倾向性应用的需求规定的任何预期的形状。当模塑料218(见图7)在受控的二次注塑程序(步骤108)中被加到裸片200和基体210上的时候，围墙206阻止模塑料218进入空腔216，并因此维持空腔216在电路202之下。人们将领会到虽然空腔可能最普遍地充满空气，但是它也可能充满另一种物质或真空。
依照一个范例，围墙206的高度是至少部份地基于组成围墙206的材料(即，围墙的可压缩性)、焊盘212的已知高度222、凸块208的离岸距离220和在裸片200的热超声粘结期间对基体210施加的压力选定的。在一个范例中，传导性焊盘212的高度是大约27微米(μm)，凸块离岸距离220在大约10-20μm的范围内。凸块离岸距离可能在裸片200与基体210粘结期间减少。所以，在一个范例，围墙206的高度h是大约40μm，以致在粘结之后，在围墙206和基体210之间本质上没有缝隙。人们将领会到在此提供的尺寸只是范例，不倾向于作为限制。围墙206、传导性焊点212和凸块离岸距离220的尺寸可能改变，取决于应用、所用的材料和所用的裸片粘结程序。
依照前面的讨论，至少在一些实施方案中，围墙206是在裸片200粘结到基体上210之前在裸片200上形成的。然而，作为替代，围墙206可能是在裸片200粘结到基体上210之前在基体210上形成的。依照前面的讨论，围墙206可能是通过基体受控的形成图案和使用传统的电介质沉积程序和非必选的选择性清除程序在基体210上形成的。在这个范例中，为了在裸片200粘结到基体210上的时候在围墙顶端和裸片200之间提供本质上为零的缝隙，围墙206和凸块208的离岸距离(即，高度)是受控的。
封装的BAW滤波器的一些范例是使用在此讨论的封装方法的实施方案生产的。图8举例说明包含范例BAW滤波器300的基体部分的顶面图像。那些BAW滤波器300在基体上被使用传统方法形成的“街道”302彼此分开。BAW滤波器包含若干传导性连接点304，这些连接点允许信号进出BAW滤波器300。绝缘围墙206形成的屏障308(见图6)在BAW滤波器裸片周围清晰可见。在这个范例中，屏障308由SU8聚合物组成。模塑料是使用受控的二次注塑(overmolding)程序加到BAW滤波器上的。屏障308阻止模塑料在指定位置流动以便在BAW滤波器裸片的下面形成未填充的气隙。模塑料310被屏障308阻断在图9中能看到，该图是。一部分BAW滤波器300的放大图像。在二次注塑(overmolding)程序之后，基体可能沿着街道302被单独挑出，以形成个别的封装元件(图1的步骤110)。
为了测试使用作为本发明的实施方案的倒装芯片封装方法形成的元件的强健性，一些范例BAW滤波器元件被生产出来并且经受“剪切”测试。在这些测试中，剪切力被施加在元件上，该力连续地(或递增地)增加，直到将裸片与基体剪开。这个测试提供关于凸块208和裸片200之间以及凸块208和基体焊点212之间粘结的强度和机械完整性的数据。下面的表1包含依照在此讨论的封装程序的实施方案制造的十一个BAW滤波器范例的测试结果数据。在每一个范例中，裸片包含金凸块208并且是使用GGI粘结程序粘结到基体上的。GGI粘结机是为在GGI粘结程序期间施加5牛顿的粘结力和施加1.5瓦特的超声波功率持续0.3秒而编程的。
表1：BAW滤波器封装范例的裸片剪切数据
  范例编号   凸块转移   凸块高度(μm)   裸片剪切力(Kgf)
  1   6   20.3   261.50
  2   5   21.9   331.80
  3   4   19.5   227.90
  4   5   20.9   202.80
  5   5   22.0   254.60
  6   5   22.5   255.40
  7   4   21.8   241.40
  8   6   24.3   248.20
  9   4   23.8   244.00
  10   6   23.4   210.20
  11   6   20.8   219.40
  最小值   4.00   19.5   202.80
  最大值   6.00   24.3   331.80
  平均值   5.09   21.93   245.17
  标准差   0.83   1.5   34.60
*“凸块转移”指的是在第4列中列出的裸片剪切力之下从裸片上剪掉的凸块的数目，暗示凸块和基体焊点之间的粘结良好。
表1的数据指出依照在此讨论的封装方法的范例封装的元件证明好的结合点强度和可靠性。原位空腔的出现和在空腔区域中没有模塑料不对元件的机械可靠性产生不利影响。因此，这些以简单清楚和低成本的封装方法就地形成裸片下空腔的方面和实施方案提供强健可靠的封装元件，例如，RFIC(具体地说，MEMS装置)。
至此已经描述了至少一个实施方案的一些方面，人们将领会到各种不同的变更、修正和改进对于熟悉这项技术的人将很容易发生。这样的变更、修正和改进预计将成为这份揭示的一部份而且倾向于在本发明的范围之内。因此，前面的描述和附图只是作为范例，而本发明的范围应该依据对所附权利要求书及其等价文件的适当解释确定。

Claims (24)

1.一种倒装芯片封装元件，其中包括：
有第一表面的基体，该基体包括安排在第一表面上的众多传导性焊点；
有第二表面的裸片，该裸片包括安排在第二表面上的众多凸块，众多凸块之中的每个凸块被分别粘结到相应的传导性焊点上；
接在基体和裸片之间并且至少部份地安排在裸片上围住定义裸片和基体之间的空腔的指定位置的绝缘屏障；以及
覆盖裸片和至少一部分裸片的模塑料；
其中模塑料没有空穴。
2.根据权利要求1的倒装芯片封装元件，其中绝缘屏障包含SU8聚合物。
3.根据权利要求1的倒装芯片封装元件，其中在屏障和基体之间和在屏障和裸片之间的缝隙为零。
4.根据权利要求1的倒装芯片封装元件，其中众多凸块包括众多柱状铜凸块。
5.根据权利要求1的倒装芯片封装元件，其中众多凸块包括众多金凸块。
6.根据权利要求1的倒装芯片封装元件，其中裸片包含安排在指定位置内的电路。
7.根据权利要求1的倒装芯片封装元件，其中裸片包含安排在指定位置内的MEMS装置。
8.根据权利要求1的倒装芯片封装元件，其中空腔是谐振腔。
9.根据权利要求1的倒装芯片封装元件，其中屏障在裸片的第二表面上完全包围指定位置。
10.一种倒装芯片半导体元件的封装方法，该方法包括：
提供裸片，该裸片在其第一表面上已形成众多连接凸块；
提供基体，该基体在其第二表面上已形成众对应的传导性焊盘；
在裸片的第一表面和基体的第二表面之一上形成绝缘屏障；
用热超声法把裸片粘结到基体上；以及
在粘结期间压缩绝缘屏障消除屏障和基体之间的任何缝隙并且在裸片和基体之间形成空腔，该空腔是靠屏障定义的。
11.根据权利要求10的方法，其中用热超声法把裸片粘结到基体上包括使用金-金互连工艺把众多连接凸块粘结到对应的众多传导性焊盘上。
12.根据权利要求10的方法，其中形成绝缘屏障包括形成用SU8聚合物制成的屏障。
13.根据权利要求10的方法，其中形成绝缘屏障包括形成当裸片粘结到基体上的时候至少部份地在裸片的第一表面上包围某指定位置的绝缘屏障。
14.根据权利要求13的方法，其中提供裸片包括提供包含MEMS装置的裸片，该MEMS装置至少被部份地安排在裸片上的指定位置之内。
15.根据权利要求13的方法，其中形成绝缘屏障包括形成在裸片的第一表面上完全包围某指定位置的绝缘屏障。
16.根据权利要求15的方法，进一步包括让模塑料在裸片和至少一部分基体上流动，其中模塑料的流动被防止模塑料进入空腔的屏障阻挡。
17.一种倒装芯片半导体元件的封装方法，该方法包括：
提供有第一表面的裸片；
在裸片的第一表面上形成一屏障，该屏障至少部份地围住裸片第一表面上的某指定位置；
把裸片按倒装芯片配置粘结到基体上；以及
让模塑料在裸片上和至少在一部分基体上流动；
其中把裸片粘结到基体上包括引起屏障和基体之间的接触；
其中模塑料的流动被在裸片和基体之间提供空腔的屏障阻挡，该空腔接近裸片第一表面上的指定位置。
18.根据权利要求17的方法，进一步包括给裸片植球。
19.根据权利要求18的方法，其中给裸片植球包括在裸片的第一表面上形成金凸块。
20.根据权利要求19的方法，其中基体包含镀金焊盘，而把裸片粘结到基体上包括使用金-金互连工艺在裸片上的金凸块和基体上的镀金传导性焊点之间形成粘结。
21.根据权利要求18的方法，其中给裸片植球包括形成裸片第一表面的柱状铜凸块。
22.根据权利要求21的方法，其中基体包括传导性焊盘，而把裸片粘结到基体上包括使用热超声粘结程序在裸片上的柱状铜凸块和基体上的传导性焊盘之间形成粘结。
23.根据权利要求17的方法，其中形成屏障包括形成绝缘屏障。
24.根据权利要求23的方法，其中形成绝缘屏障包括形成由SU8聚合物组成的屏障。
CN200880125542.4A 2007-12-26 2008-11-10 原位空腔集成电路块 Active CN101978483B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/964,092 2007-12-26
US11/964,092 US8900931B2 (en) 2007-12-26 2007-12-26 In-situ cavity integrated circuit package
PCT/US2008/082975 WO2009085409A1 (en) 2007-12-26 2008-11-10 In-situ cavity integrated circuit package

Publications (2)

Publication Number Publication Date
CN101978483A true CN101978483A (zh) 2011-02-16
CN101978483B CN101978483B (zh) 2014-07-16

Family

ID=40824624

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200880125542.4A Active CN101978483B (zh) 2007-12-26 2008-11-10 原位空腔集成电路块

Country Status (6)

Country Link
US (2) US8900931B2 (zh)
EP (1) EP2235747B1 (zh)
KR (1) KR101581971B1 (zh)
CN (1) CN101978483B (zh)
HK (1) HK1150470A1 (zh)
WO (1) WO2009085409A1 (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103420323A (zh) * 2012-04-25 2013-12-04 罗伯特·博世有限公司 微机械元件和微机械元件的制造方法
CN105668502A (zh) * 2016-03-24 2016-06-15 美新半导体（无锡）有限公司 一种带腔体器件的气密封装结构及其制造方法
CN106816420A (zh) * 2015-11-30 2017-06-09 讯芯电子科技（中山）有限公司 一种声波元件封装结构及其制造方法
CN106946216A (zh) * 2016-01-07 2017-07-14 中芯国际集成电路制造(上海)有限公司 一种mems器件及其制备方法、电子装置
CN108512523A (zh) * 2017-11-06 2018-09-07 贵州中科汉天下微电子有限公司 压电声波器件的封装方法及封装结构
CN111003682A (zh) * 2018-10-08 2020-04-14 凤凰先驱股份有限公司 电子封装件及其制法
CN113200510A (zh) * 2021-04-29 2021-08-03 日月光半导体制造股份有限公司 半导体结构
CN113889445A (zh) * 2020-07-02 2022-01-04 江苏中科智芯集成科技有限公司 一种晶圆级芯片封装结构及封装方法

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110049703A1 (en) * 2009-08-25 2011-03-03 Jun-Chung Hsu Flip-Chip Package Structure
US8617927B1 (en) * 2011-11-29 2013-12-31 Hrl Laboratories, Llc Method of mounting electronic chips
US8531040B1 (en) * 2012-03-14 2013-09-10 Honeywell International Inc. Controlled area solder bonding for dies
DE102012224424A1 (de) * 2012-12-27 2014-07-17 Robert Bosch Gmbh Sensorsystem und Abdeckvorrichtung für ein Sensorsystem
CN104079249B (zh) 2013-03-27 2018-05-04 精工爱普生株式会社 电子器件、电子设备、移动体、电子器件的制造方法
WO2014194025A1 (en) * 2013-05-29 2014-12-04 Cavendish Kinetics, Inc Techniques for chip scale packaging without solder mask
US10079160B1 (en) 2013-06-21 2018-09-18 Hrl Laboratories, Llc Surface mount package for semiconductor devices with embedded heat spreaders
US9559071B2 (en) 2013-06-26 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming hybrid bonding structures with elongated bumps
DE112013003153T5 (de) * 2013-06-28 2015-05-13 Intel IP Corporation Mikroelektromechanisches System (MEMS) auf anwendungspezifischer integrierter Schaltung (ASIC)
US10074628B2 (en) 2013-10-04 2018-09-11 Mediatek Inc. System-in-package and fabrication method thereof
US9165877B2 (en) * 2013-10-04 2015-10-20 Mediatek Inc. Fan-out semiconductor package with copper pillar bumps
US10103128B2 (en) 2013-10-04 2018-10-16 Mediatek Inc. Semiconductor package incorporating redistribution layer interposer
US9370107B2 (en) * 2014-04-18 2016-06-14 Unimicron Technology Corp. Embedded component structure and process thereof
DE102014118214B4 (de) * 2014-12-09 2024-02-22 Snaptrack, Inc. Einfach herstellbares elektrisches Bauelement und Verfahren zur Herstellung eines elektrischen Bauelements
US9704808B2 (en) * 2015-03-20 2017-07-11 Mediatek Inc. Semiconductor device and wafer level package including such semiconductor device
US9385083B1 (en) 2015-05-22 2016-07-05 Hrl Laboratories, Llc Wafer-level die to package and die to die interconnects suspended over integrated heat sinks
FR3041625B1 (fr) * 2015-09-29 2021-07-30 Tronics Microsystems Dispositif de fixation de deux elements tels qu'une puce, un interposeur et un support
US10026672B1 (en) 2015-10-21 2018-07-17 Hrl Laboratories, Llc Recursive metal embedded chip assembly
TWI676591B (zh) 2015-10-28 2019-11-11 美商伊凡聖斯股份有限公司 用於具有微機電系統（ｍｅｍｓ）間隙控制結構之mems裝置的方法及設備
US9508652B1 (en) 2015-11-24 2016-11-29 Hrl Laboratories, Llc Direct IC-to-package wafer level packaging with integrated thermal heat spreaders
US10329142B2 (en) * 2015-12-18 2019-06-25 Samsung Electro-Mechanics Co., Ltd. Wafer level package and method of manufacturing the same
US10333493B2 (en) 2016-08-25 2019-06-25 General Electric Company Embedded RF filter package structure and method of manufacturing thereof
US10103095B2 (en) 2016-10-06 2018-10-16 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect
US10923449B2 (en) 2016-10-06 2021-02-16 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect
US11069606B2 (en) 2016-10-06 2021-07-20 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect
DE102016124270A1 (de) * 2016-12-13 2018-06-14 Infineon Technologies Ag Halbleiter-package und verfahren zum fertigen eines halbleiter-package
US10170304B1 (en) 2017-10-25 2019-01-01 Globalfoundries Inc. Self-aligned nanotube structures
KR102456322B1 (ko) * 2017-11-08 2022-10-19 삼성전기주식회사 기판 스트립 및 이를 포함하는 전자소자 패키지
KR102466332B1 (ko) * 2018-01-02 2022-11-15 삼성전자주식회사 가스 센서 패키지
US10468342B2 (en) 2018-02-02 2019-11-05 Compass Technology Company, Ltd. Formation of fine pitch traces using ultra-thin PAA modified fully additive process
US10636734B2 (en) 2018-02-02 2020-04-28 Compass Technology Company, Ltd. Formation of fine pitch traces using ultra-thin PAA modified fully additive process
CN109065701B (zh) * 2018-08-10 2024-03-29 浙江熔城半导体有限公司 带有单围堰、金属柱及焊锡的芯片封装结构及其制作方法
US11894824B2 (en) 2018-08-30 2024-02-06 Skyworks Solutions, Inc. Laser-marked packaged surface acoustic wave devices
US10923365B2 (en) * 2018-10-28 2021-02-16 Richwave Technology Corp. Connection structure and method for forming the same
US20200135627A1 (en) * 2018-10-30 2020-04-30 Texas Instruments Incorporated Substrates with solder barriers on leads
US10950562B1 (en) 2018-11-30 2021-03-16 Hrl Laboratories, Llc Impedance-matched through-wafer transition using integrated heat-spreader technology
CN111371428A (zh) * 2018-12-26 2020-07-03 中芯集成电路（宁波）有限公司上海分公司 控制电路与表面声波滤波器的集成方法和集成结构
CN111371424A (zh) * 2018-12-26 2020-07-03 中芯集成电路（宁波）有限公司上海分公司 控制电路与体声波滤波器的集成方法和集成结构
US20200273823A1 (en) * 2019-02-27 2020-08-27 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
KR102724663B1 (ko) 2019-12-16 2024-10-31 삼성전자주식회사 팬 아웃 반도체 패키지
US11316550B2 (en) 2020-01-15 2022-04-26 Skyworks Solutions, Inc. Biasing of cascode power amplifiers for multiple power supply domains
CN113594119B (zh) * 2021-06-25 2024-05-14 苏州汉天下电子有限公司 半导体封装及其制造方法
CN116130429A (zh) * 2022-12-01 2023-05-16 唯捷创芯(天津)电子技术股份有限公司 Csp滤波器的封装结构、制备方法、电路结构和电子设备

Family Cites Families (87)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323051A (en) * 1991-12-16 1994-06-21 Motorola, Inc. Semiconductor wafer level package
US5448014A (en) * 1993-01-27 1995-09-05 Trw Inc. Mass simultaneous sealing and electrical connection of electronic devices
US5561085A (en) * 1994-12-19 1996-10-01 Martin Marietta Corporation Structure for protecting air bridges on semiconductor chips from damage
US6140144A (en) * 1996-08-08 2000-10-31 Integrated Sensing Systems, Inc. Method for packaging microsensors
US5798557A (en) * 1996-08-29 1998-08-25 Harris Corporation Lid wafer bond packaging and micromachining
JP3622435B2 (ja) * 1997-08-06 2005-02-23 富士通株式会社 半導体装置とその製造方法
US5893726A (en) * 1997-12-15 1999-04-13 Micron Technology, Inc. Semiconductor package with pre-fabricated cover and method of fabrication
DE19801312A1 (de) * 1998-01-15 1999-07-22 Siemens Ag Halbleiterbauelement mit mehreren Substratlagen und zumindest einem Halbleiterchip und einem Verfahren zum Herstellen eines solchen Halbleiterbauelementes
EP0951068A1 (en) * 1998-04-17 1999-10-20 Interuniversitair Micro-Elektronica Centrum Vzw Method of fabrication of a microstructure having an inside cavity
US6143981A (en) * 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6399426B1 (en) * 1998-07-21 2002-06-04 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
JP2000114413A (ja) * 1998-09-29 2000-04-21 Sony Corp 半導体装置、その製造方法および部品の実装方法
US6566745B1 (en) * 1999-03-29 2003-05-20 Imec Vzw Image sensor ball grid array package and the fabrication thereof
US6498114B1 (en) * 1999-04-09 2002-12-24 E Ink Corporation Method for forming a patterned semiconductor film
US6265246B1 (en) * 1999-07-23 2001-07-24 Agilent Technologies, Inc. Microcap wafer-level package
US6228675B1 (en) * 1999-07-23 2001-05-08 Agilent Technologies, Inc. Microcap wafer-level package with vias
CA2381230A1 (en) 1999-09-03 2001-03-15 Uniax Corporation Encapsulation of organic electronic devices
US6297551B1 (en) * 1999-09-22 2001-10-02 Agere Systems Guardian Corp. Integrated circuit packages with improved EMI characteristics
US6452238B1 (en) * 1999-10-04 2002-09-17 Texas Instruments Incorporated MEMS wafer level package
US6750521B1 (en) * 1999-10-22 2004-06-15 Delphi Technologies, Inc. Surface mount package for a micromachined device
US6441481B1 (en) * 2000-04-10 2002-08-27 Analog Devices, Inc. Hermetically sealed microstructure package
JP3597754B2 (ja) * 2000-04-24 2004-12-08 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP2002016181A (ja) * 2000-04-25 2002-01-18 Torex Semiconductor Ltd 半導体装置、その製造方法、及び電着フレーム
US6384473B1 (en) * 2000-05-16 2002-05-07 Sandia Corporation Microelectronic device package with an integral window
US6214644B1 (en) * 2000-06-30 2001-04-10 Amkor Technology, Inc. Flip-chip micromachine package fabrication method
TW457657B (en) 2000-07-14 2001-10-01 Jou Jeng San Wafer-level packaging of micro electromechanical elements and fabrication method thereof
US6402970B1 (en) * 2000-08-22 2002-06-11 Charles W. C. Lin Method of making a support circuit for a semiconductor chip assembly
US6530515B1 (en) * 2000-09-26 2003-03-11 Amkor Technology, Inc. Micromachine stacked flip chip package fabrication method
US6710682B2 (en) * 2000-10-04 2004-03-23 Matsushita Electric Industrial Co., Ltd. Surface acoustic wave device, method for producing the same, and circuit module using the same
US6630725B1 (en) * 2000-10-06 2003-10-07 Motorola, Inc. Electronic component and method of manufacture
US6358773B1 (en) * 2000-12-27 2002-03-19 Vincent Lin Method of making substrate for use in forming image sensor package
US6525420B2 (en) * 2001-01-30 2003-02-25 Thermal Corp. Semiconductor package with lid heat spreader
JP4055368B2 (ja) * 2001-02-27 2008-03-05 日本電気株式会社 二次電池
JP2002261190A (ja) * 2001-02-28 2002-09-13 Sony Corp 半導体装置、その製造方法及び電子機器
US6773962B2 (en) * 2001-03-15 2004-08-10 General Electric Company Microelectromechanical system device packaging method
TWI312166B (en) * 2001-09-28 2009-07-11 Toppan Printing Co Ltd Multi-layer circuit board, integrated circuit package, and manufacturing method for multi-layer circuit board
US6787897B2 (en) * 2001-12-20 2004-09-07 Agilent Technologies, Inc. Wafer-level package with silicon gasket
US6673698B1 (en) * 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
JP2003218256A (ja) 2002-01-21 2003-07-31 Kyocera Corp 電子部品収納用パッケージ
US6660564B2 (en) * 2002-01-25 2003-12-09 Sony Corporation Wafer-level through-wafer packaging process for MEMS and MEMS package produced thereby
US7045459B2 (en) * 2002-02-19 2006-05-16 Northrop Grumman Corporation Thin film encapsulation of MEMS devices
US6838309B1 (en) * 2002-03-13 2005-01-04 Amkor Technology, Inc. Flip-chip micromachine package using seal layer
WO2003079439A2 (en) * 2002-03-19 2003-09-25 Koninklijke Philips Electronics N.V. Chip stack with intermediate cavity
TW560020B (en) * 2002-04-15 2003-11-01 Advanced Semiconductor Eng A wafer-level package with a cavity and fabricating method thereof
KR100850879B1 (ko) 2002-05-15 2008-08-07 엘지이노텍 주식회사 저온 소성 세라믹을 이용한 안테나 스위치
US7059048B2 (en) * 2002-06-07 2006-06-13 Intel Corporation Wafer-level underfill process making use of sacrificial contact pad protective material
DE10228593A1 (de) * 2002-06-26 2004-01-15 Infineon Technologies Ag Elektronisches Bauteil mit einer Gehäusepackung
US7265429B2 (en) * 2002-08-07 2007-09-04 Chang-Feng Wan System and method of fabricating micro cavities
SG111972A1 (en) * 2002-10-17 2005-06-29 Agency Science Tech & Res Wafer-level package for micro-electro-mechanical systems
US6929974B2 (en) * 2002-10-18 2005-08-16 Motorola, Inc. Feedthrough design and method for a hermetically sealed microdevice
JP4342174B2 (ja) * 2002-12-27 2009-10-14 新光電気工業株式会社 電子デバイス及びその製造方法
US6872589B2 (en) * 2003-02-06 2005-03-29 Kulicke & Soffa Investments, Inc. High density chip level package for the packaging of integrated circuits and method to manufacture same
DE10310617B4 (de) * 2003-03-10 2006-09-21 Infineon Technologies Ag Elektronisches Bauteil mit Hohlraum und ein Verfahren zur Herstellung desselben
US6812558B2 (en) * 2003-03-26 2004-11-02 Northrop Grumman Corporation Wafer scale package and method of assembly
US6743991B1 (en) * 2003-04-14 2004-06-01 Agilent Technologies, Inc. Polymeric liquid metal switch
US20040259325A1 (en) * 2003-06-19 2004-12-23 Qing Gan Wafer level chip scale hermetic package
US7368808B2 (en) * 2003-06-30 2008-05-06 Intel Corporation MEMS packaging using a non-silicon substrate for encapsulation and interconnection
JP4269806B2 (ja) * 2003-06-30 2009-05-27 カシオ計算機株式会社 半導体装置およびその製造方法
US7203394B2 (en) * 2003-07-15 2007-04-10 Rosemount Aerospace Inc. Micro mirror arrays and microstructures with solderable connection sites
US7045868B2 (en) * 2003-07-31 2006-05-16 Motorola, Inc. Wafer-level sealed microdevice having trench isolation and methods for making the same
US6777263B1 (en) * 2003-08-21 2004-08-17 Agilent Technologies, Inc. Film deposition to enhance sealing yield of microcap wafer-level package with vias
US7275424B2 (en) * 2003-09-08 2007-10-02 Analog Devices, Inc. Wafer level capped sensor
US20050054133A1 (en) * 2003-09-08 2005-03-10 Felton Lawrence E. Wafer level capped sensor
US7713841B2 (en) * 2003-09-19 2010-05-11 Micron Technology, Inc. Methods for thinning semiconductor substrates that employ support structures formed on the substrates
US7129576B2 (en) * 2003-09-26 2006-10-31 Tessera, Inc. Structure and method of making capped chips including vertical interconnects having stud bumps engaged to surfaces of said caps
KR20050040589A (ko) * 2003-10-29 2005-05-03 삼성전기주식회사 광도파로가 형성된 인쇄회로 기판 및 그 제조 방법
US7335972B2 (en) * 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
KR100604334B1 (ko) * 2003-11-25 2006-08-08 (주)케이나인 플립칩 패키징 공정에서 접합력이 향상된 플립칩 접합 방법
US20050139984A1 (en) * 2003-12-19 2005-06-30 Tessera, Inc. Package element and packaged chip having severable electrically conductive ties
US7476955B2 (en) * 2004-01-06 2009-01-13 Micron Technology, Inc. Die package having an adhesive flow restriction area
CN1943031A (zh) * 2004-04-16 2007-04-04 皇家飞利浦电子股份有限公司 集成电路、制造该集成电路的方法与组件以及具有该集成电路的移动电话
US7061099B2 (en) * 2004-09-30 2006-06-13 Intel Corporation Microelectronic package having chamber sealed by material including one or more intermetallic compounds
US7198725B2 (en) * 2004-11-05 2007-04-03 Chi-Yen Shen Method for making a surface acoustic wave device package
US7202560B2 (en) * 2004-12-15 2007-04-10 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Wafer bonding of micro-electro mechanical systems to active circuitry
US7169649B2 (en) * 2004-12-16 2007-01-30 Palo Alto Research Center, Inc. Wafer scale integration of electroplated 3D structures using successive lithography, electroplated sacrificial layers, and flip-chip bonding
US7166917B2 (en) * 2005-01-05 2007-01-23 Advanced Semiconductor Engineering Inc. Semiconductor package having passive component disposed between semiconductor device and substrate
JP2006211612A (ja) 2005-01-31 2006-08-10 Sony Corp Ｓａｗデバイス、通信モジュール及びｓａｗデバイスの製造方法
JP2006237406A (ja) * 2005-02-25 2006-09-07 Toshiba Corp 樹脂封止型電子部品装置
US20060211233A1 (en) * 2005-03-21 2006-09-21 Skyworks Solutions, Inc. Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure
US7154320B2 (en) * 2005-03-29 2006-12-26 Intel Corporation Frequency-based slope-adjustment circuit
US7576426B2 (en) * 2005-04-01 2009-08-18 Skyworks Solutions, Inc. Wafer level package including a device wafer integrated with a passive component
US7323675B2 (en) * 2005-09-21 2008-01-29 Sigurd Microelectronics Corp. Packaging structure of a light-sensing device with a spacer wall
US7576955B1 (en) * 2005-12-06 2009-08-18 Western Digital Technologies, Inc. Disk drive actuator with outer arms having regions of reduced width and increased thickness
US20070235217A1 (en) 2006-03-29 2007-10-11 Workman Derek B Devices with microjetted polymer standoffs
US7635606B2 (en) 2006-08-02 2009-12-22 Skyworks Solutions, Inc. Wafer level package with cavities for active devices
US20080217708A1 (en) * 2007-03-09 2008-09-11 Skyworks Solutions, Inc. Integrated passive cap in a system-in-package
US8324728B2 (en) * 2007-11-30 2012-12-04 Skyworks Solutions, Inc. Wafer level packaging using flip chip mounting

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103420323A (zh) * 2012-04-25 2013-12-04 罗伯特·博世有限公司 微机械元件和微机械元件的制造方法
CN106816420A (zh) * 2015-11-30 2017-06-09 讯芯电子科技（中山）有限公司 一种声波元件封装结构及其制造方法
CN106946216A (zh) * 2016-01-07 2017-07-14 中芯国际集成电路制造(上海)有限公司 一种mems器件及其制备方法、电子装置
CN106946216B (zh) * 2016-01-07 2019-09-27 中芯国际集成电路制造(上海)有限公司 一种mems器件及其制备方法、电子装置
CN105668502A (zh) * 2016-03-24 2016-06-15 美新半导体（无锡）有限公司 一种带腔体器件的气密封装结构及其制造方法
CN108512523A (zh) * 2017-11-06 2018-09-07 贵州中科汉天下微电子有限公司 压电声波器件的封装方法及封装结构
CN111003682A (zh) * 2018-10-08 2020-04-14 凤凰先驱股份有限公司 电子封装件及其制法
CN113889445A (zh) * 2020-07-02 2022-01-04 江苏中科智芯集成科技有限公司 一种晶圆级芯片封装结构及封装方法
CN113200510A (zh) * 2021-04-29 2021-08-03 日月光半导体制造股份有限公司 半导体结构

Also Published As

Publication number Publication date
US9153551B2 (en) 2015-10-06
KR20100119858A (ko) 2010-11-11
CN101978483B (zh) 2014-07-16
EP2235747A1 (en) 2010-10-06
US8900931B2 (en) 2014-12-02
KR101581971B1 (ko) 2015-12-31
HK1150470A1 (zh) 2011-12-30
WO2009085409A1 (en) 2009-07-09
US20150061125A1 (en) 2015-03-05
EP2235747B1 (en) 2018-05-09
EP2235747A4 (en) 2013-07-03
US20100283144A1 (en) 2010-11-11

Similar Documents

Publication Publication Date Title
CN101978483B (zh) 原位空腔集成电路块
CN102810507B (zh) 半导体器件和使用引线框本体形成开口的方法
US6239496B1 (en) Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same
CN102194711B (zh) 半导体器件和在fo-wlcsp中形成ipd的方法
CN102237281B (zh) 半导体器件及其制造方法
US6624511B2 (en) Hybrid integrated circuit device
TWI469233B (zh) 具有中空封裝件之封裝系統
US20030038355A1 (en) Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer
US20030001281A1 (en) Stacked chip package having upper chip provided with trenches and method of manufacturing the same
CN101018044A (zh) 多带滤波器模块以及制造该模块的方法
JP2009500820A (ja) アセンブリを製造する方法及びアセンブリ
KR20020018929A (ko) 회로 장치 및 그 제조 방법
US20070015338A1 (en) Substrate applicable to both wire bonding and flip chip bonding, smart card modules having the substrate and methods for fabricating the same
CN114823651B (zh) 一种带有滤波器的射频系统模块封装结构及方法
KR100800475B1 (ko) 적층형 반도체 패키지 및 그 제조방법
EP1929519A2 (en) Pakaged electronic devices and process of manufacturing same
CN101150886A (zh) 微机电麦克风的封装结构及封装方法
US20080237824A1 (en) Stacked electronic component package having single-sided film spacer
CN105897219A (zh) 圆片级表面声滤波芯片封装结构及其制造方法
WO2003030260A1 (fr) Dispositif de semi-conducteur et son procede de production
JP2003508832A (ja) スマートカードモジュールおよびスマートカードモジュールを含むスマートカード、ならびにスマートカードモジュールを製造するための方法
CN205609474U (zh) 金属圆片埋孔型表面声滤波芯片封装结构
JP3668090B2 (ja) 実装基板およびそれを用いた回路モジュール
CN114361051A (zh) 一种多芯片正装重置晶圆级封装结构及方法
CN105846038A (zh) 金属圆片级蚀刻型表面声滤波芯片封装结构的制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1150470

Country of ref document: HK

C14 Grant of patent or utility model
GR01 Patent grant
REG Reference to a national code

Ref country code: HK

Ref legal event code: GR

Ref document number: 1150470

Country of ref document: HK