CN101958701B - Power off delay circuit and method - Google Patents

Abstract

A power-off delay circuit, characterized in that it includes: an external power input terminal; an internal power supply terminal; a capacitor connected to the internal power supply terminal; a switch connected between the external power input terminal and the internal power supply terminal; a hysteresis comparator having a first input terminal connected to the external power input terminal, a second input terminal connected to the internal power supply terminal, and an output terminal generating a control signal to control the switch; wherein the switch is opened in a first state to connect the external power input terminal to the internal power supply terminal, and is closed in a second state.

Description

Power off delay circuit and method

technical field

The invention relates to a power-off delay circuit and method, in particular to a power-off delay circuit and method for an audio system. the

Background technique

To prevent the speaker from popping when the audio system is turned on and off, it is known to use an audio mute integrated circuit (IC) to eliminate the pop. However, when the power is turned off, the audio muting IC lacks a large enough power supply voltage to support its internal circuits to operate correctly, so it is difficult to maintain its muting function. In order to solve this problem, it is necessary to prolong the maintenance time of the power supply voltage of the audio noise canceling IC when the power is turned off, so that the internal circuit can still work normally for a period of time after the power is turned off, so that the function of muting the audio source can take effect, and the output of the audio system The voltage signal remains correct for a period of time after the power is turned off. the

U.S. Patent No. 5,778,238 discloses a power-off restart circuit for a microcontroller, which connects a P-N junction diode to an external power source to charge a capacitor, which provides the required voltage for the operation of the low-voltage detection circuit when the power is off. Energy, the MOSFET transistor is turned on and the charge of the delay capacitor at the input end of the power restart circuit is released, so as to avoid shortening the delay time when restarting due to the incomplete discharge of the delay capacitor during the previous shutdown. However, the connection of the diode between the external power supply and the internal circuit will consume an additional voltage drop, resulting in a smaller marginal value of the internal circuit operating voltage, and the output voltage of the diode will also fluctuate with the external power supply voltage. the

Therefore, there are above-mentioned inconveniences and problems in the known power-off restart circuit for microcontrollers. the

Contents of the invention

The object of the present invention is to propose a power-off delay circuit and method for an audio system. the

Another object of the present invention is to provide an audio system with power-off delay. the

For realizing the above object, technical solution of the present invention is:

A power-off delay circuit is characterized in that it comprises:

An external power input terminal;

an internal power supply;

A capacitor connected to the internal power supply end;

A switch is connected between the external power input terminal and the internal power supply terminal;

A hysteresis comparator has a first input terminal connected to the external power supply input terminal, a second input terminal connected to the internal power supply terminal, and an output terminal that generates a control signal to control the switch;

Wherein, the switch is opened in a first state to connect the external power input terminal to the internal power supply terminal, and is closed in a second state. the

The power-off delay circuit of the present invention can also be further realized by adopting the following technical measures. the

In the aforementioned power-off delay circuit, the switch includes a MOS transistor connected between the external power supply input terminal and the internal power supply terminal, and is controlled by the control signal. the

The aforementioned power-off delay circuit, wherein the switch includes:

A first PMOS transistor is connected between the external power supply input terminal and the internal power supply terminal, and is controlled by the control signal;

A voltage switching circuit is connected to the base of the first PMOS transistor to switch its voltage. the

The aforementioned power-off delay circuit, wherein the voltage switching circuit includes:

A second PMOS transistor is connected between the external power supply input terminal and the substrate of the first PMOS transistor, and the voltage of the external power supply input terminal is applied to the substrate of the first PMOS transistor in the first state ;

A resistor is connected between the internal power supply terminal and the base of the first PMOS transistor, and applies the voltage of the internal power supply terminal to the base of the first PMOS transistor in the second state. the

In the aforementioned power-off delay circuit, wherein the resistance includes a substrate resistance of the first PMOS transistor. the

In the aforementioned power-off delay circuit, the hysteresis comparator includes an initial state setting resistor connected to the output terminal of the hysteresis comparator to set the initial logic state of the control signal. the

The aforementioned power-off delay circuit, wherein the hysteresis comparator includes:

first and second input transistors, the first input transistor has a gate connected to the external power supply input terminal;

A hysteresis resistor is connected between the second input terminal and the gate of the second input transistor;

The hysteresis current source is connected in series with the hysteresis resistance;

Wherein, the hysteresis resistor generates a voltage drop to determine the hysteresis of the hysteresis comparator. the

In the aforementioned power-off delay circuit, the capacitance value of the capacitor defines the delay time of the power-off delay circuit. the

A kind of power-off delay method is characterized in that comprising the following steps:

(A) Monitor the voltage at the input terminal of the external power supply and the voltage at the supply terminal of the internal power supply;

(B) hysteresis control to connect or not connect the external power supply input terminal to the internal power supply terminal according to the voltage of the external power supply input terminal and the voltage of the internal power supply terminal;

(C) charging a capacitor while the external power supply input terminal is connected to the internal power supply terminal. the

The power-off delay method of the present invention can also be further realized by adopting the following technical measures. the

In the aforementioned power-off delay method, the step A includes comparing the voltage at the input terminal of the external power supply with the voltage at the supply terminal of the internal power supply. the

In the aforementioned power-off delay method, the step B includes turning on a MOS transistor to connect the external power supply input terminal to the internal power supply terminal. the

Aforesaid power-off delay method, wherein said step B comprises:

Turn on the PMOS transistor and connect the external power supply input terminal to the internal power supply terminal;

The voltage of the external power input terminal is applied to the base of the PMOS transistor. the

Aforesaid power-off delay method, wherein said step B comprises:

Turn off the PMOS transistor and cut off the connection between the external power supply input terminal and the internal power supply terminal;

The voltage of the internal power supply terminal is applied to the base of the PMOS transistor. the

The aforementioned power-off delay method further includes setting an initial state such that the external power input terminal is connected to the internal power supply terminal. the

A sound system, characterized in that it comprises:

a sound source line;

A drive transistor connected to the audio source line;

A power-off delay circuit, connected to the drive transistor, the power-off delay circuit has an external power supply input terminal, an internal power supply terminal and a capacitor connected to the internal power supply terminal, and the voltage at the internal power supply terminal is lower than the The voltage at the input terminal of the external power supply charges the capacitor, and when the power is off, the capacitor supplies current to the driving transistor to pull down the potential of the audio source line. the

The aforementioned audio system, wherein the power-off delay circuit includes:

A switch is connected between the external power input terminal and the internal power supply terminal;

A hysteresis comparator has a first input terminal connected to the external power supply input terminal, a second input terminal connected to the internal power supply terminal, and an output terminal that generates a control signal to control the switch;

Wherein, the switch is opened in a first state to connect the external power input terminal to the internal power supply terminal, and is closed in a second state. the

In the aforementioned power-off delay circuit, wherein the switch includes a MOS transistor connected between the external power input terminal and the internal power supply terminal, and is controlled by the control signal. the

The aforementioned power-off delay circuit, wherein the switch includes:

The first PMOS transistor is connected between the external power supply input terminal and the internal power supply terminal, and is controlled by the control signal;

A voltage switching circuit is connected to the base of the first PMOS transistor to switch its voltage. the

The aforementioned power-off delay circuit, wherein the voltage switching circuit includes:

The second PMOS transistor is connected between the external power supply input terminal and the substrate of the first PMOS transistor, and the voltage of the external power supply input terminal is applied to the substrate of the first PMOS transistor in the first state;

A resistor is connected between the internal power supply terminal and the base of the first PMOS transistor, and the voltage of the internal power supply terminal is applied to the base of the first PMOS transistor in the second state. the

In the aforementioned power-off delay circuit, wherein the resistance includes a substrate resistance of the first PMOS transistor. the

In the aforementioned power-off delay circuit, the hysteresis comparator includes an initial state setting resistor connected to the output terminal of the hysteresis comparator to set the initial logic state of the control signal. the

The aforementioned power-off delay circuit, wherein the hysteresis comparator includes:

first and second input transistors, the first input transistor has a gate connected to the external power supply input terminal;

A hysteresis resistor is connected between the second input terminal and the gate of the second input transistor;

The hysteresis current source is connected in series with the hysteresis resistance;

Wherein, the hysteresis resistor generates a voltage drop to determine the hysteresis of the hysteresis comparator. the

In the aforementioned power-off delay circuit, the capacitance value of the capacitor defines the delay time of the power-off delay circuit. the

After adopting the above technical solution, the power-off delay circuit and method of the present invention, and the audio system with power-off delay have the advantage of eliminating popping sounds when the audio system is turned on and off. the

Description of drawings

Fig. 1 is the sound system block diagram of application power-off delay circuit of the present invention;

Fig. 2 is a schematic diagram of an embodiment of the power-off delay circuit of the present invention;

Fig. 3 realizes the switch 16 with diode, NMOS or PMOS, the relationship diagram between the voltage difference ΔV and the electric current lost on the switch 16;

Fig. 4 is the circuit diagram of another embodiment of the present invention;

FIG. 5 is a graph of the external power supply voltage V _CC and the internal power supply voltage V _DD of FIG. 4;

FIG. 6 is a graph comparing the curves of the external power supply voltage V _CC and the internal power supply voltage V _DD .

Detailed ways

The present invention will be further described below in conjunction with embodiment and accompanying drawing. the

Please refer to FIG. 1 now. FIG. 1 is a schematic diagram of a power-off delay circuit used in an audio system. As shown in the figure, a reset IC 10 is connected to an external power supply V _CC , an external capacitor C and a plurality of driving transistors M1 - MN, and each driving transistor is connected to a speaker 12 via an audio line 11 . When the restart IC 10 detects that the external power supply voltage V _CC is abnormal, for example, when the power is turned off, the charge stored in the capacitor C provides the load current I_load to the driving transistors M1-MN, thereby pulling the voltage of the audio source line 11 to 0 volts or more. Avoid popping sounds. The power-off delay circuit according to the present invention is integrated in the restart IC 10, which delays the time when the internal power supply of the restart IC 10 is powered off, so that the restart IC 10 can maintain a sufficient load for a period of time after the external power supply V _CC is powered off. Current I_load. As shown in Figure 2, the power-off delay circuit 14 includes a capacitor C connected to the internal power supply terminal V _DD , a switch 16 connected between the external power supply input terminal V _CC and the internal power supply terminal V _DD , and a hysteresis comparator 18 according to the external The power supply voltage V _CC and the internal power supply voltage V _DD control the switch 16 . The first input terminal of the hysteresis comparator 18 is connected to the external power input terminal V _CC , the second input terminal is connected to the internal power supply terminal V _DD , and the output terminal generates a control signal S1 to control the switch 16 . In the first state, the switch 16 is turned on to connect the external power input terminal V _CC to the internal power supply terminal V _DD , so the external power V _CC can charge the capacitor C. In the second state, the switch 16 is turned off to cut off the connection between the external power input terminal V _CC and the internal power supply terminal V _DD , and the capacitor C provides the power required for the operation of the internal circuit 20 . By hysteresis controlling the connection or non-connection of the external power input terminal V _CC to the internal power supply terminal V _DD , a stable internal power supply voltage V _DD can be maintained. The capacitance of the capacitor C defines the delay time of the power-off delay circuit 14 , that is, the time for the power-off delay circuit 14 to support the correct operation of the internal circuit 20 . In this embodiment, the capacitor C is set outside the restart IC 10 in order to adjust the size of the capacitor C to optimize the delay time. In other embodiments, the capacitor C can also be set outside the restart IC 10 according to system requirements. internal.

FIG. 3 is a schematic diagram of an embodiment of the switch 16 and the hysteresis comparator 18 . Here, the switch 16 includes a PMOS transistor P1 connected between the external power supply input terminal V _CC and the internal power supply terminal V _DD , controlled by the control signal S1, and the PMOS transistor P2 and the resistor R _WELL form a voltage switching circuit connected to the external power supply input Between terminal V _CC and internal power supply terminal V _DD . The PMOS transistor P2 is connected between the external power input terminal V _CC and the base of the PMOS transistor P1 , and the resistor R _WELL is connected between the internal power supply terminal V _DD and the base of the PMOS transistor P1 . The switch 16 is realized by using the PMOS transistor P1 in order to reduce the voltage drop on the switch 16 as much as possible. The PMOS transistor P2 and the resistor R _WELL are a switching well structure, which is used to connect the well region of the PMOS transistor P1 to the highest potential to improve the ability to prevent latch up. In this embodiment, the PMOS transistor P1 is used to define the voltage drop between the external power supply input terminal V _CC and the internal power supply terminal V _DD when the switch 16 is turned on, and the PMOS transistor P2 and the resistor R _WELL are used to switch the N-type well The potential of the N-type well can be connected to different sides according to the voltages V _CC and V _DD at both ends of the switch 16 . When the external power supply voltage V _CC is higher than the internal power supply voltage V _DD , the hysteresis comparator 18 turns on the PMOS transistors P1 and P2, and the N-type well is connected to the external power supply V _CC through the PMOS transistor P2, so the base of the PMOS transistor P1 (i.e. N-type well) is connected to the high potential terminal V _CC . When the external power supply voltage V _CC is lower than the internal power supply voltage V _DD , the PMOS transistors P1 and P2 are turned off by the hysteresis comparator 18, so the parasitic resistance R _WELL connects the base of the PMOS transistor P1 to the high potential terminal V _DD . By switching the potential of the N-well, the PMOS transistor P1 operates as a switch element. Fig. 4 is the schematic diagram that compares the effect of the present invention and known technology, and the ΔV of horizontal axis represents the voltage drop of switch 16, and the vertical axis represents the electric current of switch 16, and curve 22 is the current-voltage characteristic curve of PMOS transistor P1, and curve 24 is The current-voltage characteristic curve of a diode. Using the PMOS transistor P1 as a switch component, the loss voltage difference ΔV is about 0.1V, which is smaller than the conduction voltage drop V _DIODE (about 0.6V) of the diode, thus reducing the external power input terminal V _CC and the internal power supply terminal The voltage drop between V _DD , the internal power supply voltage V _DD (=V _CC -ΔV) is higher than the internal power supply voltage (=V _CC -V _DIODE ) using a diode, thereby increasing the operating voltage of the internal circuit 20 by a margin of about 0.5V. On the other hand, the rising slope of curve 22

Slope=1/Ron, [Formula 1]

where Ron is the on-resistance value of the PMOS transistor P1. Increasing the size of the PMOS transistor P1 can reduce its on-resistance Ron, thereby increasing the rising slope Slope of the curve 22 . the

Returning to Fig. 3, the hysteresis comparator 18 has a pair of input transistors M1 and M2, the gate of the input transistor M1 is connected to the external power supply input terminal V _CC , the bias current source I _BIAS is connected to the input transistors M1 and M2, and the hysteresis resistor P _HYS is connected between the second input terminal of the hysteresis comparator 18 and the gate of the input transistor M2. The hysteresis current source I _HYS is connected in series with the resistor R _HYS to provide current to flow through the resistor R _HYS to generate a voltage drop, which determines the magnetic The hysteresis size ΔH of the hysteresis comparator 18. Preferably, the initial state setting resistor R _INI is connected to the output terminal of the hysteresis comparator 18 , and its output signal S1 is preset at a logic low level, so that the default state of the PMOS transistor P1 is turned on. Referring to FIG. 5 , the waveform 26 represents the external power supply voltage V _CC , the waveform 28 represents the internal power supply voltage V _DD , and the level 30 represents the standby power of the external power supply V _CC , generally 3.3V or 5V. After the power is turned on, the external power supply voltage V _CC rises from 0 to the rated value. During this period, because the switch 16 is turned on, the internal supply voltage V _DD also rises accordingly. Due to the hysteresis characteristic of the hysteresis comparator 18, the switch 16 is closed at a later time t1 until the internal power supply voltage V _DD drops below the threshold value, such as time t2, the hysteresis comparator 18 opens the switch 16 again, so the external The power supply V _CC charges the capacitor C to pull up the internal power supply voltage V _DD . At time t3, the switch 16 is closed by the hysteresis comparator 18 again, so the internal power supply voltage V _DD starts to drop again. When the external power supply voltage V _CC drops below the standby level 30, the falling slope of the internal power supply voltage V _DD is determined by the capacitance value of the capacitor C as follows

R _SW = falling slope of V _CC (V/s), [Equation 2]

C>I_load/R _SW . [Formula 3]

For example, if the load current I_load is 5mA, R _SW =5V/1ms=5K(V/s), then

C>5mA/5KV/s=1μF. the

If the load current I_load is 20mA, R _SW ＝5V/10ms＝0.5K(V/s), then

C>20mA/0.5KV/s=40μF. the

As shown in section 32 in FIG. 5 , when the capacitance of the capacitor C is larger, the falling slope of the internal power supply voltage V _DD becomes gentler.

Referring to Figure 6, after the power is turned on, when the external power supply voltage V _CC rises to the cut-in voltage Vr of the PMOS transistor P1, the PMOS transistor P1 is turned on, so the internal power supply voltage V _DD jumps up to about 0.1 volts lower than the external power supply voltage V _CC , and then rises with the external power supply voltage V _CC . After the external power supply voltage V _CC reaches the rated value, because of hysteresis, the internal power supply voltage V _DD reaches the value of V _CC later. Thereafter, the internal power supply voltage V _DD is maintained near V _CC by the hysteresis comparator 18 , and the magnitude of its ripple depends on the magnitude of the hysteresis ΔH. During this period, the switch 16 is switched repeatedly by the control signal S1 , and the time T of each closing depends on the load I_load and the hysteresis ΔH. Selecting an appropriate hysteresis value ΔH can reduce the switching frequency of the switch 16 and reduce switching power loss.

The above embodiments are only for illustrating the present invention, rather than limiting the present invention. Those skilled in the relevant technical field can also make various transformations or changes without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions should also be described as belonging to the category of the present invention and should be defined by each claim. the

Claims (10)

1. a power-off delay circuit, is characterized in that comprising:

One external power source input;

One internal electric source feed end;

One electric capacity connects described internal electric source feed end;

One switch is connected between described external power source input and described internal electric source feed end;

One hysteresis comparator has that first input end connects described external power source input, the second input connects described internal electric source feed end, and switch described in the control of output generation control signal, the voltage of the more described external power source input of described hysteresis comparator and the voltage of described internal electric source feed end produce described control signal;

Wherein, described switch is opened and is connected described external power source input to described internal electric source feed end under the first state, and closes under the second state;

Wherein, described switch comprises:

One the one PMOS transistor is connected between described external power source input and described internal electric source feed end, is subject to the control of described control signal;

One voltage commutation circuit connects the transistorized substrate of a described PMOS, to switch its voltage.

2. power-off delay circuit as claimed in claim 1, is characterized in that, described voltage commutation circuit comprises:

One the 2nd PMOS transistor is connected between described external power source input and the transistorized substrate of a described PMOS, the voltage of described external power source input is applied to the transistorized substrate of a described PMOS under described the first state;

One resistance is connected between described internal electric source feed end and the transistorized substrate of a described PMOS, the voltage of described internal electric source feed end is applied to the transistorized substrate of a described PMOS under described the second state.

3. power-off delay circuit as claimed in claim 2, is characterized in that, described resistance comprises the transistorized substrate resistance of a described PMOS.

4. power-off delay circuit as claimed in claim 1, is characterized in that, described hysteresis comparator comprises that initial state setting resistance connects the output of described hysteresis comparator, sets the initial logic state of described control signal.

5. power-off delay circuit as claimed in claim 1, is characterized in that, described hysteresis comparator comprises:

First and second input transistors, described the first input transistors has gate and connects described external power source input;

Magnetic hysteresis is connected to resistance between the gate of described the second input and described the second input transistors;

The source-series described magnetic hysteresis resistance of electric current for magnetic hysteresis;

Wherein, described magnetic hysteresis produces pressure drop to determine the magnetic hysteresis size of described hysteresis comparator with resistance.

6. power-off delay circuit as claimed in claim 1, is characterized in that, the capacitance of described electric capacity defines the time of delay of described power-off delay circuit.

7. a power-off delay method, is characterized in that comprising the following steps:

(A) monitor the voltage of external power source input and the voltage of internal electric source feed end;

(B) according to the voltage magnetic hysteresis of the voltage of described external power source input and described internal electric source feed end control and described external power source input connected or be free of attachment to described internal electric source feed end;

(C) during described external power source input is connected to described internal electric source feed end, to capacitor charging;

Wherein, described steps A comprises the voltage of more described external power source input and the voltage of described internal electric source feed end;

Wherein, described step B comprises:

Open PMOS transistor and described external power source input is connected to described internal electric source feed end;

The voltage of described external power source input is applied to the transistorized substrate of described PMOS.

8. a power-off delay method, is characterized in that comprising the following steps:

(A) monitor the voltage of external power source input and the voltage of internal electric source feed end;

(B) according to the voltage magnetic hysteresis of the voltage of described external power source input and described internal electric source feed end control and described external power source input connected or be free of attachment to described internal electric source feed end;

(C) during described external power source input is connected to described internal electric source feed end, to capacitor charging;

Wherein, described steps A comprises the voltage of more described external power source input and the voltage of described internal electric source feed end;

Wherein, described step B comprises:

Close PMOS transistor and cut off being connected between described external power source input and described internal electric source feed end;

The voltage of described internal electric source feed end is applied to the transistorized substrate of described PMOS.

9. power-off delay method as claimed in claim 7, is characterized in that, more comprises that setting initial state makes described external power source input be connected to described internal electric source feed end.

10. power-off delay method as claimed in claim 8, is characterized in that, more comprises that setting initial state makes described external power source input be connected to described internal electric source feed end.