CN101943811B - flat panel display - Google Patents

Abstract

A flat display panel includes a thin film transistor array substrate, a filter substrate disposed opposite to the thin film transistor array substrate. The first electrodes and the second electrodes are arranged on the thin film transistor array substrate, the first electrodes receive a plurality of scanning signals from a driving circuit, and each second electrode is connected with a corresponding scanning line. A plurality of signal lines are formed on the filter substrate and are arranged in the display area. The plurality of third electrodes and the plurality of fourth electrodes are arranged on the filter substrate, wherein each third electrode is electrically connected with the corresponding first electrode and a corresponding signal line, and each fourth electrode is electrically connected with the corresponding second electrode and a corresponding signal line.

Description

flat panel display

technical field

The invention relates to a flat display panel, in particular to a flat display panel with a narrow frontal margin.

Background technique

Please refer to FIG. 1 , which shows a schematic top view of a conventional flat display panel. The figure shows that the liquid crystal display panel 10 includes a thin film transistor array substrate (TFT array substrate) 102 and a color filter substrate (color filter substrate) 104 stacked on the thin film transistor array substrate 102 . The thin film transistor array substrate 102 is provided with a plurality of scanning lines 106 arranged in the horizontal direction and data lines (not shown) arranged in the vertical direction. The scanning lines 106 intersect with the data lines and define a display area (ActiveArea, AA )112. Each scanning line 106 is connected to a driving circuit 110 by a wire 108 to receive a scanning signal from the driving circuit 110 .

For example, for a liquid crystal display panel conforming to the Video Graphics Array (VGA) standard, its resolution is 640*480. If designed according to this standard, the wires 108 are usually arranged on both sides of the liquid crystal display panel 10 , and each side has 320 wires 108 . Assuming that the line width of each wire 108 is 2.5 μm and the distance between two adjacent wires 108 is 3 μm, the total width of 320 wires 108 is 2.5*320+3*319=1757 μm=1.757 mm (cm). Based on this calculation, the width W of the frontal margin needs to be about 2mm to be sufficient. In other words, a total width of 4 mm needs to be reserved on both sides of the liquid crystal display panel 10 for laying the wires 108 and other circuits, which will reduce the area of the display area 102 .

Contents of the invention

Embodiments of the invention provide a flat panel display panel that effectively reduces the width of the frontal edge.

According to the design of an embodiment of the present invention, a flat display panel includes a thin film transistor array substrate and a filter substrate oppositely arranged. A plurality of scan lines arranged along a first direction and a plurality of data lines arranged along a second direction are formed on the thin film transistor array substrate. A plurality of first electrodes and a second electrode are arranged on the thin film transistor array substrate, the first electrodes receive a plurality of scanning signals from a driving circuit, and each second electrode is connected to a corresponding scanning line. A plurality of signal lines are formed on the filter substrate, and these signal lines are arranged in the display area (active area, AA). A plurality of third electrodes and fourth electrodes are disposed on the filter substrate, wherein each third electrode is electrically connected to a corresponding first electrode and a corresponding signal line, and each fourth electrode is electrically connected to a corresponding second electrode. electrodes and a corresponding signal line.

In one embodiment, the filter substrate has a black matrix, the black matrix is made of conductive material, and the signal line connecting the third electrode and the fourth electrode is composed of part of the black matrix. The material of the black matrix can be chromium (Cr) or chromium oxide (CrO) or a material doped with black in metal. At this time, each signal line has two line segments arranged along the first direction and the second direction.

In one embodiment, the filter substrate has a black matrix, and the black matrix is made of resin. Preferably, the signal lines connecting the third electrode and the fourth electrode are disposed on the surface of the black matrix. At this time, each signal line has two line segments arranged along the first direction and the second direction. In addition, when the signal lines connecting the third electrode and the fourth electrode are transparent electrodes, the signal lines may not be distributed along the surface of the black matrix.

In one embodiment, the first electrode is electrically connected to the third electrode through a conductive spacer, and similarly, the second electrode is electrically connected to the fourth electrode through a conductive spacer. Usually, a sealant is provided between the TFT array substrate and the filter substrate, and the sealant is doped with conductive spacers and covers the first electrode, the second electrode, the third electrode and the fourth electrode.

In one embodiment, the second electrodes may be distributed on both sides of the display area, for example, the left and right sides, and part of the second electrodes are arranged adjacent to the left side, and correspondingly connected to each odd-numbered scanning line. The rest of the second electrodes are disposed adjacent to the right side, and correspondingly connected to the even-numbered scanning lines.

In one embodiment, a liquid crystal layer is disposed between the thin film transistor array substrate and the filter substrate to form a liquid crystal display panel. However, the foregoing embodiments are not limited to liquid crystal display panels, and are also applicable to other display panels having optical filter substrates, such as electrophoretic display (electrophoresis display, EPD) panels, electrowetting display (electrowetting display, EWD) panels, organic light emitting Diode panel (OLED).

Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention. In order to make the above and other objects, features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic top view of a conventional flat display panel.

FIG. 2 is a schematic top view of a flat panel display panel according to an embodiment of the invention.

FIG. 3 is an enlarged schematic diagram of a part of the thin film transistor array substrate according to FIG. 2 .

FIG. 4 is an enlarged schematic diagram of a partial area of the filter substrate according to FIG. 2 .

FIG. 5 is a schematic cross-sectional view along the line A-A of FIG. 3 and the line B-B of FIG. 4 .

FIG. 6 is a schematic top view of a flat panel display panel according to another embodiment of the present invention.

Symbol Description

10, 20, 30 flat panel display panels 102, 202, 302 thin film transistor array substrates

104, 204, 304 filter substrates 106, 206 scanning lines

108, 216 wires 110, 210, 303 drive circuits

112 display area AA 114, 220 frame glue

201, 203 transparent substrate 207, 209 insulating layer

205 black matrix 208 data line

211 conductive spacer 212, 306 first electrode

213, 308 second electrode 214, 310 third electrode

215, 312 fourth electrode 218, 316 signal line

W, W' frontal edge width

Detailed ways

Please refer to FIG. 2 , which is a schematic top view of a flat panel display panel according to an embodiment of the present invention. The flat panel display 20 includes a TFT array substrate 202 and a filter substrate 204 oppositely disposed. A liquid crystal display panel is formed when a liquid crystal layer is arranged between the thin film transistor array substrate and the filter substrate. However, the present invention can also be applied to other display panels that have a filter substrate but do not include a liquid crystal layer, such as electrophoretic display (EPD) panels, electrowetting display (EWD) panels, organic light emitting diode panels (OLED), etc. It is not limited here. For the convenience of description, the following embodiments are all described by taking a liquid crystal display panel as an example.

A plurality of scan lines 206 arranged along a first direction and a plurality of data lines 208 arranged along a second direction are formed on the TFT array substrate 202 . Here, the first direction is the horizontal direction D1 as shown in the figure, and the second direction is the vertical direction D2. Since the thin film transistor array substrate 202 is stacked under the filter substrate 204, the scanning lines 206 and the data lines 208 are all indicated by dotted lines. In addition, a plurality of first electrodes 212 and second electrodes 213 are disposed on the TFT array substrate 202 , and a plurality of third electrodes 214 and fourth electrodes 215 are correspondingly disposed on the filter substrate 204 . Preferably, each first electrode 212 is set corresponding to a third electrode 214 , and each second electrode 213 is set corresponding to a fourth electrode 215 . Wherein, the first electrode 212 is connected to the corresponding third electrode 214 , and the second electrode 213 is also connected to the corresponding fourth electrode 215 . There are many ways of conduction, for example, two electrodes can be conducted with each other through a conductive spacer, which will be described in detail later. A driving circuit 210 is disposed adjacent to the second electrode 212 , so that an output signal of the driving circuit 210 can be connected to the first electrode 212 through a wire 216 as a scanning signal. Since the two ends of each signal line 218 are connected to a third electrode 214 and a fourth electrode 215, each scan signal output by the drive circuit 210 will pass through the wire 216, the thin film transistor array substrate 202 in sequence The first electrode 212 on the filter substrate 204, the third electrode 214 on the filter substrate 204, the signal line 218, the fourth electrode 215 on the filter substrate 204, the second electrode 213 on the thin film transistor array substrate 202, and finally input to each scan line 206 to drive the pixel switch in the display area (active area, AA). In addition, the driving circuit 210 can be a driving chip (chip) or a circuit formed by a system on glass (SOG) process, such as a circuit formed by low temperature polysilicon (LTPS), microcrystalline silicon (Micro-C), non Crystalline silicon (a-Si) and other processes directly form the driving circuit on the glass.

In this embodiment, the signal line 218 transmitting the scanning signal is laid on the filter substrate 204 , so it is different from the wiring 108 shown in FIG. 1 . Since the signal line 218 does not connect to the scan line 206 in the display area AA via the frontal area on the side of the display area AA, the width W' of the frontal area is significantly reduced. In other words, only the second electrode 213 and other lines are provided in the frontal margin area of this embodiment, but no wires connecting the driving circuit and the scanning line are arranged, so the effect of narrow frontal margin can be achieved. Taking a panel with a resolution of 640*480 as an example, compared to the total frontal edge width 2W on both sides of the panel shown in Figure 1 is 4mm, the total frontal edge width 2W' on both sides of the present embodiment can be reduced to within 1.2mm or Even smaller, the reduction of the frontal edge is as high as 70%.

Please refer to FIGS. 3 to 5 at the same time, wherein, FIG. 3 is an enlarged schematic diagram of a part of the thin film transistor array substrate according to FIG. Figure 3A-A line and a schematic cross-sectional view along Figure 4B-B line.

In FIG. 3 , a first electrode 212 is disposed on the right edge of the TFT array substrate 202 , and a second electrode 213 is disposed below the display area AA near the drive circuit 210 . The first electrode 212 is connected to the wire 216 , and the second electrode 213 is connected to the scan line 206 . Wherein, the material of the first electrode 212 and the second electrode 213 may be metal, indium tin oxide (ITO), indium zinc oxide (IZO) or a combination of the above materials.

FIG. 4 shows that a black matrix 205 is disposed on the filter substrate 204 . The black matrix 205 is a conductive material or a tree finger material. In this embodiment, the black matrix 205 is an example of a conductive material, such as chromium (Cr) or chromium oxide (CrO). When the black matrix 205 is made of conductive material, a part of the black matrix 205 can be directly used as the signal line 218 connecting the third electrode 214 and the fourth electrode 215 . At this time, the part of the black matrix 205 which is regarded as the signal line 218 is properly designed to avoid short circuit between two adjacent signal lines 218 . Since the black matrix 205 is used as the signal line 218 , each signal line 218 has two line segments extending along the vertical direction D2 and the horizontal direction D1 to form an approximate L shape. The third electrodes 214 are arranged corresponding to the positions of the first electrodes 212 , preferably, one third electrode 214 is arranged corresponding to one first electrode 212 . Likewise, each fourth electrode 215 is also arranged corresponding to the position of one second electrode 213 . The material of the third electrode 214 and the fourth electrode 215 can be metal, indium tin oxide (ITO), indium zinc oxide (IZO) or a combination of the above materials.

FIG. 5 shows a schematic cross-sectional view of the thin film transistor array substrate 202 and the filter substrate 204 , and a liquid crystal layer 222 is disposed between the thin film transistor array substrate 202 and the filter substrate 204 . The TFT array substrate 202 includes a transparent substrate 201 , a patterned metal layer (wires 206 and scan lines 216 ), an insulating layer 203 , a first electrode 212 and a second electrode 213 . The filter substrate 204 includes a transparent substrate 203 , a black matrix 205 , an insulating layer 209 , a third electrode 214 and a fourth electrode 215 . As shown in the figure, a plurality of conductive spacers 211 are arranged between the thin film transistor array substrate 202 and the filter substrate 204, so as to connect the first electrode 212 and the third electrode 214, and connect the second electrode 213 and the second electrode 213. the fourth electrode 215 . In this way, each scan signal output by the driving circuit 210 will sequentially pass through the wire 216, the first electrode 212, the conductive spacer 211, the third electrode 214, the signal line 218, the fourth electrode 215, the conductive spacer 211 , the second electrode 213 , and finally input to the corresponding scan line 206 .

In addition, the black matrix 205 may not be made of conductive material. For example, if the black matrix 205 is made of resin, the signal line 218 is arranged between the surface of the black matrix 205 and the insulating layer 209 (not shown), and along the black matrix 205 is laid out to connect the third electrode 214 and the fourth electrode 215 . The technical method of this design is similar to the above-mentioned embodiment, and will not be repeated here.

In addition, a sealant 220 is usually provided between the thin film transistor array substrate 202 and the filter substrate 204 as an insulating layer, and a liquid crystal layer 222 is filled in a space surrounded by the sealant 220 as a display area AA. Wherein, the sealant 220 is doped with conductive spacers 211 and covers the first electrode 212 , the second electrode 213 , the third electrode 214 and the fourth electrode 215 . In practice, the conductive spacers 211 can be doped into the sealant 220 first, and then coated on one of the patterned thin film transistor array substrate 202 or the filter substrate 204, and then the thin film transistor array The substrate 202 and the filter substrate 204 are bonded together and then cured.

In the above-mentioned embodiment, the signal line 218 , the second electrode 213 , and the fourth electrode 215 are collectively arranged on the right side of the flat panel display panel 20 . However, the second electrodes 213 and the fourth electrodes 215 may also be dispersedly disposed on the left and right sides of the flat panel display panel 20 . Please refer to FIG. 6 . FIG. 6 is a schematic top view of a flat panel display panel according to another embodiment of the present invention. Here, the similarities between the flat display panel 30 and the flat display panel 20 of the previous embodiment will not be repeated, and only the differences will be described below.

As shown in the figure, a plurality of first electrodes 306 are arranged under a thin film transistor array substrate 202 and near a driving circuit 303, wherein the first electrode 306a is arranged at the bottom left, and the first electrode 306a is arranged at the bottom right. An electrode 306b. Similarly, the plurality of second electrodes 308 disposed on both sides of the thin film transistor array substrate 202 can be further divided into a second electrode 308 a on the left and a second electrode 308 b on the right. Wherein, the second electrode 308a on the left is connected to an odd number of scanning lines 314a, for example, the 1st, 3rd, 5th... Nth, where N is a positive integer. On the contrary, the second electrode 308b on the right side is connected to an even number of scan lines 314b, for example, the 2nd, 4th, 6th... (N+1)th.

On the other hand, a plurality of third electrodes 310 are disposed under a filter substrate 204 and respectively correspond to the first electrodes 306, wherein the third electrode 310a is disposed on the lower left side, and the third electrode 310a is disposed on the lower right side. 310b. Moreover, a plurality of fourth electrodes 312 a and 312 b corresponding to the second electrodes 308 a and 308 b are also disposed on both sides of the filter substrate 204 . The signal lines 316 formed on the surface of the filter substrate 204 connect the third electrodes 310 and the fourth electrodes 312 in a one-to-one manner. That is, the left signal line 316a is connected to the third electrode 310a and the fourth electrode 312a, and the right signal line 316b is connected to the third electrode 310b and the fourth electrode 312b. Such a design method has its advantages. For example, when the driving circuit 303 consists of at least two driving chips (not shown), the electrodes 306-312 and the signal line 316 can be divided into Two parts for easy layout of lines, suitable for larger size panels.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention shall prevail according to the contents defined in the claims. In addition, any embodiment or protection scope of the present invention does not necessarily achieve all the objects or advantages or features disclosed in the present invention. In addition, the abstract and the title are only used to assist in the search of patent documents, and are not used to limit the protection scope of the present invention.

Claims (8)

1. a flat display panel is characterized in that, comprises:

One membrane transistor multiple substrate has many sweep trace and many data lines of arranging along a second direction of arranging along a first direction, and this first direction and this second direction intersect;

Said sweep trace and said data line intersect and define a viewing area;

A plurality of first electrodes and second electrode; Be located on the lateral margin position, said viewing area between this membrane transistor multiple substrate and the filter sheet base plate; Those first electrodes receive a plurality of sweep signals from least one driving circuit, and those second electrodes connect those sweep traces;

Said filter sheet base plate has many signal line; And

A plurality of conductive gap are arranged between said membrane transistor multiple substrate and the filter sheet base plate;

A plurality of third electrodes and the 4th electrode; Be located on the lateral margin position of viewing area of corresponding said first electrode and said second electrode; Those third electrodes electrically connect those first electrodes and those signal wires through said conductive gap, and those the 4th electrodes electrically connect those second electrodes and those signal wires through said conductive gap;

Wherein, be provided with a frame glue between membrane transistor multiple substrate and this filter sheet base plate, and this frame glue is doped with said conductive gap and covers first electrode, second electrode, third electrode and the 4th electrode.

2. flat display panel according to claim 1 is characterized in that this filter sheet base plate has a black matrix", and this black matrix" is made up of this black matrix" of part by conductive material and those signal wires.

3. flat display panel according to claim 1 is characterized in that this filter sheet base plate has a black matrix", and this black matrix" is the resin material, and those signal wires are arranged on this black matrix".

4. flat display panel according to claim 1; It is characterized in that the material of those first electrodes, those second electrodes, those third electrodes and those the 4th electrodes is the combinations for indium tin oxide, indium-zinc oxide, metal or above-mentioned material.

5. flat display panel according to claim 1 is characterized in that, those signal wires have along two line segments of this first direction and the configuration of this second direction simultaneously.

6. flat display panel according to claim 1; It is characterized in that; Those second electrode neighbor configuration of part are in an end of those sweep traces; And connect odd number bar sweep trace, remaining those second electrode neighbor configuration is in an other end of those sweep traces, and connection even number bar sweep trace.

7. flat display panel according to claim 1 is characterized in that, this flat display panel be panel of LCD, electrophoresis display panel, electric wet-type display panel and organic LED panel one of them.

8. flat display panel according to claim 1 is characterized in that this driving circuit is a circuit system on glass, comprises with wherein a kind of technology of low temperature polycrystalline silicon, microcrystal silicon, amorphous silicon to be formed directly into driving circuit on glass.

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