CN101937406A - Method and system for driving 1394 devices in VxWorks operating system - Google Patents
Method and system for driving 1394 devices in VxWorks operating system Download PDFInfo
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Abstract
The invention provides a method and a system for driving 1394 devices in a VxWorks operating system. The method comprises the following steps: (a) initializing; (b) interruption handling; (c) and enabling DMA to read/write, and receiving and transmitting data. The system comprises an initializing unit, an interruption handling unit, a data transmitting unit and a data receiving unit, wherein the initializing unit is used for setting a relative register of the link layer chip and a relative bit of a physical layer register, enabling the registers to be in the ready state, and initializing a DMA receiving descriptor and a DMA transmitting descriptor; the interruption handling unit is used for handling various interruptions; the data transmitting unit is used for transmitting data in a DMA mode; and the data receiving unit is used for receiving data in a DMA mode. The invention drives 1394 devices in the VxWorks operating system.
Description
Technical field
The present invention relates to field of computer technology, more particularly, relate to the method and system of realizing 1394 equipment that drive in a kind of vxworks operating system.
Background technology
IEEE (Institute of Electrical and Electronics Engineers, IEEE-USA) the 1394th, by a kind of high-speed serial interface of apple (APPLE) company proposition, Apple is referred to as FireWire (live wire), Sony (Sony) is referred to as i.Link, and Texas Instrument (Texas Instruments) is referred to as Lynx.Nineteen ninety-five, IEEE formulates and has issued IEEE 1394-1995 standard, and has released IEEE 1394A standard in 2000, can support the transfer rate of 100Mbps, 200Mbps and 400Mbps.In up-to-date IEEE1394B standard, the transfer rate of support has been brought up to 800Mbps, 1.6Gbps and 3.2Gbps.
The IEEE1394 bus is except the transfer rate height, and it is simple, easy to use also to have an interface, advantages such as favorable compatibility and upgradability, and can be independent of main frame, and support the connection of point-to-point, each node can independently be carried out affairs by Offhost.This standard has obtained the concern of a lot of well-known IT vendors both domestic and external and support energetically since issue, many manufacturers are in order to make this technology can widespread use and popularization, and design link layer chip based on the OHCI standard, make by CPU control link layer chip realize the data interaction of point-to-point become a kind of may.
Vxworks operating system is that (Real-Time Operating System RTOS), is the key components of embedded-development environment to a kind of embedded real-time operating system of designing and developing in nineteen eighty-three of U.S. WindRiver company.In the high field of smart sharp technology such as its good sustained developing ability, high performance kernel, high reliability and remarkable real-time are widely used in and communicate by letters, military affairs, Aeronautics and Astronautics and real-time requirement.As a computer system, inevitably need to use exterior I/O equipment, the driver of I/O equipment provides accessibility and operability for it just.At present, vxworks operating system provides the support that multiple I/O device driver package is drawn together serial ports, parallel port, network interface card, ATA etc., but do not provide driving support to external unit (being called for short 1394 equipment) with 1394 standard interfaces, and, realize that in vxworks operating system 1394 equipment that drive are necessary in view of the increasingly extensive and many superiority of the application of 1394 equipment.
Summary of the invention
The objective of the invention is at the deficiencies in the prior art and defective, a kind of method and system with 1394 equipment of realizing driving in vxworks operating system is provided.
For achieving the above object, the embodiment of the invention provides following technical scheme: realize the method for 1394 equipment that drive in a kind of vxworks operating system, comprise step:
A) initialization;
B) Interrupt Process;
C) enable the DMA read-write, receive and send data.
Described a) initialization further comprises step:
A1) link layer register and Physical layer register are set, make register be in standby condition;
A2) initialization DMA receives descriptor and DMA transmission descriptor;
A3) interrupt service routine is installed, is made by the interrupt mask register that the link layer chip is set and interrupt opening;
A4) warm reset bus, the enable link layer.
Described a1) link layer register and Physical layer register are set, make register be in standby condition and specifically comprise step:
The bus option register is set; Console controller control register LPS position is set; Bus number in node identification and the status register is set; Enable the PostedWrites position; Remove the link layer control register; Enable cycle timer and period controller; Remove interrupt register; Tagging DMA buffer area is set and enables tagging DMA; Configuration ROM mapping register and initialization ConfigROM are set; Obtain the size of maximum data packet, unit is a byte; Asynchronous receiving filtration register is set; The byte exchange is set.
Described a2) initialization DMA reception descriptor and DMA transmission descriptor specifically comprise step:
Determine transmission descriptor that needs and the number that receives descriptor;
For sending data and receiving the data allocations memory headroom;
Initialization sends the descriptor chained list and receives the descriptor chained list;
In corresponding command register, dma controller carries out command analysis according to the address in the register with the address assignment of the head node of each descriptor chained list.
Describedly for the storage allocation space specific implementation that transmits and receive data be: disposablely in the physical memory space, open up one section continuous space, the storage packet that sends and receive respectively, described continuous space is divided into some equal memory blocks.The size that sends the single memory block of buffer zone is the size of the packet of a maximum, the integral multiple of the size of the packet that the single memory block size of send buffer is a maximum, and whole storage space is static, does not discharge in operational process.
The read operation of described DMA comprises step: after receiving the signal that interruption that packet context Processing tasks receives DMA produces, whether inquiry has packet to come in current reception descriptor, and judged whether to stride descriptor, the address and the big or small mode by message queue together that will receive packet according to the information that obtains passes to the task of unpacking then.
The write operation of described DMA comprises step: after the data envelope that application program will need to send installs, earlier the information of packet is put in the dynamic chained list, send the descriptor chained list from being inserted into successively then according to the form that sends descriptor, by the transmission that relevant register starts DMA is set, after first packet of transmission finishes, can produce one and be sent completely interruption, in this interruption, can continue from dynamic link table, to obtain packet and be inserted in the descriptor chained list, up to the transmission of finishing entire packet.
Described interruption comprises: the interruption of irrecoverable property, circulation bag interruption continuously, and bus reset interrupts, and request is sent completely interruption, and response is sent completely interruption, and request package is interrupted, and the respond packet interruption receives when waiting and interrupts, and sends when waiting to interrupt and the interruption of tagging bag.
Realize the system of 1394 equipment that drive in a kind of vxworks operating system, comprising:
Initialization unit is used to be provided with the relevant bits of the related register and the Physical layer register of link layer chip, makes to be in standby condition, and initialization DMA receives descriptor and DMA sends descriptor;
The Interrupt Process unit is used to handle all kinds of interruptions;
Data transmission unit sends data with dma mode;
The Data Receiving unit receives data with dma mode.
Described initialization unit further comprises:
The initialization of register unit is used to be provided with the bus option register; LPS position in the console controller control register is set; Bus number in node identification and the status register is set; Enable the PostedWrites position; Remove the link layer control register; Enable cycle timer and period controller; Remove interrupt register; Tagging DMA buffer area is set and enables tagging DMA; Configuration ROM mapping register and initialization ConfigROM are set; Obtain the size of maximum bag, unit is a byte; Asynchronous receiving filtration register is set; The byte exchange is set;
The Memory Allocation unit is used for the disposable one section continuous space of opening up in the physical memory space, store the packet that sends and receive respectively, and described continuous space is divided into some equal memory blocks;
The dma descriptor initialization unit is used for initialization DMA and sends descriptor chained list and DMA reception descriptor chained list;
Interruption articulates the unit, is used to articulate interrupt service routine.
As seen, compared with prior art, the technical scheme that the embodiment of the invention provides has realized 1394 equipment that drive in vxworks operating system.
Description of drawings
Fig. 1 is IEEE 1394 hardware topology structural representations;
Fig. 2 is IEEE 1394 protocol stack structure synoptic diagram;
Fig. 3 is IEEE 1394 driving framework synoptic diagram;
Fig. 4 is the packet flow graph between two equipment of IEEE 1394B;
Fig. 5 distributes synoptic diagram for a kind of memory headroom that the embodiment of the invention provides;
Fig. 6 receives descriptor chain list structure synoptic diagram for embodiment of the invention DMA;
Fig. 7 is an embodiment of the invention packet receiving data stream synoptic diagram;
Fig. 8 sends descriptor chain list structure synoptic diagram for embodiment of the invention DMA;
Fig. 9 sends data flow diagram for embodiment of the invention packet;
Realize the method flow diagram of 1394 equipment that drive in a kind of vxworks operating system that Figure 10 provides for the embodiment of the invention;
Realize the system architecture synoptic diagram of 1394 equipment that drive in a kind of vxworks operating system that Figure 11 provides for the embodiment of the invention.
Embodiment
The invention will be further described below in conjunction with drawings and Examples, the embodiment of the invention is that example describes in detail with OHCI (Open Host Controller Interface) link layer chip and the physical chip that drives the release of company of Texas Instrument (TI) particularly to drive the external unit with 1394 standard interfaces in vxworks operating system.
The topological structure of 1394 buses is tree-like structures, tree structure is exactly that all equipment that link together can not form a ring (circle), otherwise just can not normally work, but IEEE 1394B has proposed a method of avoiding ring texture, though equipment be connected to form a ring (circle) also can operate as normal.
See also shown in Figure 1ly, Fig. 1 is an IEEE 1394B bus hardware topological structure.An IEEE1394 system is made up of numerous addressable nodes (node), and node (node) is one the 1394 basic composition unit in the network.
See also shown in Figure 2ly, Fig. 2 is an IEEE1394 protocol stack structure synoptic diagram.IEEE 1394 standard definitions three basic agreement layers, be respectively transaction layer, link layer, Physical layer, the data transmission procedure that is used between requestor and respondent is finished relevant service, has increased bus management layer and application layer afterwards newly, every layer of service of being responsible for finishing oneself.The embodiment of the invention is based on that asynchronous transfer mode in the link layer realizes driving.
See also shown in Figure 3, Fig. 3 is an IEEE1394B driving framework synoptic diagram, the embodiment of the invention drives and has only realized the data link layer in the protocol stack, provide some application program interface function to the user, can directly on application layer, call this interface function and carry out the DMA transmission of packet, data are arrived the node that receives by Physical layer and transmission cable.
See also shown in Figure 4, Fig. 4 is the packet flow graph between two equipment of IEEE 1394B, in point-to-point data transmission, initiate a request package by application program in the node one (sending ending equipment), DMA by transmitting terminal is sent to node two (receiving device) via 1394 cable, node two passes to the reception task by receiving after DMA receives packet, the reception task unpacks the back according to packet format and sends a response data packet, send DMA by it and be sent to node one via 1394 cables, the reception DMA of node one passes to the reception task after receiving response data packet then, has finished the process of a data interaction like this.
Data link layer has mainly realized receiving the data descriptor chained list of DMA and transmission DMA, and this chained list is maintained in internal memory, carries out communication by this chained list and dma controller.
See also shown in Figure 5ly, the present invention adopts unified Memory Distribution Map, promptly in initialization procedure, opens up one section continuous space in physical memory, respectively the storage packet that sends and receive.Whole storage space is static, does not discharge in operational process.The size that is used to send the single memory block of packet is the size of the packet of a maximum, the integral multiple of the size of the packet that the single memory block size that is used to receive packet is a maximum.
At present, 1394 OHCI (Open Host Controller Interface, open host controller interface agreement) supports 7 kinds of DMA (Direct Memory Access, direct memory access) type, every kind of DMA type all has the register space of oneself, and support " logical data flow context (Context) ", i.e. a DMA passage at least.Each DMA passage is by a DMA context chained list (Context program) and two other register: context control register (ContextControl register) and command address register (CommandPtr register) are formed.The context chained list is meant the dma descriptor chained list, and this chained list is arranged in main memory.Each descriptor definition in the descriptor chained list data packet format waiting for transmission and control information, and data are put into corresponding FIFO (First Input First Output by corresponding D MA controller, first in first out) in the data buffer, sends interrupt request then.The context control register can be controlled beginning and the end of DMA, and returns transmission state; Command address register is used for preserving the number of the start address and the descriptor of descriptor chained list.
In order to satisfy the needs of driver efficient operation and realization, the embodiment of the invention has defined following several data structures:
DMA receives descriptor structure body (DMA_CMD)
struct?dma_cmd
{
U32 control; The control bit of/* command description symbol, 32 */
U32 address; The address of/* data buffer, 32 */
U32 branchAddress; The address of the next descriptor of/*, 32 */
U32 status; / * mode bit, 32 */
}；
DMA sends descriptor structure body (AT_DMA_PRG)
struct at_dma_prg
{
Struct dma_cmd begin; / * initial order descriptor, 16 byte */
Quadlet_t data[4]; / * be used for store data packet header */
Struct dma_cmd end; / * the finish command descriptor, 16 byte */
Quadlet_t pad[4]; Be used for when/* needs filling, assurance be 16 byte-aligned */
}；
DMA receives context mechanism body (DMA_RCV_CTX)
struct?dma_rcv_ctx
{
struct?ti_ohci*ohci；
Enum context_type type; The contextual type of/*, whether be asynchronous or synchronous */
Int ctx; / * whether be request contexts or response context */
Unsigned int num_desc; The number * of/* reception descriptor/
Unsigned int buf_size; / * be used for depositing the big or small * of single DMA send buffer/
Unsigned int split_buf_size; The big or small * that the data packet buffer that/* separates distributes/
Struct dma_cmd**prg_cpu; / * is used for depositing the first ground of the reception descriptor of specifying number
Location */
dma_addr_t*prg_bus；
Quadlet_t**buf_cpu; / * be used for depositing the first address * of first single memory block/
Quadlet_t*split_buf; / * separates the buffer zone of bag, and the size of maximum data packet is worked as appearance
When striding descriptor, that the reception that is distributed in two descriptor correspondences is slow
The packet that dashes the district be incorporated into handle in this memory block */
Int length; / * is used for depositing in the current DMA send buffer and effectively counts
According to length */
Unsigned int buf_ind; The sequence number * of the DMA reception descriptor that/* is current/
Unsigned int buf_offset; / * be used for depositing current DMA receive in the descriptor effectively
The address offset amount * of data/
quadlet_t*spb；
spinlock_tlock；
Int ctrlClear; / * deposits the control of asynchronous reception context and removes the register side-play amount, can remove register with visiting asynchronous reception context control by this numerical value, can be used for stopping to receive DMA*/
Int ctrlSet; The asynchronous reception context of/* control setting register side-play amount can be with visiting asynchronous reception context control setting register by this numerical value, can be used for starting receive DMA*/
Int cmdPtr; / * command pointer register side-play amount can be used for the visit order pointer register by this numerical value, and the command pointer register has been deposited first and effectively received the address of descriptor, notice DMA from this descriptor corresponding buffer region begin to receive packet */
int?ctxtMatch；
}；
DMA sends context mechanism body (DMA_TRM_CTX)
struct?dma_trm_ctx
{
struct?ti_ohci*ohci；
enum?context_type?type；
int?ctx；
Unsigned int num_desc; / * be used to send the number * of descriptor/
Struct at_dma_prg**prg_cpu; / * is used to preserve the internal memory that first sends descriptor
Address */
Unsigned int prg_ind; / * be used for writing down the sequence number * of current descriptor/
unsigned?int?sent_ind；
Int free_prgs; The number of the descriptor of/* free time is not if be 0 then expression can
To be used for sending packet, if be 0, then can not send */
Quadlet_t*branchAddrPtr; / * be used for preserving the address * of next descriptor/
Struct list_head fifo_list; Doubly linked list of/* is used for linking the data that need transmission
Bag */
Struct list_head pending_list; Doubly linked list of/* is used for linking the number that does not send
According to the bag */
spinlock_t?lock；
Int ctrlClear; / * deposits asynchronous transmission context control and removes the register side-play amount, can remove register with visiting the control of asynchronous transmission context by this numerical value, can be used for stopping to send DMA*/
Int ctrlSet; / * asynchronous transmission context control setting register side-play amount can be with visiting asynchronous transmission context control setting register by this numerical value, can be used for starting send DMA*/
Int cmdPtr; / * command pointer register side-play amount, can be used for the visit order pointer register by this numerical value, the command pointer register has been deposited first address that effectively sends descriptor, behind the asynchronous transmission context control setting register, DMA will from this descriptor begin to resolve and send packet */
}；
The structure (TI_OHCI) of 1394 OHCI is described
struct?ti_ohci
{
enum
{
OHCI_INIT_ALLOC_HOST，
OHCI_INIT_HAVE_MEM_REGION，
OHCI_INIT_HAVE_IOMAPPING，
OHCI_INIT_HAVE_CONFIG_ROM_BUFFER，
OHCI_INIT_HAVE_SELFID_BUFFER，
OHCI_INIT_HAVE_TXRX_BUFFERS_MAYBE，
OHCI_INIT_HAVE_IRQ，
OHCI_INIT_DONE，
}init_state；
void*registers；
Quadlet_t*selfid_buf_cpu; / * tagging packet deposit memory address */
quadlet_t*csr_config_rom_cpu；
int?csr_config_rom_length；
Unsigned int max_packet_size; The big or small * of/* maximum data packet/
Struct dma_rcv_ctx ar_resp_context; The asynchronous reception response of/* context mechanism body */
Struct dma_rcv_ctx ar_req_context; The asynchronous reception request contexts of/* structure */
Struct dma_trm_ctx at_resp_context; / * asynchronous transmission response context mechanism body */
Struct dma_trm_ctx at_req_context; / * asynchronous transmission request contexts structure */
struct?hpsb_host*host；
int?phyid，isroot；
spinlock_t?phy_reg_lock；
spinlock_t?event_lock；
int?self_id_errors；
unsigned?int?selfid_swap:1；
unsigned?int?no_swap_incoming:1；
unsigned?int?check_busreset:1；
}；
See also shown in Figure 6ly, Fig. 6 is that DMA receives the descriptor chain list structure.Receiving dma descriptor pointer (prg_cpu) among the figure comes the DMA of the appointment number of dynamic assignment to receive the address of first descriptor of descriptor by the user when being used for being kept at initialization.Descriptor pointer 0 (prg_cpu[0]), descriptor pointer 1 (prg_cpu[1]), descriptor pointer 2 (prg_cpu[2]), descriptor pointer 3 (prg_cpu[3]) are used to preserve the address of each descriptor of dynamic assignment to descriptor pointer N (prg_cpu[N]).
Described control bit (Control), send buffer address (Data Address), the piece that next descriptor address (Branch Addres) and mode bit (Status) are formed constitutes a DMA_CMD structure on data structure.Need to prove that next descriptor address (BranchAddress) the inside has comprised two parts, a part is the address of next descriptor, and a part is the zone bit of one 4 bit.Whether this zone bit is used for identifying this next one descriptor effective.If 1 is effectively, if 0 is invalid, and expression finishes.
Address and this zone bit that BanchAddress variable in first descriptor has been deposited next descriptor are 1, the BranchAddress variable of second descriptor has been deposited the address of the 3rd descriptor, and it is 1 that this zone bit is set, and the like, descriptor to the last, the BranchAddress variable of last descriptor has been deposited the address of first descriptor, but this zone bit is 0, expression finishes, and has formed a loop chain like this.
The address of first buffer zone of the DMA send buffer of the appointment number that send buffer pointer (buf_cpu) is distributed by the user when being used to preserve initialization, send buffer pointer 0 (buf_cpu[0]), send buffer pointer 1 (buf_cpu[1]), send buffer pointer 2 (buf_cpu[2]) are to address that send buffer pointer N (buf_cpu[N]) has preserved the send buffer of each DMA reception descriptor correspondence.
After more than distributing, the address of first descriptor is stored in the asynchronous reception command pointer register, asynchronous reception DMA will carry out associative operation from this descriptor.After the DMA start bit set of register is set when asynchronous reception context, DMA reception mechanism will start so, as long as there is packet to send over from cable, this DMA receives controller just the send buffer of deposit data to appointment.
See also shown in Figure 7ly, Fig. 7 is that packet receives schematic flow sheet.Solid line is represented once actual operation among the figure, and the operation that the dotted line representative will take place successively.The size of each memory block is the integral multiple of packet.Pass to resolution data bag task from the data packet addressed of memory block 1 to N and the length mode by message queue.The flow process that receives packet comprises step: when receiving packet, after receiving the signal that interruption that packet context Processing tasks receives DMA produces, whether inquiry has packet to come in current reception descriptor, and judged whether to stride descriptor, the address and the big or small mode (function in the Vxworks system) by message queue together that will receive packet according to the information that obtains passes to resolution data bag task then, and the data of reception can be successively placed on as in the static memory among Fig. 5.
In the embodiment of the invention, because the size of packet may be uncertain, but the send buffer of each descriptor correspondence (in the internal memory of just distributing a certain) might not be just to fill remaining space, so just needs to use next descriptor corresponding buffer region to come another part of store data bag.In the embodiment of the invention, the send buffer of each descriptor correspondence is continuous in internal memory, but buffer length is limited, final always to the end, if stride the situation of descriptor at the end, will cause the packet that receives imperfect in internal memory, need to judge the back manually in the buffer zone from last descriptor and first descriptor this packet of big young pathbreaker according to the bag of appointment combine just passable.Last descriptor corresponding buffer region has been used up first send buffer of use, and which descriptor DMA uses automatically is to be judged by the status indicator in the descriptor.Illustrate, supposed to receive a new packet, length is 9 bytes, and it should be stored in the send buffer that current descriptor points to.But owing to last received packet and only remaining 5 idle bytes, at this moment, after receiving, current descriptor corresponding buffer region needs to use 4 bytes of the send buffer of next descriptor correspondence in the current descriptor corresponding buffer region.
See also shown in Figure 8ly, Fig. 8 is that DMA sends the descriptor chain list structure.Transmission descriptor chained list among Fig. 8 is made up of single transmission descriptor, selects the number of chained list node as required with the situation of reality.Single transmission descriptor structure meets the AT_DMA_PRG structure.Sending dma descriptor pointer (prg_cpu) among the figure comes the DMA of the appointment number of dynamic assignment to send the address of first descriptor of descriptor by the user when being used for being kept at initialization.Send descriptor pointer 0 (prg_cpu[0]), send descriptor pointer 1 (prg_cpu[1]), send descriptor pointer 2 (prg_cpu[2]), send descriptor pointer 3 (prg_cpu[3]) to address that transmission descriptor pointer N (prg_cpu[N]) has preserved each descriptor of dynamic assignment.
What need further specify is, in one hurdle, address of " next descriptor " among Fig. 8, has comprised 4 minimum bit numerical value, is referred to as Z, is used for representing to send the command block numerical value of needed 16 bytes.By the OHCI standard as can be known, the descriptor Z value that has * _ Immdiate is 2, and the Z of other descriptor is 1, can learn like this, if having data payload, then the Z value is 3, otherwise is 2.Transmission DMA can know that the number of the command block of 16 bytes that current packets need is used determines whether that transmission finishes.
After more than distributing, just can be used for sending packet.
See also shown in Figure 9ly, Fig. 9 is a packet transmission flow journey synoptic diagram.Solid line is represented once actual operation among the figure, and the operation that the dotted line representative will take place successively.The size of each memory block is the integral multiple of packet.The flow process that sends packet comprises step:
At first carry out the set of applications bag, populated according to the form of standard the packet that needs send, driver can be suspended to this packet earlier in the doubly linked list.If packet is a lot, will arrange successively backward.Judged whether that then idle descriptor determines whether continuing to send this packet, if have then earlier send the packet that can send with existing descriptor, if not then wait for, idle transmission descriptor will be arranged after interrupting producing up to being sent completely.Then successively from doubly linked list to be sent data fetch packet be inserted into to send to start in the descriptor and send DMA and send, finish up to transmission.
In the embodiment of the invention, use three kinds of command description symbols to insert bag, packet is different with receiving.If there is not the packet of load (data content), then use the OUTPUT_LAST_Immdiate descriptor, if the packet of load (having only packet header) is arranged, then use OUTPUT_MORE_Immdiate descriptor and OUTPUT_LAST descriptor, finish that each packet is inserted in the transmission descriptor chained list.Relevant bits in the register is set starts DMA and send by the asynchronous transmission context is set then.
See also shown in Figure 10ly, Figure 10 is a kind of initial method process flow diagram that the embodiment of the invention provides, and comprises step:
Step 1001: the relevant bits of the related register and the Physical layer register of link layer chip is set, makes to be in standby condition, specifically may further comprise the steps:
Bus options (bus option) register is set;
LPS position in console controller control (HCControl) register is set, LPS is referred to as to connect power supply status, it is a control bit in the HCControl register, this is a control bit that is used for connecting between enable link layer chip and the physical chip, after enabling, can carry out the read and write operation of Physical layer by the link layer chip, otherwise link layer can not be carried out the read-write operation of Physical layer;
Bus number in Node indentification and status (node identification and the state) register is set; Enable PostedWrites (announcement is write, and is meant to send an answer signal before data are write host memory) position;
Remove the link layer control register; Enable cycle timer and period controller;
Remove interrupt register;
Tagging DMA buffer area is set and enables tagging DMA;
Configuration ROM mapping (configuration ROM mapping) register and initialization Configrom are set;
Obtain the size of maximum bag, unit is a byte;
Asynchronous receiving filtration register is set;
The byte exchange is set.
Step 1002: initialization DMA receives descriptor and DMA sends descriptor;
Specifically comprise concrete steps:
Determine the number of needed transmission descriptor and reception descriptor, be provided with according to own needs;
Be the storage allocation space that transmits and receive data;
Initialization sends and receives the descriptor chained list;
In corresponding command register, dma controller carries out command analysis according to the address in the register with the address assignment of the head node of each descriptor chained list.
Step 1003: interrupt service routine is installed, is made by the interrupt mask register that the link layer chip is set and interrupt opening;
Need to prove, in the embodiment of the invention API (Application Programming Interface by vxworks operating system, application programming interfaces) function is installed, and by IntMask (interrupt mask) register is set needed interrupt bit is set.
In the embodiment of the invention, the reception of DMA data and transmission all need CPU application interruption is told the current state of program, and the efficient of system handles also can be embodied in this Interrupt Process function.When system need enter interruption, by reading the interrupt event register, which type of interrupt judgement is, the interrupt type that occurs in the embodiment of the invention is including, but not limited to irrecoverable property interruption, circulation bag is continuously interrupted, bus reset interrupts, and request is sent completely interruption, and response is sent completely interruption, request package is interrupted, respond packet is interrupted, and receives when waiting and interrupts, and sends when waiting and interrupts, tagging bag interruption etc., if there is the interruption of the above-mentioned type to take place, then at first clear corresponding interruption flag is handled this interruption then.
Step 1004: warm reset bus, enable link layer;
Need to prove that the warm reset bus is finished by the relevant bits of writing physical register, the enable link layer is finished by the HCControl register is set.
According to above-mentioned method, the embodiment of the invention also provides the system that realizes 1394 equipment that drive in a kind of vxworks operating system, and as shown in figure 11, system comprises:
In the embodiment of the invention, described initialization unit 1101 further comprises:
Initialization of register unit 11011 is used to be provided with Bus options (bus option) register; LPS position in HCControl (console controller control) register is set, LPS is referred to as to connect power supply status, it is a control bit in the HCControl register, this is a control bit that is used for connecting between enable link layer chip and the physical chip, after enabling, can carry out the read and write operation of Physical layer by the link layer chip, otherwise link layer can not be carried out the read-write operation of Physical layer; Bus number in Node indentification and status (node identification and the state) register is set; Enable the PostedWrites position; Remove the link layer control register; Enable cycle timer and period controller; Remove interrupt register; Tagging DMA buffer area is set and enables tagging DMA; Configuration ROM mapping (configuration ROM mapping) register and initialization Configrom are set; Obtain the size of maximum bag, unit is a byte; Asynchronous receiving filtration register is set; The byte exchange is set.
One section continuous space is disposablely opened up in Memory Allocation unit 11012 in the physical memory space, the storage packet that sends and receive respectively, and described continuous space is divided into some equal memory blocks.The size that sends the single memory block of buffer zone is the size of the packet of a maximum, the integral multiple of the size of the packet that the single memory block size of send buffer is a maximum, and whole storage space is static, does not discharge in operational process;
Dma descriptor initialization unit 11013 is used for initialization DMA and sends descriptor chained list and DMA reception descriptor chained list;
Interruption articulates unit 11014, is used to articulate interrupt service routine.
Further, native system also comprises:
Interrupt Process unit 1102 is used to handle all kinds of interruptions;
Further, native system also comprises:
Further, native system also comprises:
Need to prove that the annexation between each unit that the embodiment of the invention provides is in order clearly to explain the needs of its information interaction control procedure, therefore only to be considered as annexation in logic, and should not only limit to physical connection.
By said system, embodiment provided by the invention has realized in vxworks operating system the driving to 1394 equipment.
In sum, the embodiment of the invention is an example with OHCI link layer chip and the physical chip that TI (Texas Instrument) company releases, and the principle and the embodiment of the embodiment of the invention are set forth.For present technique field personnel, the technical scheme that provides by the embodiment of the invention can be developed 1394 drivers of other individual chips.
Through the above description of the embodiments, those skilled in the art can be well understood to the present invention and can realize by the mode that software adds essential hardware platform, can certainly all implement, but the former is better embodiment under a lot of situation by hardware.Based on such understanding, all or part of can the embodying that technical scheme of the present invention contributes to background technology with the form of software product, this computer software product can be stored in the storage medium, as ROM/RAM, magnetic disc, CD etc., comprise that some instructions are with so that a computer equipment (can be a personal computer, server, the perhaps network equipment etc.) carry out the described method of some part of each embodiment of the present invention or embodiment.
The embodiment of the invention has been used specific embodiment the principle and the embodiment of the embodiment of the invention has been set forth, and the explanation of above embodiment just is used to help to understand the method and the core concept thereof of the embodiment of the invention; Simultaneously, for one of ordinary skill in the art, according to the thought of the embodiment of the invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as the restriction to the embodiment of the invention.
Claims (10)
1. realize the method for 1394 equipment that drive in the vxworks operating system, it is characterized in that, comprise step:
A) initialization;
B) Interrupt Process;
C) enable the DMA read-write, receive and send data.
2. method according to claim 1 is characterized in that, described a) initialization further comprises step:
A1) link layer register and Physical layer register are set, make register be in standby condition;
A2) initialization DMA receives descriptor and DMA transmission descriptor;
A3) interrupt service routine is installed, is made by the interrupt mask register that the link layer chip is set and interrupt opening;
A4) warm reset bus, the enable link layer.
3. method according to claim 2 is characterized in that, described a1) link layer register and Physical layer register are set, make register be in standby condition and specifically comprise step:
The bus option register is set; Console controller control register LPS position is set; Bus number in node identification and the status register is set; Enable the PostedWrites position; Remove the link layer control register; Enable cycle timer and period controller; Remove interrupt register; Tagging DMA buffer area is set and enables tagging DMA; Configuration ROM mapping register and initialization ConfigROM are set; Obtain the size of maximum data packet, unit is a byte; Asynchronous receiving filtration register is set; The byte exchange is set.
4. method according to claim 2 is characterized in that, described a2) initialization DMA receives descriptor and DMA transmission descriptor specifically comprises step:
Determine transmission descriptor that needs and the number that receives descriptor;
For sending data and receiving the data allocations memory headroom;
Initialization sends the descriptor chained list and receives the descriptor chained list;
In corresponding command register, dma controller carries out command analysis according to the address in the register with the address assignment of the head node of each descriptor chained list.
5. method according to claim 4, it is characterized in that, describedly for the storage allocation space specific implementation that transmits and receive data be: disposablely in the physical memory space, open up one section continuous space, store the packet that sends and receive respectively, described continuous space is divided into some equal memory blocks.The size that sends the single memory block of buffer zone is the size of the packet of a maximum, the integral multiple of the size of the packet that the single memory block size of send buffer is a maximum, and whole storage space is static, does not discharge in operational process.
6. method according to claim 1, it is characterized in that, the read operation of described DMA comprises step: after receiving the signal that interruption that packet context Processing tasks receives DMA produces, whether inquiry has packet to come in current reception descriptor, and judged whether to stride descriptor, the address and the big or small mode by message queue together that will receive packet according to the information that obtains passes to the task of unpacking then.
7. method according to claim 1, it is characterized in that, the write operation of described DMA comprises step: after the data envelope that application program will need to send installs, earlier the information of packet is put in the dynamic chained list, send the descriptor chained list from being inserted into successively then according to the form that sends descriptor, by the transmission that relevant register starts DMA is set, after first packet of transmission finishes, can produce one and be sent completely interruption, in this interruption, can continue from dynamic link table, to obtain packet and be inserted in the descriptor chained list, up to the transmission of finishing entire packet.
8. according to each described method of claim 1-7, it is characterized in that, described interruption comprises: the interruption of irrecoverable property, circulation bag are continuously interrupted, and bus reset interrupts, request is sent completely interruption, response is sent completely interruption, and request package is interrupted, and respond packet is interrupted, Deng the time receive to interrupt, send when waiting and interrupt and the interruption of tagging bag.
9. realize the system of 1394 equipment that drive in the vxworks operating system, it is characterized in that, comprising:
Initialization unit is used to be provided with the relevant bits of the related register and the Physical layer register of link layer chip, makes to be in standby condition, and initialization DMA receives descriptor and DMA sends descriptor;
The Interrupt Process unit is used to handle all kinds of interruptions;
Data transmission unit sends data with dma mode;
The Data Receiving unit receives data with dma mode.
10. system according to claim 9 is characterized in that, described initialization unit further comprises:
The initialization of register unit is used to be provided with the bus option register; LPS position in the console controller control register is set; Bus number in node identification and the status register is set; Enable the PostedWrites position; Remove the link layer control register; Enable cycle timer and period controller; Remove interrupt register; Tagging DMA buffer area is set and enables tagging DMA; Configuration ROM mapping register and initialization ConfigROM are set; Obtain the size of maximum bag, unit is a byte; Asynchronous receiving filtration register is set; The byte exchange is set;
The Memory Allocation unit is used for the disposable one section continuous space of opening up in the physical memory space, store the packet that sends and receive respectively, and described continuous space is divided into some equal memory blocks;
The dma descriptor initialization unit is used for initialization DMA and sends descriptor chained list and DMA reception descriptor chained list;
Interruption articulates the unit, is used to articulate interrupt service routine.
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