CN101924931B - Digital television PSI/SI information distributing system and method - Google Patents
Digital television PSI/SI information distributing system and method Download PDFInfo
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- CN101924931B CN101924931B CN2010101771855A CN201010177185A CN101924931B CN 101924931 B CN101924931 B CN 101924931B CN 2010101771855 A CN2010101771855 A CN 2010101771855A CN 201010177185 A CN201010177185 A CN 201010177185A CN 101924931 B CN101924931 B CN 101924931B
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Abstract
The invention discloses digital television PSI/SI information distributing system and method. The system comprises a CPU, a TS stream output channel, a buffer control module, a distribution timing control module, a port polling control module, a combined buffer and continuity counting processing module, a system main control module and an SDRAM (Synchronous Dynamic Random Access Memory). Tasks of sending PSI/SI information, processed by the CPU originally, are contributed by hardware in a digital television embedded system to ensure that the CPU preferably processes and sends PSI/SI data packets without interrupting other tasks, thereby greatly lowering the load of the CPU, and ensuring that the requirement for interval accuracy of sending the PSI/SI data and the stability and the reliability of the system.
Description
Technical field
The present invention relates to a kind of DTV PSI/SI information system and method for giving out a contract for a project.
Background technology
When embedded system is applied in digital television front equipment; To the processing of programme information and PSI/SI with transmit that normally to adopt processor be that CPU handles and analyzes, need to handle owing to when machine works, have great deal of information, this just brings very high load to flush bonding processor; Especially when these information of transmission; CPU is from interrupting there is certain delay to transmission, especially in the operating system of preemptive multitasking mechanism, and the inaccuracy problem of life period when the task of CPU is switched; Impact for PSI/SI information transmission interval and accuracy; Can not reach in real time when causing a large amount of PSI/SI information to send, affect also for the PCR adjustment of program stream and disturb, more can cause the transmission spacing accuracy of PSI/SI; Such as the ECM in the scrambled program process, EMM, CAT meter accuracy inaccuracy, can cause the scrambling confusion phenomena.
Summary of the invention
Send PSI/SI information through CPU and cause cpu load excessive in order to solve existing embedded system; Influence the technical problem that it handles other tasks; The present invention provides that a kind of can effectively to solve CPU load when sending PSI/SI information excessive, makes the PSI/SI information can be in strict accordance with sending the technical scheme that separation standard is sent.
In order to realize above-mentioned technique effect; The technical scheme that the present invention adopts is: a kind of DTV PSI/SI information system of giving out a contract for a project; Comprise that CPU, TS flow output channel, it also comprises writes the buffering control module, the timing control module of giving out a contract for a project; Port poll control module, close road buffering and continuity counting processing module, main system control module and SDRAM, wherein:
Writing the buffering control module is connected with CPU through CPU bus on chip interface; And be connected to the timing control module of giving out a contract for a project; With receive and temporary CPU the packet that will send; The attribute data of record data bag simultaneously, the address that will be stored in SDRAM according to the attribute data calculated data bag simultaneously line item of going forward side by side;
The timing control module of giving out a contract for a project is connected with CPU through CPU bus on chip interface; And be connected with the external timing signal module; Under the driving of clock signal; Data transfer request according to CPU produces packet transmission request, and record will be stored in the memory address of SDRAM from the packet of writing the buffering control module;
Port poll control module is connected with the timing control module of giving out a contract for a project, with scheduling give out a contract for a project timing control module the packet request of sending simultaneously concurrent the referring to of read data packet memory address ask;
Close the road buffering and be connected with TS stream output channel, also send with the road of closing of realizing packet with continuity counting processing module; And
Main system control module respectively with write buffering control module, the timing control module of giving out a contract for a project, port poll control module and close the road buffering, continuity counting processing module is connected; And communicate by letter with SDRAM through sdram controller; Be used to control the state that the buffering control module is write in inquiry; When receiving that CPU writes when asking through the packet of writing the buffering control module and transmit; The packet of writing in the buffering control module is write the appropriate address among the SDRAM through sdram controller, when receiving the transmission request of the timing control module of giving out a contract for a project, extract the packet of being stored among the SDRAM through sdram controller; And packet is sent to closes road buffering and continuity counting processing module, to realize the SDRAM scheduling.
Above-mentioned a kind of DTV PSI/SI information system of giving out a contract for a project; Its described buffering control module of writing comprises property register, writes buffer register and address mapping table module; Described bag property register with write buffer register and be connected to CPU through cpu i/f respectively, the bag property register receives the packet attribute information that CPU sent, and the calculated data bag is stored in the address of SDRAM; Above-mentioned information with packet is sent to the address mapping table module then; Write the buffer stock module and accept packet that CPU sends and temporary, accept the control of main system control module simultaneously, temporary packet is sent to SDRAM through main system control module.
Above-mentioned a kind of DTV PSI/SI information system of giving out a contract for a project, its described timing control module of giving out a contract for a project comprises interval register group sum counter array, described interval register group is connected to CPU through cpu i/f; And be provided with timing value in advance; The timer array is connected to the external timing signal module, and recruiting unit's time pulse signal is also counted, and the timing value with count value and interval register compares simultaneously; When count value is identical with timing value, then produce the request of transmission.
Above-mentioned a kind of DTV PSI/SI information system of giving out a contract for a project; Its described port poll control module comprises port request poll module and request queue module; Described port request poll module is connected to the timer array; Receive packet and send request, and read the data packet addressed information in the address mapping table module, be sent to the request queue module after gathering and read the information of giving out a contract for a project with the waiting system main control module.
Above-mentioned a kind of DTV PSI/SI information system of giving out a contract for a project; Its described road buffering of closing comprises continuity counting control module and buffering control module with continuity counting processing module; Described continuity counting control module is connected to main system control module; When main system control module sends packet, packet is carried out the continuity counting, and continuity numerical value is write packet, the buffering control module receives the packet that continuity counting control module is sent; And in the gap of sending packet, insert buffered data packet, send by TS stream output channel.
The method that the present invention also provides a kind of DTV PSI/SI information to give out a contract for a project, the bag that CPU will send writes buffer module, and enables corresponding counting unit; Counting unit produces the request of sending packet after the transmission that arrives default at interval; After type requests poll module is received request; Extraction give out a contract for a project type and the bag sequence number of request of request are when the port poll activates corresponding ports, with the bag type of asking; Port numbers; The bag sequence number is carried out the SDRAM map addresses, obtains the address of request package in SDRAM, afterwards port numbers and SDRAM address is write the request array; Main control module has detected when request bag, and the packet that will send is read in the SDRAM address in the request array, closes the road buffer memory by what port numbers write the corresponding port, carries out the correction of continuity counting then; The last ready signal of set, passage close this signal of road control module response, and the bag that is about to buffering area is squeezed into circulation road, accomplish the hardware operation of giving out a contract for a project.
Technique effect of the present invention is; In the DTV embedded system, share the task of the transmission PSI/SI information that former cause CPU handles through hardware; Making CPU no longer need interrupt other tasks comes priority treatment to send the PSI/SI packet; Greatly reduce the load of CPU, guaranteed the reliable and stable of system.
Below in conjunction with accompanying drawing the present invention is further described.
Description of drawings
Fig. 1 is a structural representation of the present invention;
Fig. 2 is the structural representation of writing the buffering control module of the present invention;
Fig. 3 is the single port structural representation of the timing control module of giving out a contract for a project of the present invention;
Fig. 4 is the single particular counter structural representation of the timing control module of giving out a contract for a project of the present invention;
Fig. 5 is the type requests poll control module structural representation of the timing control module of giving out a contract for a project of the present invention;
Fig. 6 is the structural representation of port poll control module of the present invention;
Fig. 7 is the request queue modular structure sketch map of port poll control module of the present invention;
Fig. 8 closes the structural representation of road buffering and continuity counting processing module for the present invention;
Fig. 9 is the structural representation of main system control module of the present invention;
Figure 10 is the give out a contract for a project flow chart of method of PSI/SI information of the present invention.
Embodiment
Referring to Fig. 1, the present invention includes and write the buffering control module, the timing control module of giving out a contract for a project, is closed road buffering and continuity counting processing module, main system control module and SDRAM at port poll control module, wherein,
Write the buffering control module referring to Fig. 2 and promptly wrap property register and write buffer register by two groups of registers, and address mapping table module composition, the bag that CPU will send writes in the buffer register; To wrap attribute simultaneously and write the bag property register, after being ready to complete, CPU will write the control position; Request is write in the main control module response, and the control storage control module is transferred to packet among the SDRAM; And, write address mapping table according to bag property calculation SDRAM address.
Write buffer register by data bit width 32bit, the dpram of address bit wide 6bit realizes, each bag that only allows to preserve 188byte length or 204byte length, and untapped address is left register for, to save cpu address bit wide resource.
Give out a contract for a project the interval register group of timing control module by the counter enable register referring to Fig. 3, the fixed time interval register, the type package length register is formed.The bit wide decision size that the counter enable register is supported according to port is given tacit consent to 16 kinds of PSI/SI type package.The fixed time interval register divides three groups, second interval group, ms interval group, microsecond interval register group.Each registers group precision is adjustable according to the system requirements precision.Acquiescence support spacer 15s999ms999us～0m0mslus.The maximum packet length that each PSI/SI type of type package length register decision is supported.
Be used for producing the request of transmission referring to Fig. 4 particular counter group, 6 of port ones are given tacit consent in the PSI/SI number of types decision that the particular counter number is supported by each port.The bag sequence number that bag sequence number counting ram is used to store every type of current packet.Read the interval poll and make the fixed time interval selector switch.The type selecting of giving out a contract for a project poll module is used for when request is given out a contract for a project in the generation of counter group, doing the parameter extraction of giving out a contract for a project.
After CPU write the data packet memory and enables type counter, corresponding particular counter began counting, unit interval pulse each; Interval register when counter is read one time; And the value of current count value and interval register relatively, meter is full, then produces to send to ask.At this moment, the poll of giving out a contract for a project selects module to translate the type of request, the bag sequence number of inquiring about the current request bag simultaneously according to the address of request; To send request; Request type, the output of request package sequence number is after request is sent in the secondary module response; According to bag request length register update package sequence number counting, send request thereby accomplish a packet.
When considering the port expansion, the increase of counting unit is to the burden of system resource, and counting unit adopts particular structural, and other counter of constituent parts level is shared, and count mode control is set, and realizes a second counting with a counter, millisecond counting, microsecond tally function.After meter is full, produce request signal to type poll control module.
Send the conflict of request referring to Fig. 5 for various types of bags in port of scheduling; Adopt the mode of type poll, constantly inquire about the request that each counting unit produces, if request effectively; Control module is translated into the request type parameter according to the address of request unit.Simultaneously, the inquiry packet sequence number counter, the sequence number of extraction current request bag outputs to port poll module.At this moment, control module is waited for the port poll response, receive response after, the update package sequence number counter gets into the request signal inquiry of next type.
Referring to Fig. 6, port poll control module realizes the scheduling of each port request parameter, 64 ports of maximum support, and controller activates port one by one; Enable type poll module, when having inquired when request of giving out a contract for a project, the bag type that control module will be asked; The bag sequence number, the bag port numbers is carried out computing, reads the SDRAM address mapping table; What obtain asking wraps in the address among the SDRAM, then port numbers and address is squeezed into request queue, accomplishes one-time request and handles.
Referring to Fig. 7, the request queue module is realized that by FIFO write operation is accomplished in the control of port poll; Main control module detects when having request msg in the request queue; From FIFO, packet address and port numbers are read, and from SDRAM packet is read, simultaneously according to port numbers according to packet address; Bag is written to the packet output buffering corresponding with port, thereby accomplishes the operation of once giving out a contract for a project.
Referring to Fig. 8, close road buffering and continuity counting processing module as the give out a contract for a project interface of module and circulation road of hardware, the realization packet close the road function.Continuity counting control module is used for the processing of packet continuity count area, when CPU produces the data packets request, on the one hand; Main control module according to write the bag parameter will write the buffering control module bag write SDRAM; On the one hand, master control module controls continuity counting control module is carried out the PID inquiry, when in ram, not finding corresponding PID; PID and initial continuity count value are inserted in the table, wait flow process to be written to finish.After this, each main control module reads bag and writes when closing the road buffering from SDRAM, and continuity counting control module is all carried out the PID inquiry; Find the corresponding continuity count value of this PID, packet writes the packet relevant position with the continuity count value of finding after writing fully and closing the road buffering; After the completion; Numerical value adds 1, is written back to original position in ram, handles thereby accomplish one-time continuous property counting.
What the buffering control module realized packet and circulation road closes the road pooling feature; 2 packets of each port buffering of default setting are under the control of channel control signals, in the gap of each packet of circulation road; The packet of in good time insertion buffering is accomplished the transmission of packet.
The RAM scheduler module is used to distribute the continuity counting control module and the right to use that cushions control module; Wherein, buffering is read to control has the highest priority, when ram is read by passage; Ram can not be carried out read operation by other module again, and the scheduling of write conflict is accomplished by main control module.
RAM realizes by a M9K, from the consideration that improves the M9K utilance, the continuity count table with close the road and cushion a shared M9K.32 of data bit widths, 8 of address bit wides.Wherein, the continuity count table is made in the address of low 128bit, and like this, the PID number of each port support is 128.High 128bit does the address and closes the road buffering, cushions two packets.
Referring to Fig. 9; The request of the writing position of write control register and the mode bit of request queue are inquired about in the use of main system control module scheduling SDRAM in system, main system control module back and forth, write request as packet; The TS packet that just will write the bag buffering area writes the appropriate address among the SDRAM; Query requests formation after accomplishing when sending request, writes TS inclusion road buffering with bag.So circulation realizes the SDRAM scheduling.
Referring to Figure 10, the bag that CPU will send writes buffer module, enables corresponding counting unit, and counting unit is after the transmission that arrives default at interval; Produce the request of TS bag data, after type requests poll module is found request, extract the give out a contract for a project type of request and the bag sequence number of request; When the port poll activates corresponding ports, with the bag type of request, port numbers; The bag sequence number is carried out the SDRAM map addresses, obtains the address of request package in SDRAM, afterwards port numbers and SDRAM address is write the request array; Main control module has detected when request bag, and the packet that will send is read in the SDRAM address in the request array, closes the road buffer memory by what port numbers write the corresponding port; Carry out the correction of continuity counting at last, after all operations is accomplished, the ready signal of set; Passage closes this signal of road control module response, and the bag that is about to buffering area is squeezed into circulation road, accomplishes the hardware operation of giving out a contract for a project.
Claims (6)
1. DTV PSI/SI information system of giving out a contract for a project; Comprise that CPU, TS flow output channel; It is characterized in that this system also comprises writes the buffering control module, the timing control module of giving out a contract for a project; Port poll control module, close road buffering and continuity counting processing module, main system control module and SDRAM, wherein:
Writing the buffering control module is connected with CPU through CPU bus on chip interface; And be connected to the timing control module of giving out a contract for a project; With receive and temporary CPU the packet that will send; The attribute data of record data bag simultaneously, the address that will be stored in SDRAM according to the attribute data calculated data bag simultaneously line item of going forward side by side;
The timing control module of giving out a contract for a project is connected with CPU through CPU bus on chip interface; And be connected with the external timing signal module; Under the driving of clock signal; Data transfer request according to CPU produces packet transmission request, and record will be stored in the memory address of SDRAM from the packet of writing the buffering control module;
Port poll control module is connected with the timing control module of giving out a contract for a project, with scheduling give out a contract for a project timing control module the packet request of sending simultaneously concurrent the referring to of read data packet memory address ask;
Close the road buffering and be connected with TS stream output channel, also send with the road of closing of realizing packet with continuity counting processing module; And
Main system control module respectively with write buffering control module, the timing control module of giving out a contract for a project, port poll control module and close road buffering and count processing module with continuity and be connected; And communicate by letter with SDRAM through sdram controller; Be used to control the state that the buffering control module is write in inquiry; When receiving that CPU writes when asking through the packet of writing the buffering control module and transmit; The packet of writing in the buffering control module is write the appropriate address among the SDRAM through sdram controller, when receiving the transmission request of the timing control module of giving out a contract for a project, extract the packet of being stored among the SDRAM through sdram controller; And packet is sent to closes road buffering and continuity counting processing module, to realize the SDRAM scheduling.
2. a kind of DTV PSI/SI information according to claim 1 system of giving out a contract for a project; It is characterized in that; The described buffering control module of writing comprises property register, writes buffer register and address mapping table module; Described bag property register with write buffer register and be connected to CPU through cpu i/f respectively, the bag property register receives the packet attribute information that CPU sent, and the calculated data bag is stored in the address of SDRAM; Above-mentioned information with packet is sent to the address mapping table module then; Write the buffer stock module and accept packet that CPU sends and temporary, accept the control of main system control module simultaneously, temporary packet is sent to SDRAM through main system control module.
3. a kind of DTV PSI/SI information according to claim 1 system of giving out a contract for a project; It is characterized in that the described timing control module of giving out a contract for a project comprises interval register group sum counter array, described interval register group is connected to CPU through cpu i/f; And be provided with timing value in advance; The timer array is connected to the external timing signal module, and recruiting unit's time pulse signal is also counted, and the timing value with count value and interval register compares simultaneously; When count value is identical with timing value, then produce the request of transmission.
4. a kind of DTV PSI/SI information according to claim 1 system of giving out a contract for a project; It is characterized in that; Described port poll control module comprises port request poll module and request queue module, and described port request poll module is connected to the timer array, receives packet and sends request; And read the data packet addressed information in the address mapping table module, be sent to the request queue module after gathering and read the information of giving out a contract for a project with the waiting system main control module.
5. a kind of DTV PSI/SI information according to claim 1 system of giving out a contract for a project; It is characterized in that; The described road buffering of closing comprises continuity counting control module and buffering control module with continuity counting processing module, and described continuity counting control module is connected to main system control module, when main system control module sends packet, packet is carried out the continuity counting; And continuity numerical value write packet; The buffering control module receives the packet that continuity counting control module is sent, and in the gap of sending packet, inserts buffered data packet, is sent by TS stream output channel.
6. the method that DTV PSI/SI information is given out a contract for a project is characterized in that the bag that CPU will send writes buffer module, and enables corresponding counting unit; Counting unit produces the request of sending packet after the transmission that arrives default at interval; After type requests poll module is received request; Extraction give out a contract for a project type and the bag sequence number of request of request are when the port poll activates corresponding ports, with the bag type of asking; Port numbers; The bag sequence number is carried out the SDRAM map addresses, obtains the address of request package in SDRAM, afterwards port numbers and SDRAM address is write the request array; Main control module has detected when request bag, and the packet that will send is read in the SDRAM address in the request array, closes the road buffer memory by what port numbers write the corresponding port, carries out the correction of continuity counting then; The last ready signal of set, passage close this signal of road control module response, and the bag that is about to buffering area is squeezed into circulation road, accomplish the hardware operation of giving out a contract for a project.
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| KR101199369B1 (en) * | 2005-11-25 | 2012-11-09 | 엘지전자 주식회사 | Digital broadcasting system and processing method |
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