CN101872330B - Interrupt processing method of multi-PCIE (Peripheral Component Interface Express) equipment system - Google Patents
Interrupt processing method of multi-PCIE (Peripheral Component Interface Express) equipment system Download PDFInfo
- Publication number
- CN101872330B CN101872330B CN 200910250798 CN200910250798A CN101872330B CN 101872330 B CN101872330 B CN 101872330B CN 200910250798 CN200910250798 CN 200910250798 CN 200910250798 A CN200910250798 A CN 200910250798A CN 101872330 B CN101872330 B CN 101872330B
- Authority
- CN
- China
- Prior art keywords
- interrupt
- register
- pcie
- status register
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Bus Control (AREA)
Abstract
The invention discloses an interrupt processing method of a multi-PCIE (Peripheral Component Interface Express) equipment system, relating to the field of automatic control. In the invention, an interrupt register and an interrupt state register are arranged in advance, and the value of the interrupt state register changes along with the variation of a value of the interrupt register based on a preset rule; a notification message is sent when PCIE equipment generates interrupt, and an interrupt vector number and an interrupt register address which are configurated to the PCIE equipment in advance are carried in the message; after receiving the notification message, a main control end writes the interrupt vector number into the interrupt register corresponding to a mapping address; and an interrupt processing program which is registered in advance is called and executed based on the value of the interrupt state register, and the value of the interrupt state register is revised to restore an interrupt state of the PCIE equipment corresponding to the interrupt processing program into a non-interrupt state. The invention can process interrupt simultaneously generated by a plurality of PCIE equipments, and PCIE equipment which does not support an MSI (Medium-scale Integration) interrupt mode can apply the invention, therefore, the interrupt processing efficiency of the system is improved.
Description
Technical field
The present invention relates to automation field, particularly a kind of many PCIE device systems interruption processing method.
Background technology
PCIE (personal computer expansion bus interface) equipment is that a new generation can provide massive band width and enrich function to realize the brand-new framework of exciting new-type graphical application.Referring to Fig. 1; Be the topological structure synoptic diagram of many PCIE device systems, comprise main control end and several PCIE equipment as terminal point (End Point), wherein main control end comprises CPU and PCIE master's bridge (PCIE host bridge); PCIE master's bridge is mainly used in realizes that CPU supports cpu bus data layout and each PCIE equipment to support the data-switching between data layout; Usually, also can comprise PCIE Switch (interchanger), be used to coordinate many PCIE equipment room exchanges data.
Current, in the system of many PCIE equipment, a plurality of PCIE equipment often adopt interrupt mode and main control end cooperation.A kind of traditional Interrupt Process mode of PCIE equipment support at present mainly is; System provides 4 look-at-mes for PCIE equipment; INTA, INTB, INTC, INTD, different PCIE equipment can be configured on the different look-at-mes, when the PCIE equipment in the system during more than 4; Need to adopt the mode of interrupting of sharing; Promptly share the interruption status position that interrupt handling routine detects a plurality of PCIE equipment of sharing this interruption one by one, judge the concrete PCIE equipment that interrupts that produces, carry out corresponding interrupt handling routine.
In the system of many PCIE equipment; A plurality of PCIE equipment produce when interrupting simultaneously; Owing to need to share the interrupt status register that interrupt handling routine detects a plurality of PCIE equipment of sharing this interruption one by one, it is very big to cause interrupting time-delay, and along with the increase of PCIE equipment in the system sharply increases.
The hardware of some PCIE equipment can be supported MSI (Message Signaled Interrupt; Information signal interrupts) interrupt mode; The processing procedure of MSI interrupt mode is specially: the PCIE equipment that produce to interrupt generates MSI message (carry in the MSI message in advance for the interrupt vector of this PCIE devices allocation number); After PCIE master's bridge joint is received MSI message; Interrupt vector number is write in the interrupt register in the system of being pre-configured in, and main control end just can number be called interrupt handling routine according to the interrupt vector in the interrupt register.Owing to need not to inquire about the interruption status position of each PCIE equipment in the MSI interrupt mode, practiced thrift the Interrupt Process time, solved the inefficiency problem of traditional Interrupt Process mode.
In the embodiment of the present invention process, the inventor finds to exist at least in the prior art following problem: when a plurality of PCIE equipment produce interruption simultaneously, can produce a plurality of MSI message; After PCIE master's bridge joint is received a plurality of MSI message; Can a plurality of interrupt vector orders be write in the interrupt register in the system of being pre-configured in, at this moment, because main control end does not also have enough time to handle the interruption of previous interrupt vector correspondence; The interrupt vector in back number just can cover the previous interrupt vector number in the interrupt register; That is to say, for the main control end CPU that supports the MSI interrupt mode, can't handle the produced simultaneously interruption of a plurality of PCIE equipment.
Summary of the invention
For solving the problems of the technologies described above, the present invention provides a kind of many PCIE device systems interruption processing method.
A kind of many PCIE device systems interruption processing method; Interrupt register is set in advance writes down the interrupt status register that produces the PCIE equipment that interrupts with being used to, the value of said interrupt status register changes by the change of preset rules with the value of said interrupt register; Said method comprises:
When PCIE equipment produce to interrupt, send a notification message, carry in the said notification message in advance and to be the interrupt vector of said PCIE equipment disposition number and interrupt register mapping address in the PCIE space;
Main control end number writes the corresponding interrupt register of said mapping address with said interrupt vector after receiving notification message; Call and carry out the interrupt handling routine of registered in advance according to the value of interrupt status register, and revise the value of interrupt status register, with the interruption status of recovering the corresponding PCIE equipment of said interrupt handling routine for not producing interruption status.
Said main control end comprises CPU; The PCIE master's bridge that links to each other with said CPU; Being used for said CPU supports cpu bus data layout and each PCIE equipment to support the data-switching between data layout; PLD with linking to each other with said CPU is provided with interrupt register and interrupt status register in said PLD.
Said main control end number writes the corresponding interrupt register of said mapping address with said interrupt vector after receiving notification message; Call and carry out the interrupt handling routine of registered in advance according to the value of interrupt status register, and revise the value of interrupt status register, for not producing interruption status, be specially with the interruption status of recovering the corresponding PCIE equipment of said interrupt handling routine:
Said PCIE master's bridge writes said interrupt vector number in the interrupt register in said PLD after receiving notification message;
When the value of said interrupt status register changed, said PLD triggered interrupt request through interrupt pin to said CPU;
Said CPU calls and carries out the interrupt handling routine of registered in advance according to the value of interrupt status register, and revises the value of interrupt status register, with the interruption status of recovering the corresponding PCIE equipment of said interrupt handling routine for not producing interruption status.
When said PCIE equipment is supported the MSI interrupt mode, the mapping address of interrupt register in the PCIE space write in the Msi_Addr register of PCIE equipment; Interrupt vector number is write in the Msi_Data register of PCIE equipment; And said notification message is specially MSI message.
When said PCIE equipment was not supported the MSI interrupt mode, pre-configured said PCIE equipment sent to carry in advance and is the interrupt vector of said PCIE equipment disposition number and the interrupt register notification message at the mapping address in PCIE space when produce interrupting; And interrupt register number write respectively in two registers of PCIE equipment in the mapping address in PCIE space and interrupt vector.
Interruption status with a PCIE equipment of the corresponding sign of the value of each in the said interrupt status register; Said interrupt register comprises at least:
Interrupt status register is selected section, is used to select interrupt status register; With
Section is selected in the interrupt status register position, is used for selecting the position of interrupt status register; Then
The value of said interrupt status register changes with the change of the value of said interrupt register by preset rules and is specially:
According to the value of the selection of interrupt status register described in interrupt register section, select corresponding interrupt status register;
According to the value of the position of interrupt status register described in interrupt register selection section, in the interrupt status register of selecting, select corresponding position;
The value of institute's rheme of selecting is set to preset value, is used to identify the PCIE equipment generation interruption of this correspondence.
The figure place of said at least one interrupt status register is identical, then
It is Log that said interrupt status register is selected the figure place of section
2(N/M), work as Log
2When (N/M) being not integer, it is Log that said interrupt status register is selected the figure place of section
2(N/M) round up, wherein N is the maximum PCIE number of devices that described many PCIE device systems is supported, M is the figure place of interrupt status register.
The registration interrupt handling routine is specially:
To number add that side-play amount obtains the CPU interrupt number for the interrupt vector of PCIE equipment disposition; Said side-play amount is the number of interruptions that said CPU self supports;
Said PCIE device driver is to said CPU interrupt number registration interrupt handling routine;
The interrupt handling routine that registered in advance was called and carried out to said value according to interrupt status register is specially:
Calculate the interrupt vector that writes in the said interrupt register number according to the value of said interrupt status register;
Said interrupt vector number is added the above side-play amount obtain the CPU interrupt number;
Call and carry out interrupt handling routine to said CPU interrupt number registration.
Said CPU is that each interrupt status register distributes an interrupt pin in the PLD; Then when the value of certain interrupt status register changed, said PLD triggered interrupt request through the corresponding interrupt pin of this interrupt status register to said CPU.
Said CPU is that PLD distributes an interrupt pin, also is provided with main interrupt status register in the then said PLD, and said interrupt pin is linked to each other with main interrupt status register;
Each interrupt status register in said main interrupt register, have one corresponding with it, when the value of certain interrupt status register changed, the value that corresponding position is set in the said main interrupt status register was about definite value; Then when the value of main interrupt status register changed, said PLD triggered interrupt request through said interrupt pin to said CPU.
Many PCIE device systems interruption processing method provided by the invention; Beneficial effect is: because in many PCIE device systems of the present invention; Interrupt register is set in advance writes down the interrupt status register that produces the PCIE equipment that interrupts, and the value of said interrupt status register can change by the change of preset rules with the value of said interrupt register with being used to.Like this; When a plurality of PCIE equipment produce interruption simultaneously; After main control end receives a plurality of MSI message, can a plurality of interrupt vector orders be write in the interrupt register, whenever write in the interrupt register interrupt vector number; Interrupt status register can write down the PCIE equipment of the generation interruption of this interrupt vector correspondence; Then after a plurality of interrupt vector orders write interrupt register, though the value that writes after in the interrupt register can cover previous value, but will all produce in the interrupt status register interruption the PCIE equipment records get off; Main control end just can be handled produced simultaneously a plurality of interruption according to the value in the interrupt status register, thereby makes many PCIE device systems can handle the produced simultaneously interruption of a plurality of PCIE equipment.
Further; When PCIE equipment is not supported the MSI interrupt mode; Through pre-configured said PCIE equipment; It is sent a notification message to main control end when produce interrupting, with informing main control end for the interrupt vector of said PCIE equipment disposition number and interrupt register at the mapping address in PCIE space in advance, thereby can make main control end need not to share the interrupt status register that interrupt handling routine detects a plurality of PCIE equipment of sharing this interruption one by one; Shorten the interruption time-delay of handling the PCIE equipment of not supporting the MSI interrupt mode greatly, improve the system break treatment effeciency.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the topological structure synoptic diagram of many PCIE device systems in the prior art;
Fig. 2 provides a kind of many PCIE device systems interruption processing method process flow diagram for the embodiment of the invention one;
Fig. 3 provides a kind of preferred many PCIE device systems interruption processing method process flow diagram for the embodiment of the invention two;
Fig. 4 is a kind of preferred structure block diagram of main control end in the embodiment of the invention two;
Fig. 5 is a kind of logical diagram of interrupt register and interrupt status register in the embodiment of the invention two;
Fig. 6 is the another kind of logical diagram of interrupt register and interrupt status register in the embodiment of the invention two.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
For making the object of the invention, technical scheme and advantage clearer, will combine accompanying drawing that embodiment of the present invention is done to describe in detail further below.
In the embodiment of the present invention process, the inventor finds to exist at least in the prior art following problem: when a plurality of PCIE equipment produce interruption simultaneously, can produce a plurality of MSI message; After PCIE master's bridge joint is received a plurality of MSI message; Can a plurality of interrupt vector orders be write in the interrupt register in the system of being pre-configured in, at this moment, because main control end does not also have enough time to handle the interruption of previous interrupt vector correspondence; The interrupt vector in back number just can cover the previous interrupt vector number in the interrupt register; That is to say, for the main control end CPU that supports the MSI interrupt mode, can't handle the produced simultaneously interruption of a plurality of PCIE equipment.Further, only there is the hardware designs of the PCIE equipment of minority can support the PCIE equipment of using in the MSI interrupt mode, particularly built-in field nearly all not support the MSI interrupt mode at present, can only adopts traditional interrupt mode.For solving the problems of the technologies described above, the embodiment of the invention proposes a kind of many PCIE device systems interruption processing method, describes in detail as follows.
Embodiment one
Referring to Fig. 2, the embodiment of the invention provides a kind of many PCIE device systems interruption processing method, may further comprise the steps:
Step S201: interrupt register is set in advance and is used to write down the interrupt status register that produces the PCIE equipment that interrupts, the value of said interrupt status register changes by the change of preset rules with the value of said interrupt register.
Step S202: when PCIE equipment produce to interrupt, send a notification message, carry in the said notification message in advance and to be the interrupt vector of said PCIE equipment disposition number and interrupt register mapping address in the PCIE space.
Step S203: main control end number writes the corresponding interrupt register of said mapping address with said interrupt vector after receiving notification message; Call and carry out the interrupt handling routine of registered in advance according to the value of interrupt status register, and revise the value of interrupt status register, with the interruption status of recovering the corresponding PCIE equipment of said interrupt handling routine for not producing interruption status.
It is thus clear that; Because in many PCIE device systems of the embodiment of the invention; Interrupt register is set in advance writes down the interrupt status register that produces the PCIE equipment that interrupts, and the value of said interrupt status register can change by the change of preset rules with the value of said interrupt register with being used to.Like this; When a plurality of PCIE equipment produce interruption simultaneously; After main control end receives a plurality of MSI message, can a plurality of interrupt vector orders be write in the interrupt register, whenever write in the interrupt register interrupt vector number; Interrupt status register can write down the PCIE equipment of the generation interruption of this interrupt vector correspondence; Then after a plurality of interrupt vector orders write interrupt register, though the value that writes after in the interrupt register can cover previous value, but will all produce in the interrupt status register interruption the PCIE equipment records get off; Main control end just can be handled produced simultaneously a plurality of interruption according to the value in the interrupt status register, thereby makes many PCIE device systems can handle the produced simultaneously interruption of a plurality of PCIE equipment.
Further; When PCIE equipment is not supported the MSI interrupt mode; Through pre-configured said PCIE equipment; It is sent a notification message to main control end when produce interrupting, with informing main control end for the interrupt vector of said PCIE equipment disposition number and interrupt register at the mapping address in PCIE space in advance, thereby can make main control end need not to share the interrupt status register that interrupt handling routine detects a plurality of PCIE equipment of sharing this interruption one by one; Shorten the interruption time-delay of handling the PCIE equipment of not supporting the MSI interrupt mode greatly, improve the system break treatment effeciency.
Embodiment two
Referring to Fig. 3; The embodiment of the invention provides a kind of preferred many PCIE device systems interruption processing method, and is in conjunction with referring to Fig. 4, preferred; Main control end comprises central processor CPU 401; The PCIE master's bridge 402 that links to each other with CPU401 is used for CPU401 and supports cpu bus data layout and each PCIE equipment to support the data-switching between data layout, with the PLD that links to each other with CPU401 403.Certainly,, between PCIE master's bridge 402 and each PCIE equipment, can also comprise PCIE Switch, be used to coordinate many PCIE equipment room exchanges data according to the practical application scene.
Preferably, said PLD can be CPLD or FPGA etc.
In practical application, PCIE master's bridge 402 can be arranged on the mainboard, also can be integrated among the CPU401.
The method that the embodiment of the invention provides comprises the steps:
Step S301: interrupt register is set in PLD in advance and is used to write down the interrupt status register that produces the PCIE equipment that interrupts.
Preferably, with the corresponding interruption status that identifies a PCIE equipment of the value of each in the said interrupt status register; Said interrupt register comprises at least: interrupt status register is selected section, is used to select interrupt status register; Select section with the interrupt status register position, be used for selecting the position of interrupt status register.If also remain other in the interrupt register, can be with it as reservation paragraph.
Further, in the present embodiment, the figure place of a plurality of interrupt status registers is all identical, and it is Log that then said interrupt status register is selected the figure place of section
2(N/M), work as Log
2When (N/M) being not integer, it is Log that said interrupt status register is selected the figure place of section
2(N/M) round up, wherein N is the maximum PCIE number of devices that described many PCIE device systems is supported, M is the figure place of interrupt status register.
The value of interrupt status register changes by the change of preset rules with the value of said interrupt register, is specially:
According to the value of interrupt status register selection section in the interrupt register, select corresponding interrupt status register; According to the value of selection section in interrupt status register position in the interrupt register, in the interrupt status register of selecting, select corresponding position; The value of institute's rheme of selecting is set to preset value, is used to identify the PCIE equipment generation interruption of this correspondence.
Such as, can use " 0 " and " 1 " two values to identify corresponding PCIE equipment respectively and not produce the state of interruption and the state that the generation of corresponding PCIE equipment is interrupted, promptly use " 1 " as preset value, be used to identify the PCIE equipment generation interruption of this correspondence.In the practical application, can not produce/produce interruption status with the corresponding PCIE equipment of other value sign, the embodiment of the invention does not limit this yet.In the present embodiment, with " 1 " as preset value, the PCIE equipment that is used to identify this correspondence produces and interrupts, as default value, the PCIE equipment that is used to identify this correspondence does not produce and interrupts describing for example with " 0 ".
Concrete, suppose interrupt register be 32 (certainly in the practical application, the figure place of interrupt register also can be 64 etc., can be definite according to the practical application scene, the embodiment of the invention is not done qualification to this.Here; The figure place of interrupt register is elected 32 demands that can satisfy existing many PCIE device systems usually as); The bit wide of interrupt status register can be elected 8,16, or 32 or the like as; The bit wide decision that the bit wide of interrupt status register is supported by PCIE master's bridge controller (Device Controller) of visit PLD usually; Here the bit wide of setting interrupt status register is M, and it is N that maximum PCIE that this many PCIE device systems is supported interrupt number, and the definition of two types of registers is following:
1) interrupt register: this register is divided into three sections, and first section is interrupt status register position selection section, is used for selecting a certain position in the interrupt status register, and the figure place of this section is Log
2M, i.e. 0～Log
2M-1; Second section is interrupt status register selection section, and the figure place of this section is Log
2(N/M), that is, and Log
2M～Log
2N-1.Other position in the interrupt register is the 3rd section, i.e. Log
2N～32 are used for keeping.The figure place of supposing interrupt status register is 32 (M=32), and the maximum PCIE device interrupt number that system supported is 128 (N=128), then needs 4 (128/32) individual interrupt status registers, and first section figure place is 5, is bit0～bit4 (Log
232-1), second section figure place is 2 (Log2 (128/32)), is bit5 (Log
232)～bit6 (Log
2128-1).That is to say, according to the value of the selection of interrupt status register described in interrupt register section, select corresponding interrupt status register: when the value of the interrupt status register selection section of interrupting register was 0x00, the 1st interrupt status register selected in expression; When the interrupt status register that interrupts register selected the value of section to be 0x01, the 2nd interrupt status register selected in expression; When the interrupt status register that interrupts register selected the value of section to be 0x10, the 3rd interrupt status register selected in expression; When the interrupt status register that interrupts register selected the value of section to be 0x11, the 4th interrupt status register selected in expression, or the like, the rest may be inferred, repeats no more.
Select the value of section according to the position of interrupt status register described in the interrupt register; In the interrupt status register of selecting, select corresponding position: when the interrupt status register position of interrupting register selected the value of section to be 00000 (scale-of-two), the 1st of this interrupt status register selected in expression; When the interrupt status register position of interrupting register selected the value of section to be 0x00001, the 2nd of this interrupt status register selected in expression; When the interrupt status register position of interrupting register selected the value of section to be 00010 (scale-of-two), the 3rd of this interrupt status register selected in expression; When the interrupt status register position of interrupting register selected the value of section to be 00011 (scale-of-two), the 4th of this interrupt status register selected in expression, or the like, the rest may be inferred, repeats no more.
2) interrupt status register: the MSI interrupt vector of the in store correspondence of each of this register number; Wherein the MSI interrupt vector of the PCIE equipment preserved of first interrupt status register number is 1～32; The MSI interrupt vector of the PCIE equipment that second interrupt register preserved number is 33～64, by that analogy.The value of each of this register can be passed through the interrupt register setting, and when the value of interrupting register was modified, corresponding position will be set to 1 in the interrupt status register.
Step S302: interrupt register is mapped in the PCIE space, is each PCIE equipment disposition interrupt vector number, and interrupt register number is write each PCIE equipment in the mapping address in PCIE space and interrupt vector.
Through the value of related register is set, interrupt register is mapped in the PCIE space, so that miscellaneous equipment can be visited in the system.
Preferably, number select section and interrupt status register position to select the definition of section, calculate according to the interrupt register interrupt status register for the interrupt vector of each PCIE equipment disposition, such as:
The interrupt vector number that is the 1st corresponding PCIE devices allocation of the 1st interrupt status register is 0x0000000, and wherein bit0-bit4 is the value that section is selected in the interrupt status register position, and bit5-bit6 is the value that interrupt status register is selected section.
The interrupt vector that is the 1st corresponding PCIE devices allocation of the 2nd interrupt status register number is 0100000 (scale-of-two), and wherein bit0-bit4 is the value that section is selected in the interrupt status register position, and bit5-bit6 is the value that interrupt status register is selected section.
The interrupt vector number that is the 2nd corresponding PCIE devices allocation of the 1st interrupt status register is 0x0000001, and wherein bit0-bit4 is the value that section is selected in the interrupt status register position, and bit5-bit6 is the value that interrupt status register is selected section.
Or the like, the rest may be inferred, repeats no more.
In the embodiment of the invention, when PCIE equipment is supported the MSI interrupt mode, the mapping address of interrupt register in the PCIE space write in the Msi_Addr register of PCIE equipment; Interrupt vector number is write in the Msi_Data register of PCIE equipment.
And when PCIE equipment is not supported the MSI interrupt mode, interrupt register number is write respectively in two registers of PCIE equipment in the mapping address in PCIE space and interrupt vector; And need pre-configured said PCIE equipment when producing interruption; Transmission is carried in advance and to be the interrupt vector of said PCIE equipment disposition number and the interrupt register notification message at the mapping address in PCIE space, and does not directly adopt the interrupt mode of conventional I NTA, INTB, INTC, INTD.
It is thus clear that; When PCIE equipment is not supported the MSI interrupt mode; Through pre-configured said PCIE equipment; It is sent a notification message to main control end when produce interrupting, with informing main control end for the interrupt vector of said PCIE equipment disposition number and interrupt register at the mapping address in PCIE space in advance, thereby can make main control end CPU need not to share the interrupt status register that interrupt handling routine detects a plurality of PCIE equipment of sharing this interruption one by one; Shorten the interruption time-delay of handling the PCIE equipment of not supporting the MSI interrupt mode greatly, improve the system break treatment effeciency.
The order of conditioning step S301 and step S302 not in the embodiment of the invention can first execution in step S301, execution in step S302 again; Also can first execution in step S302, execution in step S301 again; Can also carry out simultaneously.
Step S303: in each PCIE equipment, register interrupt handling routine.
Preferably, the method for registration interrupt handling routine can be in PCIE equipment:
(1) will number add that side-play amount obtains the CPU interrupt number for the interrupt vector of PCIE equipment disposition; Wherein side-play amount is the number of interruptions that main control end CPU self supports.Because interrupt register that is provided with in the PLD and interrupt status register interrupt for the MSI of new expansion outside main control end CPU; Then for main control end CPU; The MSI that expands in the PLD interrupts employed interrupt number, should be and on the basis of interrupt vector number, adds the MSI number of interruptions that PCIE master's bridge self is supported.
(2) said PCIE device driver is to said CPU interrupt number registration interrupt handling routine.
Step S304: when PCIE equipment produce to interrupt, send a notification message, carry in the said notification message in advance and to be the interrupt vector of said PCIE equipment disposition number and interrupt register mapping address in the PCIE space.
Preferably, when PCIE equipment was supported the MSI interrupt mode, said notification message was specially MSI message.
Step S305: said PCIE master's bridge writes said interrupt vector number in the interrupt register in said PLD after receiving notification message.
When in interrupting register, writing interrupt vector, the value of interrupt status register just can correspondingly change, and is concrete: at first, according to the value of the selection of interrupt status register described in interrupt register section, select corresponding interrupt status register; Once more, according to the value of the position of interrupt status register described in interrupt register selection section, in the interrupt status register of selecting, select corresponding position; At last, the value of institute's rheme of selecting is set to preset value (such as putting 1), is used to identify the PCIE equipment generation interruption of this correspondence.
Interrupt register is used for writing down the data that notification message sends over (interrupt vector number), and is set to 1 according to a certain position in the corresponding interrupt status register of the content of data, has so just write down the PCIE equipment of corresponding generation interruption.
When a plurality of PCIE equipment produce interruption simultaneously; A plurality of interrupt vector orders that PCIE master's bridge will receive write in the interrupt register; Whenever write in the interrupt register interrupt vector number; Interrupt status register can write down the PCIE equipment of the generation interruption of this interrupt vector correspondence, then after a plurality of interrupt vector orders write interrupt register, though the value that writes after in the interrupt register can cover previous value; But but will all produce in the interrupt status register interruption the PCIE equipment records get off; Such as, if the corresponding PCIE equipment of interrupt vector number 0000000 (scale-of-two), PCIE equipment that interrupt vector number 0100000 (scale-of-two) is corresponding, and the corresponding PCIE equipment of interrupt vector number 0000001 (scale-of-two) produce interruption simultaneously, then main control end CPU writes interrupt register with interrupt vector number 0000000 (scale-of-two), 0100000 (scale-of-two), 0000001 (scale-of-two) in order; When with interrupt vector number 0000000 (scale-of-two) when writing interrupt register; Put 1 for the 1st of corresponding the 1st interrupt status register, when interrupt vector number 0100000 (scale-of-two) when writing interrupt register, put 1 for the 1st of corresponding the 2nd interrupt status register; When with interrupt vector number 0000001 (scale-of-two) when writing interrupt register; Put 1 for the 2nd of corresponding the 1st interrupt status register, then after the interrupt vector that receives number is all write interrupt register, (value in the interrupt status register can not cover just to have write down the PCIE equipment of whole generations interruptions in the corresponding interrupt status register; Only after the interruption of correspondence is processed, just can be fallen clearly, put 0 again).
Step S306: when the value of said interrupt status register changed, said PLD triggered interrupt request through interrupt pin to main control end CPU.
Said main control end CPU is that each interrupt status register distributes an interrupt pin in the PLD; When the value of certain interrupt status register changed, said PLD triggered interrupt request through the corresponding interrupt pin of this interrupt status register to main control end CPU.Among Fig. 5, the corresponding interrupt pin of each interrupt status register, when in interrupting status register, having at least 1 to be put 1, the interrupt pin that this interrupt register is corresponding just produces interrupts.
But in some system,, can distribute an interrupt pin for a plurality of interrupt status registers in such system because the pin of PLD or the restriction of system break number can't provide an interrupt pin for each interrupt status register.When main control end CPU is that PLD distributes an interrupt pin, also be provided with main interrupt status register in the then said PLD, said interrupt pin is linked to each other with main interrupt status register; Each interrupt status register in said main interrupt register, have one corresponding with it, when the value of certain interrupt status register changed, the value that corresponding position is set in the said main interrupt status register was about definite value (such as putting 1); Then when the value of main interrupt status register changed, said PLD triggered interrupt request through said interrupt pin to main control end CPU.Referring to Fig. 6; For a plurality of interrupt status registers provide an interrupt pin; Need to increase a main interrupt status register this moment, each interrupt status register main interrupt status register all have one corresponding with it, when having at least one to be set to 1 in certain interrupt status register; Corresponding positions corresponding with it in main interrupt register will be set to 1, and this interrupt pin will produce interruption when having at least one to be 1 in the main interrupt register simultaneously.
Step S307: main control end CPU calls and carries out the interrupt handling routine of registered in advance according to the value of interrupt status register; And revise the value of interrupt status register, with the interruption status of recovering the corresponding PCIE equipment of said interrupt handling routine for not producing interruption status.
Preferably, the interrupt handling routine that calls and carry out registered in advance according to the value of interrupt status register can comprise the steps:
(1) calculates the interrupt vector that writes in the said interrupt register number according to the value of said interrupt status register.
(2) said interrupt vector number is added the above side-play amount and obtain the CPU interrupt number.
(3) call and carry out the interrupt handling routine of registering to said CPU interrupt number.
For logical organization shown in Figure 5; The interrupt pin of in the interrupt distribution function, interrupting according to initiation; The interrupt status register that confirm to cause interrupts reads the value of this interrupt status register then, further confirms to produce the MSI interrupt vector of interrupting number; Calculate corresponding CPU interrupt number, call and carry out the interrupt handling routine corresponding at last with this CPU interrupt number.
For logical organization shown in Figure 6; In the interrupt distribution function, at first to read main interrupt status register; According to the interrupt status register that its content confirm to cause is interrupted, read the value of this interrupt status register then, further confirm to produce the MSI interrupt vector of interrupting number; Calculate corresponding CPU interrupt number, call and carry out the interrupt handling routine corresponding at last with this CPU interrupt number.
In the present embodiment; Revise the value of interrupt status register; Interruption status to recover the corresponding PCIE equipment of said interrupt handling routine is not specially for producing interruption status, and the value of the position in the interrupt status register that the interrupt handling routine that is called and carries out is corresponding puts 0.
In the embodiment of the invention, main control end CPU can also number be provided with priority for different interrupt vectors, and then main control end CPU just can judge by different priority orders and produces the CPU interrupt number that interrupts, and further expand the application of present embodiment.
Because in many PCIE device systems of the embodiment of the invention; Interrupt register is set in advance writes down the interrupt status register that produces the PCIE equipment that interrupts, and the value of said interrupt status register can change by the change of preset rules with the value of said interrupt register with being used to.Like this; When a plurality of PCIE equipment produce interruption simultaneously; After main control end receives a plurality of MSI message, can a plurality of interrupt vector orders be write in the interrupt register, whenever write in the interrupt register interrupt vector number; Interrupt status register can write down the PCIE equipment of the generation interruption of this interrupt vector correspondence; Then after a plurality of interrupt vector orders write interrupt register, though the value that writes after in the interrupt register can cover previous value, but will all produce in the interrupt status register interruption the PCIE equipment records get off; Main control end just can be handled produced simultaneously a plurality of interruption according to the value in the interrupt status register, thereby makes many PCIE device systems can handle the produced simultaneously interruption of a plurality of PCIE equipment.
Further; When PCIE equipment is not supported the MSI interrupt mode; Through pre-configured said PCIE equipment; It is sent a notification message to main control end when produce interrupting, with informing main control end for the interrupt vector of said PCIE equipment disposition number and interrupt register at the mapping address in PCIE space in advance, thereby can make main control end need not to share the interrupt status register that interrupt handling routine detects a plurality of PCIE equipment of sharing this interruption one by one; Shorten the interruption time-delay of handling the PCIE equipment of not supporting the MSI interrupt mode greatly; The value that when interruption generating, only need read in the interrupt status register can confirm to produce the PCIE equipment of interruption, and the time delay of Interrupt Process can not increase along with the increasing of PCIE equipment in the system, thereby improves the system break treatment effeciency.
Need to prove; In this article; Term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability; Thereby make to comprise that process, method, article or the equipment of a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or also be included as this process, method, article or equipment intrinsic key element.Under the situation that do not having much more more restrictions, the key element that limits by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises said key element and also have other identical element.
One of ordinary skill in the art will appreciate that; Realize that all or part of step in the foregoing description method is to instruct relevant hardware to accomplish through program; Described program can be stored in the computer read/write memory medium; This program comprises that some instructions are in order to carry out the described method of each embodiment of the present invention when carrying out.Storage medium described here, as: ROM/RAM, magnetic disc, CD etc.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All any modifications of within spirit of the present invention and principle, being done, be equal to replacement, improvement etc., all be included in protection scope of the present invention.
Claims (8)
1. quick peripheral hardware interconnect standard PCIE device systems interruption processing method; It is characterized in that; Interrupt register is set in advance writes down the interrupt status register that produces the PCIE equipment that interrupts, the interruption status of a PCIE equipment of the corresponding sign of the value of each in the said interrupt status register with being used to; Said interrupt register comprises at least: interrupt status register is selected section, is used to select interrupt status register; Select section with the interrupt status register position, be used for selecting the position of interrupt status register;
Interrupt register is mapped in the PCIE space, is each PCIE equipment disposition interrupt vector number, and interrupt register number is write each PCIE equipment in the mapping address in PCIE space and interrupt vector;
The value of said interrupt status register changes by the change of preset rules with the value of said interrupt register; Be specially,, select corresponding interrupt status register according to the value of interrupt status register selection section in the interrupt register; According to the value of selection section in interrupt status register position in the interrupt register, in the interrupt status register of selecting, select corresponding position; The value of institute's rheme of selecting is set to preset value, and whether the PCIE equipment that is used to identify this correspondence produces interruption;
Said method comprises:
When PCIE equipment produce to interrupt, send a notification message, carry in the said notification message in advance and to be the interrupt vector of said PCIE equipment disposition number and interrupt register mapping address in the PCIE space;
Main control end number writes the corresponding interrupt register of said mapping address with said interrupt vector after receiving notification message; Call and carry out the interrupt handling routine of registered in advance according to the value of interrupt status register, and revise the value of interrupt status register, with the interruption status of recovering the corresponding PCIE equipment of said interrupt handling routine for not producing interruption status.
2. quick peripheral hardware interconnect standard PCIE device systems interruption processing method according to claim 1; It is characterized in that; Said main control end comprises central processor CPU, and the PCIE master's bridge that links to each other with said CPU is used for said CPU and supports cpu bus data layout and each PCIE equipment to support the data-switching between data layout; PLD with linking to each other with said CPU is provided with interrupt register and interrupt status register in said PLD.
3. quick peripheral hardware interconnect standard PCIE device systems interruption processing method according to claim 2 is characterized in that, said main control end number writes the corresponding interrupt register of said mapping address with said interrupt vector after receiving notification message; Call and carry out the interrupt handling routine of registered in advance according to the value of interrupt status register, and revise the value of interrupt status register, for not producing interruption status, be specially with the interruption status of recovering the corresponding PCIE equipment of said interrupt handling routine:
Said PCIE master's bridge writes said interrupt vector number in the interrupt register in said PLD after receiving notification message;
When the value of said interrupt status register changed, said PLD triggered interrupt request through interrupt pin to said CPU;
Said CPU calls and carries out the interrupt handling routine of registered in advance according to the value of interrupt status register, and revises the value of interrupt status register, with the interruption status of recovering the corresponding PCIE equipment of said interrupt handling routine for not producing interruption status.
4. quick peripheral hardware interconnect standard PCIE device systems interruption processing method according to claim 3; It is characterized in that; When said PCIE equipment support information signal interruption MSI interrupt mode, the mapping address of interrupt register in the PCIE space write in the address register register of PCIE equipment; Interrupt vector number is write in the data register register of PCIE equipment; And said notification message is specially MSI message.
5. quick peripheral hardware interconnect standard PCIE device systems interruption processing method according to claim 4; It is characterized in that; When said PCIE equipment is not supported the MSI interrupt mode; Pre-configured said PCIE equipment sends to carry in advance and is the interrupt vector of said PCIE equipment disposition number and the interrupt register notification message at the mapping address in PCIE space when produce interrupting; And interrupt register number write respectively in two registers of PCIE equipment in the mapping address in PCIE space and interrupt vector.
6. quick peripheral hardware interconnect standard PCIE device systems interruption processing method according to claim 3 is characterized in that, with the interruption status of a PCIE equipment of the corresponding sign of the value of each in the said interrupt status register; Said interrupt register comprises at least:
Interrupt status register is selected section, is used to select interrupt status register; With
Section is selected in the interrupt status register position, is used for selecting the position of interrupt status register; Then
The value of said interrupt status register changes with the change of the value of said interrupt register by preset rules and is specially:
According to the value of the selection of interrupt status register described in interrupt register section, select corresponding interrupt status register;
According to the value of the position of interrupt status register described in interrupt register selection section, in the interrupt status register of selecting, select corresponding position;
The value of institute's rheme of selecting is set to preset value, is used to identify the PCIE equipment generation interruption of this correspondence.
7. quick peripheral hardware interconnect standard PCIE device systems interruption processing method according to claim 6 is characterized in that the figure place of a plurality of interrupt status registers is all identical, then
It is Log that said interrupt status register is selected the figure place of section
2(N/M), work as Log
2When (N/M) being not integer, it is Log that said interrupt status register is selected the figure place of section
2(N/M) round up, wherein N is the maximum PCIE number of devices that described many PCIE device systems is supported, M is the figure place of interrupt status register.
8. quick peripheral hardware interconnect standard PCIE device systems interruption processing method according to claim 6 is characterized in that, the registration interrupt handling routine is specially:
To number add that side-play amount obtains the CPU interrupt number for the interrupt vector of PCIE equipment disposition; Said side-play amount is the number of interruptions that said CPU self supports;
Said PCIE device driver is to said CPU interrupt number registration interrupt handling routine;
The interrupt handling routine that registered in advance was called and carried out to said value according to interrupt status register is specially:
Calculate the interrupt vector that writes in the said interrupt register number according to the value of said interrupt status register;
Said interrupt vector number is added the above side-play amount obtain the CPU interrupt number;
Call and carry out interrupt handling routine to said CPU interrupt number registration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910250798 CN101872330B (en) | 2009-11-04 | 2009-12-11 | Interrupt processing method of multi-PCIE (Peripheral Component Interface Express) equipment system |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910209358.4 | 2009-11-04 | ||
| CN200910209358 | 2009-11-04 | ||
| CN 200910250798 CN101872330B (en) | 2009-11-04 | 2009-12-11 | Interrupt processing method of multi-PCIE (Peripheral Component Interface Express) equipment system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101872330A CN101872330A (en) | 2010-10-27 |
| CN101872330B true CN101872330B (en) | 2012-07-25 |
Family
ID=42997197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910250798 Active CN101872330B (en) | 2009-11-04 | 2009-12-11 | Interrupt processing method of multi-PCIE (Peripheral Component Interface Express) equipment system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101872330B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105993009A (en) * | 2013-11-18 | 2016-10-05 | 华为技术有限公司 | Method and apparatus for delivering msi-x interrupts through non-transparent bridges to computing resources in pci-express clusters |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9128920B2 (en) * | 2011-11-30 | 2015-09-08 | Marvell World Trade Ltd. | Interrupt handling systems and methods for PCIE bridges with multiple buses |
| CN103440188B (en) * | 2013-08-29 | 2016-09-28 | 福建星网锐捷网络有限公司 | The detection method of a kind of PCIE hardware fault and device |
| JP6110560B2 (en) | 2014-04-02 | 2017-04-05 | 華為技術有限公司Ｈｕａｗｅｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．，Ｌｔｄ． | Method, apparatus and system for handling PCIe link failures |
| CN104159325B (en) * | 2014-08-22 | 2017-11-28 | 福建三元达网络技术有限公司 | WLAN outdoor wireless access point devices based on LTE network |
| CN104679687B (en) * | 2014-12-19 | 2018-04-20 | 杭州华为数字技术有限公司 | A kind of method and device for identifying interrupt source |
| CN104683229A (en) * | 2015-02-04 | 2015-06-03 | 金万益有限公司 | Method for quickly transmitting data |
| CN105550091A (en) * | 2015-09-03 | 2016-05-04 | 刘晓建 | Monitoring card for PCI (Peripheral Component Interface)/PCIe (Peripheral Component Interface Express) device status and Gigabit network card link monitoring method |
| CN105426337A (en) * | 2015-10-29 | 2016-03-23 | 上海飞斯信息科技有限公司 | Universal processing module |
| US10565004B2 (en) * | 2016-02-04 | 2020-02-18 | Hewlett Packard Enterprise Development Lp | Interrupt and message generation independent of status register content |
| CN107168895B (en) * | 2016-03-07 | 2020-03-13 | 龙芯中科技术有限公司 | Method, bridge piece and system for controlling external equipment |
| CN108628782B (en) * | 2018-03-27 | 2024-03-15 | 天津麒麟信息技术有限公司 | Implementation method of interrupt switching mechanism based on Feiteng platform |
| CN111723032B (en) * | 2019-03-21 | 2021-09-24 | 杭州宏杉科技股份有限公司 | Interrupt management and control method and electronic equipment |
| CN110399324A (en) * | 2019-06-28 | 2019-11-01 | 苏州浪潮智能科技有限公司 | It interrupts converter and interrupts conversion method |
| CN111078597B (en) * | 2019-12-04 | 2021-07-30 | 江苏芯盛智能科技有限公司 | Interrupt message generation device and method and end equipment |
| CN112631883B (en) * | 2020-12-15 | 2023-10-13 | 成都海光集成电路设计有限公司 | PCIe data transmission pressure manufacturing method, system and electronic equipment |
| CN114253681B (en) * | 2021-11-18 | 2024-10-22 | 威胜信息技术股份有限公司 | Interrupt registration and sharing management method and electronic equipment |
| CN114546912A (en) * | 2022-01-17 | 2022-05-27 | 飞腾信息技术有限公司 | Interrupt expansion method for server system |
| CN114265800B (en) * | 2022-03-02 | 2022-06-07 | 山东云海国创云计算装备产业创新中心有限公司 | Interrupt message processing method and device, electronic equipment and readable storage medium |
| CN118260224A (en) * | 2022-12-28 | 2024-06-28 | 华为技术有限公司 | Interrupt reporting method, interrupt configuration method and device |
| CN117873672A (en) * | 2023-12-26 | 2024-04-12 | 象帝先计算技术(重庆)有限公司 | Interrupt processing system, interrupt processing component, interrupt processing device, interrupt processing method, interrupt processing apparatus, and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1052202A (en) * | 1989-11-03 | 1991-06-12 | 国际商业机器公司 | Programmable interrupt controller |
| CN1298519A (en) * | 1998-04-29 | 2001-06-06 | 英特尔公司 | Interrupt controller |
| CN1894680A (en) * | 2003-12-19 | 2007-01-10 | 英特尔公司 | Driver transparent message signaled interrupts |
| CN101211323A (en) * | 2006-12-28 | 2008-07-02 | 联想(北京)有限公司 | Hardware interruption processing method and processing unit |
| CN100416530C (en) * | 2003-08-09 | 2008-09-03 | 得州仪器公司 | System for signaling serialized interrupts using message signaled interrupts |
-
2009
- 2009-12-11 CN CN 200910250798 patent/CN101872330B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1052202A (en) * | 1989-11-03 | 1991-06-12 | 国际商业机器公司 | Programmable interrupt controller |
| CN1298519A (en) * | 1998-04-29 | 2001-06-06 | 英特尔公司 | Interrupt controller |
| CN100416530C (en) * | 2003-08-09 | 2008-09-03 | 得州仪器公司 | System for signaling serialized interrupts using message signaled interrupts |
| CN1894680A (en) * | 2003-12-19 | 2007-01-10 | 英特尔公司 | Driver transparent message signaled interrupts |
| CN101211323A (en) * | 2006-12-28 | 2008-07-02 | 联想(北京)有限公司 | Hardware interruption processing method and processing unit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105993009A (en) * | 2013-11-18 | 2016-10-05 | 华为技术有限公司 | Method and apparatus for delivering msi-x interrupts through non-transparent bridges to computing resources in pci-express clusters |
| CN105993009B (en) * | 2013-11-18 | 2019-04-19 | 华为技术有限公司 | The method and apparatus that MSI-X is interrupted are transmitted by computing resource of the non-transparent bridge into PCIe cluster |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101872330A (en) | 2010-10-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101872330B (en) | Interrupt processing method of multi-PCIE (Peripheral Component Interface Express) equipment system | |
| KR100762388B1 (en) | Low-overhead processor interfacing | |
| CN101390057B (en) | Two-level interrupt service routine | |
| JPWO2009133669A1 (en) | Virtual machine control device, virtual machine control method, and virtual machine control program | |
| CN101634974A (en) | Method, device and system for processing multiple interrupt types | |
| JP5507317B2 (en) | Microcomputer and interrupt control method | |
| CN103455363A (en) | Command processing method, device and physical host of virtual machine | |
| CN103077140A (en) | Communication method and communication device for motion control card of robot and host | |
| CN103019848B (en) | Method for realizing peripheral component interconnect (PCI) bus non-vector interrupt | |
| CN111913898A (en) | PCIE root complex message interrupt generating method using end point | |
| KR101673247B1 (en) | Processor with assignable general purpose register set | |
| CN102622274A (en) | Computer device and interrupt task allocation method thereof | |
| CN113282397B (en) | Interrupt processing method and equipment for peripheral | |
| CN102473136A (en) | Memory management device, memory management method, memory management program, computer-readable recording medium storing the memory management program and integrated circuit | |
| CN101645051A (en) | GPIO interrupt control device, chip and GPIO interrupt control method | |
| KR100528476B1 (en) | Interupt processing circuit of computer system | |
| CN101814011A (en) | Usb host controller and the control method that is used for usb host controller | |
| CN102117261B (en) | Communication method between inner processors of chip | |
| US10162530B2 (en) | Computer and computer system for collision determination of a command identifier | |
| CN102043741A (en) | Circuit and method for pipe arbitration | |
| JP2010244164A (en) | Dma controller, information processor, and dma management method | |
| CN104123261B (en) | A kind of electronic equipment and information transferring method | |
| JP2014038438A (en) | Arithmetic processing unit, information processing apparatus and interruption control method | |
| CN217085748U (en) | Processor, mainboard and electronic equipment | |
| CN108093093B (en) | Method and device for updating address table of destination equipment in source equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20101027 Assignee: The anti-Technology Service Co., Ltd in guarantor Tai'an, Haikang, Fuyang Assignor: Hangzhou Hikvision Digital Technology Co., Ltd. Contract record no.: 2014990000024 Denomination of invention: Interrupt processing method of multi-PCIE (Peripheral Component Interface Express) equipment system Granted publication date: 20120725 License type: Exclusive License Record date: 20140113 |
|
| LICC | Enforcement, change and cancellation of record of contracts on the licence for exploitation of a patent or utility model |