CN101833186B - Pixel circuit of display device - Google Patents
Pixel circuit of display device Download PDFInfo
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- CN101833186B CN101833186B CN2009101266590A CN200910126659A CN101833186B CN 101833186 B CN101833186 B CN 101833186B CN 2009101266590 A CN2009101266590 A CN 2009101266590A CN 200910126659 A CN200910126659 A CN 200910126659A CN 101833186 B CN101833186 B CN 101833186B
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Abstract
The invention relates to a pixel circuit of a display device. The pixel circuit comprises a first memory module and a switch module, wherein the switch module consists of a plurality of switches; the first end of the first memory module receives pixel signals; the second end of the first memory module is coupled with a first voltage; the first memory module is used for storing the pixel signals; the switch module comprises a first switch and a second switch; the first switch and the second switch are switched on according to a first signal and a second signal respectively; and the input ends of the first switch and the second switch are coupled with data wires, while the output ends are coupled with the first memory module. The cooperation of the first switch and the second switch has the advantage of avoiding the influence of subjective effect during transmitting the pixel signals.
Description
Technical field
The present invention relates to a kind of image element circuit of display device, and relate in particular to a kind of increase and pass through the voltage range of scanning switch, and be increased under the low frequency of operation image element circuit in order to the electric capacity of the memory module of storage pixel signal to the picture element signal of pixel electrode.
Background technology
The display panel of LCD is made up of the array of pixels with a plurality of image element circuits.Figure 1A is the circuit diagram of conventional pixel circuit.Please refer to Figure 1A, image element circuit 100A comprises switch module 111A, reaches memory capacitance 112A.Switch module 111A realizes that by nmos pass transistor its grid couples sweep trace SC to receive sweep signal, and its first source/drain electrode couples data line DA with the reception picture element signal, with and second source/drain electrode couple pixel electrode Pix.Memory capacitance 112A realizes by nmos pass transistor that also its grid couples pixel electrode Pix, and its first and second source/drain electrode couples a voltage (for example voltage of public electrode).When making switch module 111A conducting when the sweep signal activation, the picture element signal on the data line DA is transferred into pixel electrode Pix and memory capacitance 112A is advanced in storage, with turning to of control liquid crystal.
As everyone knows, nmos pass transistor is made in the substrate of P type, couples negative supply voltage VSSA's.If between the negative supply voltage VSSA, then owing to the influence of main body effect, not all picture element signal in this voltage range can pass through switch module 111A to be sent to pixel electrode Pix to the voltage range of picture element signal at positive voltage VDDA.That is to say to have only voltage range, just can be transferred into pixel voltage Pix, and can't be transmitted to the picture element signal of the high voltage range of voltage VDDA at voltage VDDA-Δ V at the picture element signal of voltage VSSA to the voltage VDDA-Δ V.Hence one can see that, and the voltage range of passing through switch module 111A is restricted.
In addition, the memory capacitance 112A NMOS electric capacity that is otherwise known as, and its electric capacity is along with changing under grid the is in low frequency of operation.Fig. 1 C is the electric capacity curve map of mos capacitance in low frequency of operation.Please refer to Fig. 1 C, curve 101 has been drawn the electric capacity Cgb of NMOS electric capacity.When grid voltage Vg less than zero the time, can between grid and substrate, form accumulation layer with as electric capacity.When grid voltage Vg greater than zero, but during less than critical voltage Vtn, can in the substrate under the grid oxic horizon, form vague and general layer, and the thickness of vague and general layer can increase along with the increase of grid voltage, to reduce the electric capacity Cgb of NMOS electric capacity.
At the same time, the electric capacity Cgb of NMOS electric capacity is made of the grid capacitance vague and general layer capacitance that is connected in series, and wherein grid capacitance is formed between grid and vague and general layer two parallel plane.In other words, under low frequency of operation, when grid voltage Vg greater than zero and during less than critical voltage Vtn, the electric capacity Cgb of NMOS electric capacity can't reach desired electric capacity.As grid voltage Vg during greater than critical voltage Vtn, channel layer can be formed in the substrate under the grid oxic horizon, and the electric capacity of NMOS electric capacity is made of the grid capacitance that is formed between these two parallel planes of grid and channel layer.
Figure 1B is the circuit diagram of another conventional pixel circuit.Please refer to Figure 1B, switch module 111B and memory capacitance 112B realize that by the PMOS transistor wherein the PMOS transistor is made, and couples positive voltage VDDA in the substrate of N type.Because the influence of main body effect, have only voltage range just can be transferred into pixel voltage Pix to the picture element signal in the voltage VDDA, and can't be transmitted to the picture element signal of the low voltage range of voltage VSSA+ Δ V at voltage VSSA at voltage VSSA+ Δ V.Hence one can see that, and the voltage range of passing through switch module 111 is restricted.Please refer to Fig. 1 C, curve 102 has been drawn the electric capacity Cgb of the memory capacitance 112 that realizes on the PMOS transistor, and memory capacitance 112 is called as PMOS electric capacity.Similarly, under low frequency of operation, when grid voltage Vg less than zero and during greater than critical voltage Vtp, the electric capacity Cgb of PMOS electric capacity can't reach desired electric capacity.Above-mentioned voltage limit and electric capacity deficiency then become the problem that the circuit design utmost point of image element circuit need solve.
Summary of the invention
The invention provides a kind of image element circuit, a plurality of switches that its utilization is connected in parallel transmit the picture element signal with big voltage range with the foundation sweep signal, to avoid the influence of main body effect.In addition, the present invention also provides a kind of image element circuit, and its increase is coupled to the equivalent capacity of memory module of pixel electrode with the storage pixel signal.
The present invention proposes a kind of image element circuit of display device, and it comprises first memory module and switch module.First memory module has first end and second end, in order to the storage pixel signal, and the plain signal of the first termination reproduced image of first memory module wherein, second end of first memory module couples first voltage.Switch module is made up of a plurality of switches, and it comprises first switch and second switch.First switch has input end and output terminal, and the conducting according to first signal, and wherein the input end of first switch couples data line, and the output terminal of first switch couples first memory module.Second switch has input end and output terminal, and the conducting according to secondary signal, and wherein the input end of second switch couples data line, and the output terminal of second switch couples first memory module.
In one embodiment of the invention, described first switch and second switch are respectively nmos pass transistor and PMOS transistor.
In one embodiment of the invention, image element circuit further comprises multiplexer, and it produces first signal and secondary signal according to sweep signal.And, the conducting synchronously of first switch and second switch according to first signal and secondary signal.
The present invention also proposes a kind of image element circuit of display device, and it comprises first switch, first memory module and second memory module.First switch has input end and output terminal, and wherein the input end of first switch receives picture element signal, and the conducting according to sweep signal of first switch.First memory module has first end and second end, and in order to the storage pixel signal, wherein first end of first memory module couples the output terminal of first switch, and second end of first memory module couples first voltage.Second memory module has first end and second end, and in order to the storage pixel signal, wherein first end of second memory module couples the output terminal of first switch, and second end of second memory module couples second voltage.
In one embodiment of the invention, described first memory module and second memory module are respectively NMOS electric capacity and PMOS electric capacity.
The invention provides a kind of image element circuit, it comprises first and second switch that is connected in parallel, to guarantee that the picture element signal of voltage range between positive voltage and negative supply voltage basically can be all by switch module to the first memory module, to avoid the influence of main body effect.In addition, the invention provides another image element circuit, it comprises first memory module and second memory module, and an end of first and second memory module is coupled to the output terminal of first switch, comes the storage pixel signal in order to increase equivalent capacity.
For making above-mentioned feature and advantage of the present invention to become apparent, embodiment cited below particularly, and conjunction with figs. is done following detailed description.
Description of drawings
Figure 1A is the circuit diagram of conventional pixel circuit.
Figure 1B is the circuit diagram of another conventional pixel circuit.
Fig. 1 C is the electric capacity curve map of mos capacitance under low frequency of operation.
Fig. 2 A is the circuit diagram according to the image element circuit of one embodiment of the invention.
Fig. 2 B is the curve map according to the equivalent capacity of memory module under low frequency of operation of Fig. 2 A embodiment.
Fig. 3 is the circuit diagram according to the image element circuit of another embodiment of the present invention.
Fig. 4 is the circuit diagram according to the image element circuit of further embodiment of this invention.
Embodiment
Be applied to display device at this hypothesis positive voltage VDDA and negative supply voltage VSSA, for example the voltage of LCD.The source electrode driver of display device can utilize the voltage range between positive voltage VDDA and negative supply voltage VSSA, drives turning to and the gray level of show image of liquid crystal.And increase drives the voltage range of liquid crystal, the easier identification of the gray level that human eye is experienced.Yet the switch module of image element circuit utilizes MOS transistor to realize, often owing to main body effect, and restriction drives the voltage range of liquid crystal.In addition, the memory capacitance of image element circuit can utilize mos capacitance to realize, when the voltage of picture element signal zero and the critical voltage of mos capacitance between the time, can cause the electric capacity deficiency of storage pixel signal.Following embodiments of the invention then provide a kind of circuit design of image element circuit to address the above problem.
Fig. 2 A is the circuit diagram according to the image element circuit of one embodiment of the invention.Please refer to Fig. 2 A, image element circuit 200 comprises switch SW 1 and memory module 221 and 222.The input end of switch SW 1 couples data line DA1 to receive picture element signal Vp, and its output terminal couples memory module 221 and 222.Switch SW 1 conducting according to sweep signal is in order to be sent to memory module 22 1 and 222 with the picture element signal Vp on the data line DA1, with storage pixel signal Vp.In the present embodiment, memory module 221 and 222 can be respectively NMOS electric capacity and PMOS electric capacity.First end of memory module 221 and second end are coupled to the output terminal and the negative supply voltage VSSA of switch SW 1 respectively.First end of memory module 222 and second end are coupled to the output terminal and the positive voltage VDDA of switch SW 1 respectively.
Please refer to Fig. 1 C, single memory module can utilize NMOS electric capacity or PMOS electric capacity to realize, its electric capacity can change along with the change of grid voltage (just being sent to the voltage of the picture element signal Vp of storage voltage), and when the voltage of picture element signal Vp be zero and critical voltage Vtn/Vtp between the time, can cause the electric capacity deficiency of storage pixel signal Vp.In the present embodiment, can utilize dissimilar mos capacitances to implement the equivalent capacity of memory module 221 and 222, in order to the voltage as picture element signal Vp be zero with critical voltage Vtn/Vtp between the time, increase is in order to the electric capacity of storage pixel signal Vp.Fig. 2 B is the curve map according to the equivalent capacity of memory module under low frequency of operation of the embodiment of Fig. 2 A.Please refer to Fig. 2 A and Fig. 2 B, memory module 221 and 222 equivalent capacity Ceq can be approximately equal to the average electrical capacity that uses NMOS electric capacity and use the electric capacity that PMOS electric capacity obtains respectively.Shown in Fig. 2 B, when the voltage of picture element signal Vp be zero and critical voltage Vtn/Vtp between the time, increase the equivalent capacity Ceq of memory module 221 and 222 effectively.
Fig. 3 is the circuit diagram according to the image element circuit of another embodiment of the present invention.Please refer to Fig. 3, image element circuit comprises switch module 310, memory module 321 and multiplexer 330, and wherein switch module 310 is made up of a plurality of switch.In the present embodiment, switch module 310 comprises switch T1 and T2, wherein can utilize nmos pass transistor and PMOS transistor to realize switch T1 and T2 respectively.Switch T1 and T2 are what be connected in parallel, and the conducting according to the first signal S11 that transmits self-scanning signal S1 and secondary signal S12 respectively.When the sweep signal activation, multiplexer 330 produces the secondary signal that has first signal of high logic and have low logic, with synchronous actuating switch T1 and T2.Then, the picture element signal Vp on the switch module 310 transmit data line DA1 to memory module 321 with storage pixel signal Vp.On the contrary, when sweep signal S1 was disabled, multiplexer 330 produces had first signal S11 of low logic and the secondary signal S12 with high logic, so that switch T1 and T2 are not conducting.Memory module 321 is the electric capacity of NMOS electric capacity or other type, the picture element signal Vp that transmits from switch module 310 in order to storage, and other type for example polysilicon layer-insulation course-polysilicon layer structure, metal level-insulation course-metal-layer structure.
By as can be known aforementioned, the voltage range that forms between voltage VDDA and voltage VSSA can't transmit the signal of whole voltage ranges by single switch, comprises the single switch that utilizes nmos pass transistor or PMOS transistor to be realized.In the present embodiment, switch T1 and T2 form a transmission lock, and conducting synchronously with transmit voltage range between voltage VDDA and voltage VSSA picture element signal Vp and can distortion.In other words, the picture element signal Vp with low-voltage can be undistorted to be sent to memory module 321 by switch T1, and have high-tension picture element signal Vp and can transmit and undistorted by switch T2.
Fig. 4 is the circuit diagram according to the image element circuit of further embodiment of this invention.Please refer to Fig. 4, the difference of Fig. 4 embodiment and Fig. 3 embodiment is that image element circuit further comprises memory module 422, and can utilize PMOS electric capacity to realize memory module 422.Please refer to Fig. 2 A and Fig. 2 B, when the voltage of picture element signal Vp be zero and critical voltage Vtn/Vtp between the time, memory module 421 and 422 connected mode can increase its equivalent electric capacity, in order to storage pixel signal Vp.
In sum, the image element circuit of the embodiment of the invention utilizes dissimilar MOS transistor to realize two switches, and two switches are connected in parallel, to guarantee that the picture element signal of voltage range between voltage VDDA and voltage VSSA basically can be all by switch module to the first memory module, to avoid the influence of main body effect.And increase the voltage range that drives image element circuit, because big voltage range can drive the gray level that image element circuit shows more images, therefore can improve display quality.In addition, image element circuit utilizes dissimilar mos capacitances to realize two memory modules, in order to increase the electric capacity of storage pixel signal.
Though the present invention as above discloses with embodiment; right its is not in order to limit the present invention; any person of an ordinary skill in the technical field; under the situation that does not break away from the spirit and scope of the present invention; can make some changes and improve, thus protection scope of the present invention should with appended claim scope was limited is as the criterion.
Claims (9)
1. the image element circuit of a display device comprises:
First memory module has first end and second end, and in order to the storage pixel signal, wherein first termination of this first memory module is received this picture element signal, and second end of this first memory module couples first voltage; And
Switch module is made up of a plurality of switches, comprising:
First switch has input end and output terminal, the conducting according to first signal, and wherein the input end of this first switch couples data line, and the output terminal of this first switch couples this first memory module; And
Second switch has input end and output terminal, the conducting according to secondary signal, and wherein the input end of this second switch couples this data line, and the output terminal of this second switch couples this first memory module;
Second memory module has first end and second end, and in order to store this picture element signal, wherein first end of this second memory module couples the output terminal of this first switch and this second switch, and second end of this second memory module couples second voltage;
Wherein, this first switch and this second switch are dissimilar MOS transistor, and this first memory module is dissimilar mos capacitances with this second memory module.
2. image element circuit as claimed in claim 1, wherein this first switch and this second switch conducting synchronously according to this first signal and this secondary signal.
3. image element circuit as claimed in claim 1, wherein this first switch and this second switch are respectively nmos pass transistor and PMOS transistor.
4. image element circuit as claimed in claim 1 further comprises:
Multiplexer produces this first signal and this secondary signal according to sweep signal.
5. the image element circuit of a display device comprises:
First switch has input end and output terminal, and wherein the input end of this first switch receives picture element signal, and this first switch conducting according to sweep signal;
First memory module has first end and second end, and in order to store this picture element signal, wherein first end of this first memory module couples the output terminal of this first switch, and second end of this first memory module couples first voltage; And
Second memory module has first end and second end, and in order to store this picture element signal, wherein first end of this second memory module couples the output terminal of this first switch, and second end of this second memory module couples second voltage;
Wherein, this first memory module and this second memory module are dissimilar mos capacitances.
6. image element circuit as claimed in claim 5, wherein this first memory module and this second memory module are made up of a plurality of mos capacitances.
7. image element circuit as claimed in claim 6, wherein this first memory module and this second memory module are respectively NMOS electric capacity and PMOS electric capacity.
8. image element circuit as claimed in claim 5 further comprises:
Second switch has input end and output terminal, and wherein the input end of this second switch couples the input end of this first switch, and the output terminal of this second switch couples the output terminal of this first switch;
Wherein, this first switch and this second switch are dissimilar MOS transistor.
9. image element circuit as claimed in claim 8, wherein this first switch and this second switch conducting synchronously according to this sweep signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101266590A CN101833186B (en) | 2009-03-10 | 2009-03-10 | Pixel circuit of display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009101266590A CN101833186B (en) | 2009-03-10 | 2009-03-10 | Pixel circuit of display device |
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| CN101833186A CN101833186A (en) | 2010-09-15 |
| CN101833186B true CN101833186B (en) | 2011-12-28 |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105185816A (en) | 2015-10-15 | 2015-12-23 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method, and display device |
| US11600234B2 (en) | 2015-10-15 | 2023-03-07 | Ordos Yuansheng Optoelectronics Co., Ltd. | Display substrate and driving method thereof |
| WO2021035415A1 (en) | 2019-08-23 | 2021-03-04 | 京东方科技集团股份有限公司 | Display device and manufacturing method therefor |
| WO2021035420A1 (en) | 2019-08-23 | 2021-03-04 | 京东方科技集团股份有限公司 | Display panel and manufacturing method therefor, and display device |
| WO2021035529A1 (en) | 2019-08-27 | 2021-03-04 | 京东方科技集团股份有限公司 | Electronic device substrate and method for manufacture and electronic device thereof |
| WO2021035414A1 (en) | 2019-08-23 | 2021-03-04 | 京东方科技集团股份有限公司 | Pixel circuit and driving method therefor, and display substrate and driving method therefor, and display device |
| US12120914B2 (en) | 2019-08-23 | 2024-10-15 | Boe Technology Group Co., Ltd. | Display device and manufacturing method thereof |
| CN114864647A (en) | 2019-08-23 | 2022-08-05 | 京东方科技集团股份有限公司 | Display device and method for manufacturing the same |
| KR20220049031A (en) | 2019-08-23 | 2022-04-20 | 보에 테크놀로지 그룹 컴퍼니 리미티드 | Display device, manufacturing method thereof, and driving board |
| CN111883530B (en) * | 2020-09-28 | 2020-12-25 | 南京晶驱集成电路有限公司 | Capacitor and preparation method thereof |
| CN114187876A (en) * | 2021-11-26 | 2022-03-15 | 绵阳惠科光电科技有限公司 | Pixel driving circuit, display panel and electronic equipment |
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