CN1018310B - Semiconductor device - Google Patents

Abstract

To elevate an open voltage when a light is applied by forming intermediate layers which have higher specific resistivities than adjoining semiconductor layers between semiconductor layers and between a semiconductor layer and an electrode. At the junction boundary (a) between a transparent electrode 2 and a P-type layer 3, the junction boundary (b) between the P-type layer 3 and an I-type layer 4 and the junction boundary (c) between the I-type layer 4 and the N-type layer 5 in a P-I-N type semiconductor device, intermediate layers which have higher specific resistivities then adjoining semiconductor layers are provided. With this constitution, an open voltage at the time of light application can be elevated.

Description

Semiconductor device

The present invention relates to semiconductor device, particularly relate to and be included in the semiconductor device that the photronic semiconductor device that has high open circuit voltage under the light radiation or photronic photoelectric conversion efficiency are improved.

Up to the present, as the material of optical-electrical converter, solar cell for example, employing be a kind of semi-conducting material such as a-Si that contains amorphous semiconductor: H, a-Si ₁-x: Cx: H, a-Si ₁-xGex: H, a-Si: F: H, a-Si ₁-xNxH, a-Ge: H, a-Si ₁-xGex: F: H, a-Si: H, uc-Si: H, uc-Si ₁-xGex: H(wherein x satisfies relational expression 0＜x＜1) or partly comprise the semi-conducting material of these amorphous semiconductors.

Common solar cell has the Pin of stratiform, (nip, pinpin ... or nipnip ... etc. structure, they are by sequentially depositing congener amorphous semiconductor or just deposit the different types of amorphous semiconductor with wide energy gap in their doped layer.Except owing to during device production and the distribution of the dopant that causes of later thermal diffusion, be uniformly on the thickness direction of the doping density in P type or n type layer, be generally 0.01 to 5 atomic percentage.

Fig. 5 shows the common semiconductor device that solar cell adopted that the Pin N-type semiconductor N that uses three-decker is made.In Fig. 5, digital 31 is glass substrate, and a transparency electrode 32 is adhered on it.On transparency electrode 32, form p type semiconductor layer 34 successively, i type semiconductor layer 35 and n type semiconductor layer 36.On n type semiconductor layer 36, form an electrode 37 then.Semiconductor device 38 is made of glass substrate 31, transparency electrode 32, p type semiconductor layer 34, i type semiconductor layer 35, n type semiconductor layer 36 and electrode 37.

On above-mentioned semiconductor device 38, the direction that light arrow in Fig. 9 is pointed out is injected glass substrate 31, and sees through glass substrate 31 and electrode 32, and irradiation is to p type semiconductor layer 34, i N-type semiconductor N 35 and n N-type semiconductor N 36 then.Because this irradiation, in each semiconductor layer and the hole is collected in the P type layer, therefore on transparency electrode 32, produce positive charge, on electrode 37, produce negative electrical charge.So just produce opto-electronic conversion, and semiconductor device 38 is had as photronic function.

Yet its shortcoming of semiconductor device with above structure is that it can not improve magnitude of voltage (representing with Voc below this) under open-circuit condition when photoirradiation, because this semiconductor device is being conditional aspect the raising internal electric field.

For example, utilizing under the above-mentioned device situation, when requiring electromotive force,, can be together in series a plurality of devices in order to overcome above-mentioned shortcoming greater than Voc.Yet, even so, suppose that the Voc of each device can improve, Chuan Lian device count can reduce so.Further, even if total all devices the conditional situation of area under, the method that increases by the area that makes each semiconductor layer can be suspected the performance of device and can improve greatly.

When noticing the structure of semiconductor device, effectively result of study is, we find under the situation of total area that does not increase all devices and series connection number of devices, found out than common semiconductor device have higher Voc and under specific voltage the semiconductor device of higher electric current (operating current), and realized this semiconductor device among the present invention.

In addition, generally all know, in common semiconductor device, when impurity density becomes big, diminish at p type semiconductor layer with at the contact resistance that reaches between the electrode of n type semiconductor layer and n type layer side between the electrode of P type layer side.It is desirable that this contact resistance is diminished, because when p type semiconductor layer and n type semiconductor layer during as photovoltaic devices, and solar cell for example, this resistance has reduced the duty factor of photovoltaic devices.Therefore, from then on viewpoint is set out, and wishes to increase impurity density.Yet, becoming too high as the impurity density of n type and p type semiconductor layer, the problem that can cause is that the characteristic as photovoltaic devices can degenerate, this is owing in those parts that contain impurity big optical absorption loss is arranged.

The present invention is in order to address the above problem, its objective is semiconductor device that a high open circuit voltage that has is provided and the semiconductor device that photoelectric conversion efficiency is improved under photoirradiation.

According to the present invention, it provides a kind of semiconductor device, and it is formed by first and second electrodes and by the accumulation semiconductor layer of the P type that contains amorphous fraction, i type and n type.Or by comprising amorphous fraction and being formed at the accumulation semiconductor layer of the n of two main lip-deep electrodes type, i type and P type.It is characterized in that having at least a boundary layer is to be made by semiconductor or insulator, and its resistivity is higher than the semiconductor that is adjacent to boundary layer, this boundary layer be between the semiconductor layer or semiconductor and electrode between.

The present invention further provides the semiconductor device of forming by the Pin type that contains noncrystal semiconductor layer and niP type layer and at least two electrodes, it is characterized in that the doping in P type and n type layer can be minimum on the junction interface of P|i or n|i, and on the direction at the interface that tends to P| electrode or n| electrode, increase gradually.

The present invention further provides semiconductor device, it comprises the niP type that contains amorphous semiconductor or Pin type layer and the electrode that is attached to P type layer in semiconductor, with the electrode that in semiconductor, is attached to n type layer, it is characterized in that (I) one of them p type semiconductor layer at least has the conduction type identical with P type semiconductor and higher impurity density and (II)-n type semiconductor layer has and the same conduction type of n N-type semiconductor N, and higher impurity density, between between the electrode of p type semiconductor layer and p type semiconductor layer homonymy and/or between the electrode of n type semiconductor layer and n type semiconductor layer homonymy.

In the present invention, noun " Pin type or niP type device mean that device comprises following each layer at least: (A) a kind of conductive type layer, (B) non-doping or slightly some doping be actually intrinsic layer and (C) a kind of layer and at least two electrodes of and above-mentioned conductivity type opposite.And then it in fact comprises the device that many P, i and/or n layer are formed.And the cascade connection type device of being piled into by Pin or niP unit.

Fig. 1 is the view of explanation semiconductor device embodiment of the present invention.

Fig. 2 is the view of the common semiconductor device embodiment of explanation.

Fig. 3 is the view that the example of the dopant distribution in the explanation Pin type semiconductor layer of the present invention reaches the example of dopant distribution in common Pin type semiconductor layer.

Fig. 4 is the diagram of the V-I characteristic of the solar cell that is obtained in the comparative example among the embodiment and by comparison.

Fig. 5 is the view profile of common semiconductor device.

Noun " the Pin type device that contains amorphous semiconductor " means that generally such device promptly has structure used in a-Si photovoltaic devices or photodiode, and any the equal of semiconductor device that satisfies this condition can adopt in the present invention.

Moreover noun " semiconductor that contains amorphous " means that it is that semiconductor or (3) amorphous semiconductor that is dispersed in the amorphous semiconductor is the semiconductor that is dispersed in the big granular crystalline state semiconductor that (1) semiconductor is only formed (2) crystallite semiconductor by amorphous.These semiconductors usually are referred to as non-single crystal semiconductor.

Here preferably use the a-Si of boron-doping: H, a-Si ₁-xCx: H, or other similar material is as the P type (P type layer hereinafter referred to as) that contains amorphous semiconductor; A-Si: H, a-Si ₁-xGex: H, or other same type of material is as the i type layer (i type layer hereinafter referred to as) that contains amorphous semiconductor; Mix the a-Si of phosphorus: H, uc-Si: these are to be used in common the amorphous semiconductor photovoltaic devices or photodiode as the n type layer (n type layer hereinafter referred to as) that contains amorphous semiconductor for H or other same type of material.

Be higher than resistivity with the adjoining semiconductor layer of this boundary layer as its resistivity of boundary layer of the present invention, usually best employed its conductance of layer be not more than i type layer conductance 1/10th (for example at a-Si: the conductance of i type layer is approximately 5 * 10 under the H situation ^-9(Ω Cm) ^-1) and be not more than one of the percentage of the conductance of the P type layer of adjacent interface layer or n type layer.For example, the object lesson of above-mentioned boundary layer is cured by resulting oxidation titanium film of electron beam vacuum deposition method or silica; Si ₁-xNx: H or Si ₁-xCx: H(wherein x satisfies relational expression 0＜x＜1), Si ₁-xCx: X: Y, Si ₁-xNx: X: Y or Si ₁-xOx: X: Y(wherein x satisfies relational expression 0＜X＜1, and x is H, Cl, F or Br, and Y is H, Cl, F or Br), above component is to short circuit current, and the influence of the curve factor and other factors is little, and the insulating barrier that other layers are had no adverse effect.In these examples, Si ₁,-xCx: H(x here satisfies relation or 0＜X＜1) be favourable especially can significantly improve the Voc this point.

Above-mentioned semi-conductive resistivity can easily be regulated by changing its composition ratio, i.e. the value of doping in the above-mentioned fraction of mentioning or " x ".For example, in the present invention, the trivalent of from 0.001 to 5 atomic percentage or pentad such as phosphorus or boron can be used as dopant.

Its resistivity is higher than the boundary layer of adjacent with it semiconductor layer resistivity, can be formed on by the following face place of respectively tying in the Pin N-type semiconductor N device shown in Figure 1: the junction interface (a) of transparency electrode 2 and P type layer 3; The junction interface (b) of i type layer 4 and P type layer 3; The junction interface (c) of n type layer 5 and l type layer 4; The junction interface d of metal electrode 6 and n type layer 5; And following each place, junction interface of niP N-type semiconductor N device shown in Figure 2; The junction interface (e) of transparency electrode 2 and n type layer 5; The junction interface (f) of metal electrode 6 and P type layer 3; The junction interface (b) of i type layer 4 and P type layer 3; The junction interface (c) of n type layer 5 and i type layer 4 and in P type layer and n type layer.Under semiconductor device situation shown in Figure 1, junction interface (a) at transparency electrode 2 and P type layer 3, particularly the boundary layer of the junction interface (b) of P type layer 3 and i type layer 4 formation is best, because these interfaces are in the light incident side of light, so Voc can further improve.

Comprise semiconductor or the insulator of its resistivity at the thickness of formed boundary layer between the semiconductor layer or between semiconductor layer and electrode greater than the resistivity of the contiguous semiconductor layer of boundary's interbed, its value is 10 to 500A, the best is 10 to 200A, be more preferred from 10 to 100A, when interfacial layer thickness during less than 10A, the raising of Voc is a bit, otherwise, when reducing greater than the 500A curve factor, its value becomes very big.

In semiconductor device of the present invention, the manufacturing of boundary layer can be adopted glow discharge decomposition method, sputtering method, hot CVD (chemical vapour deposition (CVD)) method, optical cvd method or other similar methods.Basically all there is the device of Pin type or niP semiconductor layer to can be used as the monotype device with this, cascade connection type device, integrated-type device.Adoptable in the present invention semiconductor is restriction especially not, can use any semiconductor device that comprises Pin type or niP N-type semiconductor N as long as that is to say.

Preferably use under light source such as the fluorescent lamp of low illuminance by the semiconductor device of the present invention that said method obtained, under this light source irradiation, series resistance can not become serious problem, because semiconductor device of the present invention can make series resistance increase, and therefore reduces the curve factor or other similar factor.

Can be made into semiconductor device as top mentioned device, it has high electric current under specific voltage and high Voc as long as very small amount of dopant is added to makes this degree that reaches in the boundary layer, and promptly the resistivity of boundary layer is not less than the resistivity of adjoining with it semiconductor layer.

Below situation of the present invention is explained.

In the present invention as containing the i type layer of amorphous Pin type or niP type semiconductor layer, the thickness of this layer is approximately 2500 to 9000A comprising for example: a-Sic: H, a-SiGe: H, a-Ge: H, a0Si: F: H, a-SiN: H or a-SiSn: H; Or these are by phosphorus or boron doped amorphous semiconductor.Can adopt the layer that forms by mixing as P type layer, its thickness is about 80 to 300A, for example a-SiC: H, and uc-Si: H or a-Si: H uses the III a family element of periodic table as P type dopant.And then, as n type layer, can adopt the layer that forms by mixing, its thickness is about 80 to 300A, for example, and a-SiC: H, uc-Si: H or a-Si: H, the Va elements of using periodic table is as n type dopant layer.Yet the i type layer among the present invention, P type are blamed and n type layer is not limitation these layers above-mentioned.

In the mentioned in the above P type layer, by the element doping a-SiC of III a family: the layer that H or a-Si: H obtained is for best, because they have little activation energy and little optical absorption loss, and then, in the related in the above n type layer, with Va elements a-SiC: the H that mixes, the layer that uc-Si: H or a-Si: H obtained is for best, because they have little activation energy and high conductivity.

In the explanation in front, illustrated that mixing as the P type is that the III a family element of periodic table is B, Al, Ga, In and Te and is that the Va elements of periodic table is N, P, As, Sb, Te and Po as n type dopant.Yet employed in the present invention dopant is not confined to those elements recited above.Any dopant is as long as it can produce the P type with mixing or the n N-type semiconductor N all can be used.

In Pin type of the present invention or the niP type semiconductor layer, at least in P type layer and n type layer to have the minimum part of dopant dose be in the junction interface of P/i or n/i and this dosage is progressively increasing on the junction interface direction of P/ electrode or n/ electrode.

Fig. 1 is the embodiment of explanation semiconductor device of the present invention.In Fig. 1, on glass substrate 11, provide again-p type semiconductor layer 13 with transparency electrode 12, provide by this way, promptly dopant dose is minimum on the junction interface of P/i.On p type semiconductor layer 13, form i type semiconductor layer 14 successively, n type semiconductor layer 15 and back electrode 16.

In the semiconductor device of Fig. 1, dopant dose is minimum on the P/i of junction interface.Yet semiconductor device can prepare in this manner, i.e. the distribution of the dopant in p type semiconductor layer is uniformly and dopant dose is minimum on the n/i of the junction interface of n type semiconductor layer.Semiconductor device can also this mode prepare, and promptly in P type and n N-type semiconductor N were two-layer, dopant dose was minimum on junction interface P/i and n/i respectively.In Fig. 1, light 17 is injected from P type layer side, but it also can be injected from n type layer side.The quantity of Pin layer is not restricted to one, and it can be stacked into 2 to 5 layers.In this case, some layers of first Pin layer top can prepare by this way, and promptly dopant is minimum on the junction interface of i layer, or makes with the common Pin layer that is shown in Fig. 2.Number 18 in Fig. 2 is common P type layers.

Some are used in dopant dose 0.01 to 5 atomic percentage normally in P type or the n type layer, but dopant is minimum near the junction interface of P/i or n/i in the present invention, that part of 20 to 30A preferably from the junction interface, be more preferably from that part of doping of junction interface 100A and preferably be not more than 0.01 atomic percentage, more preferably be not more than 0.001 atomic percentage.These facts are to understand from the trial result of inventor's semiconductor device.

The distribution of require mixing is that the junction interface from the junction interface of P/i or n/i to P/ electrode or n/ electrode progressively increases.Utilize this structure, the diffusion that enters the dopant of i layer is minimized, and the interface between i layer and the doped layer improves.Therefore open circuit voltage is improved.

Illustrating of " increasing gradually " in this manual is not to mean because the increase naturally of the dopant that thermal diffusion causes, but mean owing to regulate the continuous or stepped increase that amount obtained of dopant when mixing, under the sort of situation, from improving the viewpoint of Voc, preferably each component rather than the dopant in P type or n type layer do not have marked change.

Fig. 3 is the view of the embodiment of dopant distribution in the explanation semiconductor device of the present invention, and wherein P type i type, and n type layer is respectively a-SiC: H, a-Si: H and a-Si: H.A shows the distribution curve of P type dopant in the p type semiconductor layer in Fig. 3, and B shows the distribution curve of n type dopant in the n type semiconductor layer, and C and D show the distribution curve of P type dopant and n type dopant in the common semiconductor device.

Fig. 3 has just shown the preferred examples of dopant distribution in a kind of P type or the n type layer, and distribution occasion need not be confined to the condition shown in Fig. 3, in other words, only requires to have at least the agent content that mixes of a conductive layer to locate minimum at P/i or n/i junction interface.

When application a-SiC: H produces semiconductor device of the present invention as doped layer, make the a-SiC that does not have doping: H be present in the place, junction interface of P/i or n/i as insulation.So in the present invention structure can adopt.

The electrode that adopts among the present invention is restriction especially not, but can adopt transparent electrode, metal electrode, silicon compound electrode, or the pellet electrode that obtains from produce normally used these materials of solar cell.

The present invention produces arrangement of semiconductors can adopt capacity plate antenna coupled mode ionomer cvd device, electric induction coupled mode plasma CVD equipment, the heat plasma body device, ecr plasma CVD device, the optical cvd device, be excited formula CVD device, and other similar device, but adoptable device is not limited to these.Produce the method for semiconductor device and the not restriction especially of material of use thereof among the present invention.

Pin structure among the present invention or niP structure are structures commonly used in photoelectric device that contains amorphous semiconductor and photodiode.

In the p type semiconductor layer of mentioning, use a-SiC in the above: H or a-Si: H is best with the layer that III a family element doping obtains, and this is because they have little activation energy to produce the contributive and little hole of optical absorption loss to the semiconductor conductance.Also have, in the above-mentioned n type semiconductor layer of mentioning, use a-SiC: H, uc-Si: H or a-Si: H is best with the layer that V a family element doping obtains, this is that it is to semi-conductive conduction contribution and make it that high conductance be arranged because they have little activation energy to produce electronics.Yet in above-mentioned i type, the material that is adopted in P type and the n type semiconductor layer is not limited to the described material in top.

In the above description, the element of having described as P type dopant is an III a family element in the periodic table, i.e. B, al, Ge, In and Te, as the element of n type dopant be V a family in the periodic table element promptly, N, P, As, Sb, Te and PO.Yet dopant of the present invention is not limited to those that the top describes, and any dopant is as long as can produce the P type or the n N-type semiconductor N both can use with its doping.

In the present invention, be in p type semiconductor layer and between the electrode of p type semiconductor layer homonymy, and/or the impurity concentration that is in n type semiconductor layer and P type between the electrode of n type semiconductor layer homonymy and/or n type layer is greater than 2 times of impurity concentration usually, preferably 4 times.The upper limit of impurity concentration has no particular limits, but adjusts to no more than 10 atomic percentages usually.The thickness of high-density semiconductor layer is 10 to 300A, and preferably 30 to 150A is thick.

Now example and the comparative example with regard to situation of the present invention describes.

Example and comparative example

Prepared the solar cell of structure as shown in Figure 1 as test.

As its thickness of transparency electrode is the SnO of 300A ₂Be deposited on the sheet glass with as substrate.

Is the P type a-SiC of 150A with plasma CVD method with thickness: the H film is deposited on the substrate.P type a-SiC: H is used SiH ₄, CH ₄And B-2H ₆(being diluted to 1000ppm with hydrogen) is as unstripped gas.The film of 70A wherein, the SiH of usefulness ₄, CH ₄And B ₂H ₆Flow be respectively 10Sccm, 30Sccm, 200Sccm.Then, continue glow discharge, when reducing B gradually ₂H ₆Air inflow the time, the a-SiC of remaining 80A: H deposition forms.B when the P layer deposition process is finished ₂H ₆Flow be zero Sccm, go out the i type a-Si of 7000A thickness with the glow discharge decomposition method deposit: the H layer.Then, decompose deposit with glow discharge and go out the n type uc-Si that thickness is 300A: the H layer, at that time with the PH of the 100ppm of the 100Sccm of hydrogen dilution ₃SiH with 20Sccm ₄Mist pass through.Thickness be 1000A Al vacuum evaporation thereon as metal back electrode to make 1cm ²Device.

Work as B ₂H ₆Volume flow when constant dopant dose in the P type layer be 2 atomic percentages.For comparison purpose, except thickness is that the P type a-SiC of 150A: H is under above-mentioned constant flow rate the deposit, with method for preparing the solar cell of common type.

Prepared two kinds of solar cells are to measure its V-II characteristic under the fluorescent lamp of 200Lux in illuminance all, and its result is shown among Fig. 4.

The about 0.6V of the open circuit voltage of the solar cell of comparative example.Otherwise the open circuit voltage of the solar cell in the example is 0.7V.Can aware electric current and FF(curve duty factor) improvement arranged slightly.

Like that semiconductor device according to the invention has than high electric current (operating current) under high Voc of common device and the specific voltage just as described above, and therefore, it is best suited for the solar cell that consumption is used.Particularly be equipped in low-light (level) the light source for example electricity used down of fluorescent lamp and the solar cell on the electronic instrument.

And then, semiconductor device according to the invention has not only reduced between the electrode on p type semiconductor layer and the P type layer side, and/or the contact resistance between the electrode on n type semiconductor layer and the n type layer side, and can also keep optical absorption loss very little, therefore, compare with common semiconductor device and can improve photoelectric conversion efficiency.

Claims (6)

1, semiconductor device comprises Pin type layer or nip type layer and at least two electrodes that contain amorphous semiconductor, it is characterized in that, doping in P type or n type layer is minimum on the junction interface of P/i or n/i, and on the direction at the interface that trends towards P/ electrode or n/ electrode, increase gradually, constant part this part in P type or n type layer of the impurity concentration that it is 10A to 300A that P type or n type layer have a thickness has at least 20A thick from the junction interface of P/i or n/i.

2,, be a-SiC one of in P type layer and the n type layer at least wherein according to the device of claim 1 ₂The H layer.

3,, be a-Si one of in P type layer and the n type layer at least wherein according to the device of claim 1 ₂The H layer.

4, according to the device of claim 1, wherein doping rises on the direction at the interface that trends towards P/ electrode or n/ electrode gradually, and this part in P type or n type layer has at least 100A thick from the junction interface of P/i or n/i.

5, according to any one device of claim 1 to 3, wherein the dopant in the P type layer is the element of choosing from the family of B, Al, Ga, In and Tl.

6, according to any one device of claim 1 to 3, wherein the dopant in the n type layer is the element of choosing from N, P, As, Sb, Te and Po family.

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