Embodiment
The present invention improves the framework of light emitting diode drive controller and chip for driving thereof, and carries out the control and the running of display mode and non-display mode through corresponding How It Works again.
Please refer to Fig. 1, be the embodiment calcspar of light emitting diode drive controller of the present invention.As shown in the figure, present embodiment provides a kind of light emitting diode drive controller, and in order to carry out the control of a display mode and a non-display mode, it comprises: a microprocessing unit 10 and a plurality of chip for driving (U1, U2 ..., UN).And the light emitting diode drive controller of present embodiment can be applicable to a display system (figure does not show), in order under display mode, drive those chip for driving (U1, U2 ..., UN) institute connects at least one light emitting diode (scheming not show) of use, and under non-display mode, adjust chip for driving (U1, U2 ..., UN) drive characteristic or obtain each chip for driving (U1, U2 ..., UN) status information.
Wherein, microprocessing unit 10 is used for producing the idsplay order of a tool one image data, perhaps produces a pattern steering order and and confirms identification signal.And microprocessing unit 10 follows this idsplay order can further produce the output enable signal of a display mode, and follows this pattern steering order further to produce the output enable signal of a non-display mode.
Chip for driving (U1, U2 ..., UN) form a serial and arrange and be connected in microprocessing unit 10.And chip for driving (U1, U2 ..., UN) have respectively a sequence data input pin position (SDI_1, SDI_2 ..., SDI_N), a sequence data output pin position (SDO_1, SDO_2 ..., SDO_N), a breech lock activation pin position (LE_1, LE_2 ..., LE_N), an output enable pin position (OE_1, OE_2 ..., OE_N) and a frequency signal pin position (CLK_1, CLK_2 ..., CLK_N).
Wherein, at each chip for driving (U1, U2, ..., UN) between, the sequence data input pin position SDI_1 of chip for driving U1 connects microprocessing unit 10, and the sequence data output pin position SDO_1 of chip for driving U1 connects the sequence data input pin position SDI_2 of chip for driving U2, by that analogy, allow each chip for driving (U1, U2, ..., UN) be able to mutually form connected in series, and each chip for driving (U1, U2, ..., UN) separately sequence data input pin position (SDI_1 in, SDI_2, ..., SDI_N) also separately sequence data output pin position (SDO_1 of serial connection, SDO_2, ..., SDO_N) to form a sequence data transmission path (figure does not show).Make each chip for driving (U1, U2 ..., UN) the sequence data transmission path connected and be connected in microprocessing unit 10.
But it should be noted that, by design of the present invention, no matter under any pattern, last chip for driving in connected in series, just the sequence data output pin position SDO_N of chip for driving UN can be considered invalid (Null) pin position, does not need to connect back microprocessing unit 10 again and forms feedback circuit.And thus, just do not need additionally to increase the pin position connects feedback circuit to microprocessing unit 10, and can reduce the shared area of circuit, and also comparatively convenient in the expansion of integral body.
And one of characteristics of present embodiment also be each chip for driving (U1, U2 ..., UN) breech lock activation pin position (LE_1, LE_2 ..., LE_N) be designed to transmitted in both directions pin position, and can accept the control transmission direction, and this one the design promptly be allow breech lock activation pin position (LE_1, LE_2 ..., LE_N) but function as program I/O (General PurposeI/O, GPIO) function of pin position.And chip for driving (U1, U2 ..., UN) separately breech lock activation pin position (LE_1, LE_2 ..., LE_N) be connected in parallel in microprocessing unit 10.
Thus, in display mode, the chip for driving of present embodiment (U1, U2 ..., UN) the sequence data transmission path that sees through separately receives in the sequence mode and the transmitting and displaying instruction, and see through separately breech lock activation pin position (LE_1, LE_2 ..., LE_N) receive the breech lock enable signal that microprocessing unit 10 is exported in mode arranged side by side, to carry out the action of synchronous image data; In non-display mode, the chip for driving of present embodiment (U1, U2 ..., UN) the sequence data transmission path that sees through separately comes the acknowledge identification signal in the sequence mode, and see through separately breech lock activation pin position (LE_1, LE_2 ..., LE_N) receive drive characteristic steering order and output state information in mode arranged side by side.
In addition, on architecture design, chip for driving (U1, U2 ..., UN) separately output enable pin position (OE_1, OE_2 ..., OE_N) and frequency signal pin position (CLK_1, CLK_2 ..., CLK_N) for input action pin position, and be connected in microprocessing unit 10 with parallel way.Wherein, output enable pin position (OE_1, OE_2 ..., OE_N) in order to the output enable signal that receives the display mode that microprocessing unit 10 exported or the output enable signal of non-display mode.And frequency signal pin position (CLK_1, CLK_2 ..., CLK_N) receive the frequency signal that microprocessing unit 10 is provided, with as each chip for driving (U1, U2 ..., UN) operation frequency.And those skilled in the art should understand the effect and the principle of frequency signal, below are just no longer given unnecessary details.
Therefore, under the framework based on foregoing light emitting diode drive controller, when chip for driving (U1, U2 ..., UN) be to enter default display mode when not receiving the pattern steering order, and the light emitting diode that drives separately to be connected according to idsplay order, to demonstrate this image data.
Wherein under display mode, its operation workflow and each pin bit function are as described below: at first, chip for driving (U1, U2 ..., UN) separately sequence data transmission path receives in the sequence mode and the transmitting and displaying instruction; When idsplay order after chip for driving U1 transfers to chip for driving UN, breech lock activation pin position separately (LE_1, LE_2 ..., LE_N) can receive the breech lock enable signal that microprocessing unit 10 is exported side by side, to carry out the action of synchronous image data; Moreover, output enable pin position separately (OE_1, OE_2 ..., OE_N) receive the triggering of the output enable signal of this display mode in mode arranged side by side, show image data after this is synchronously with the driven for emitting lights diode.And this promptly is the operation workflow of general so-called display mode.
On the other hand, when chip for driving (U1, U2 ..., UN) be to enter non-display mode when receiving the pattern steering order, and confirm to start running by the indication of confirming identification signal, come each self-adjusting one drive characteristic or export a status information separately according to the light emitting diode error detection to receive the drive characteristic steering order.
Wherein under non-display mode, its operation workflow and each pin bit function are as described below: at first, chip for driving (U1, U2 ..., UN) separately output enable pin position (OE_1, OE_2 ..., OE_N) be the output enable signal that receives this non-display mode in mode arranged side by side, be used for confirming breech lock activation pin position (LE_1, LE_2 ..., LE_N) for input action pin position or output action pin position; Moreover, chip for driving (U1, U2 ..., UN) the sequence data transmission path that sees through in regular turn separately again receives and the acknowledge identification signal, and each chip for driving (U1, U2 ..., UN) can confirm whether will start running at present according to the indication of confirming identification signal, when chip for driving (U1, U2 ..., UN) when running, breech lock activation pin position separately (LE_1, LE_2 ..., LE_N) receive drive characteristic steering order and output state information in mode arranged side by side.
In addition, aforementioned chip for driving (U1, U2 ..., UN) be according to the output enable signal of this non-display mode (OE_1, OE_2 ..., OE_N) confirm breech lock activation pin position (LE_1, LE_2 ..., LE_N) for input action pin position or output action pin position, it is also in order to judge that present non-display mode is a luminance gain control model or an error detection pattern.And when judging when being the luminance gain control model at present, then breech lock activation pin position (LE_1, LE_2 ..., LE_N) be input action pin position; And when judging when being the error detection pattern at present, then breech lock activation pin position (LE_1, LE_2 ..., LE_N) be output action pin position.
At last, if present non-display mode is when being the luminance gain control model, then each chip for driving (U1, U2 ..., UN) can see through breech lock activation pin position (LE_1, LE_2 ..., LE_N) receive the drive characteristic steering order that comes from microprocessing unit 10; If present non-display mode is when being the error detection pattern, then each chip for driving (U1, U2 ..., UN) can see through breech lock activation pin position (LE_1, LE_2 ..., LE_N) return status information and give microprocessing unit 10.And herein the status information of indication can for example be meant each chip for driving (U1, U2 ..., UN) information of the light emitting diode error condition that detected.
And can obviously learn by present embodiment, the present invention is under non-display mode, its mainly be see through breech lock activation pin position (LE_1, LE_2 ..., LE_N) receive drive characteristic steering order and output state information, it is to belong to the input arranged side by side and the aspect of output side by side.
In order to further specify the framework of chip for driving used in the present invention, refer again to Fig. 2, be the embodiment calcspar of the chip for driving of light emitting diode drive controller of the present invention.As shown in the figure, present embodiment is done explanation with the framework of a chip for driving U.The chip for driving U of present embodiment comprises: a displacement impact damper 21, an image data buffer 22, a drive current output port 23, a key control unit 24, a multiplexer 25 and a mode detecting unit 26.Wherein, displacement impact damper 21 is serially connected with between a sequence data input pin position SDI and the sequence data output pin position SDO, and transmits data in the sequence mode.Image data buffer 22 connects displacement impact damper 21.Multiplexer 25 connects a breech lock activation pin position LE, an output enable pin position OE, sequence data input pin position SDI, image data buffer 22, drive current output port 23, key control unit 24 and mode detecting unit 26.Mode detecting unit 26 then connects breech lock activation pin position LE, output enable pin position OE, sequence data input pin position SDI.In addition, displacement impact damper 21 and mode detecting unit 26 can connect a frequency signal pin position CLK again, are used for receiving a frequency signal that microprocessing unit 10 provided with as operation frequency.
And the idsplay order that produces a tool one image data when the microprocessing unit 10 of light emitting diode drive controller is when giving sequence data input pin position SDI, mode detecting unit 26 receives idsplay order, to control multiplexer 25 breech lock activation pin position LE is connected in image data buffer 22, and output enable pin position OE is connected in drive current output port 23.And under this switching state, promptly be to belong to display mode.
And then under display mode, displacement impact damper 21 is to see through sequence data input pin position SDI to receive idsplay order, and export idsplay order through sequence data output pin position SDO and give next chip for driving, and displacement impact damper 21 also can store image data in the idsplay order of transmission tool image data.Then, the switching that has seen through multiplexer 25 owing to image data buffer 22 is connected in breech lock activation pin position LE, therefore when image data buffer 22 receives the breech lock enable signal that microprocessing unit 10 exported, just can receive image data in the displacement impact damper 21 synchronously according to the breech lock enable signal.
Drive current output port 23 connects image data buffer 22, in order to receive this image data after synchronously, and the switching that has seen through multiplexer 25 owing to drive current output port 23 is connected in output enable pin position OE, therefore receiving microprocessing unit 10 when following the output enable signal of the display mode that this idsplay order exports when drive current output port 23, then is that the triggering by the output enable signal of this display mode comes the driven for emitting lights diode.So as to finishing the running of display mode.Wherein, drive current output port 23 is in order to connect at least one driving pin position Drive, and each drives pin position Drive and is used for connecting a light emitting diode.And if the chip for driving U of present embodiment for example is used for driving 16 light emitting diodes, then drive current output port 23 can connect 16 driving pin position Drive.
Under the another kind of situation, when the microprocessing unit 10 generations one pattern steering order of light emitting diode drive controller is given breech lock activation pin position LE and output enable pin position OE, and when the output enable signal that produces a non-display mode is given output enable pin position OE, mode detecting unit 26 can receive the pattern steering order that breech lock activation pin position LE and output enable pin position OE are transmitted, so just control multiplexer 25 breech lock activation pin position LE is connected in key control unit 24, and mode detecting unit 26 confirms that according to the output enable signal of non-display mode it is input action or output action that multiplexer 25 provides breech lock activation pin position LE again.And under this switching state, promptly be to belong to non-display mode.
And about confirming that according to the output enable signal of non-display mode it is the description of input action or output action that multiplexer 25 provides breech lock activation pin position LE in above-mentioned mode detecting unit 26, it just can judge present non-display mode simultaneously is a luminance gain control model or an error detection pattern.When judging when being the luminance gain control model at present, then breech lock activation pin position is provided is input action to multiplexer 25; And when judging when being the error detection pattern at present, then breech lock activation pin position is provided is output action to multiplexer 25.Wherein, those skilled in the art should understand, detect the technological means of the pattern of non-display mode according to the output enable signal of non-display mode about implementation pattern detecting unit 26, it can for example be microprocessing unit 10 additional marking signal when the output enable signal of this non-display mode of output, with when mode detecting unit 26 judges that the output enable signal of non-display mode includes this marking signal, then be to be that digital 1 signal (binary one signal) is expressed as the error detection pattern for example with output enable pin position OE; Otherwise, be that digital 0 signal (Binary Zero signal) is expressed as the luminance gain control model then with output enable pin position OE.And this only is a kind of design aspect wherein certainly, is not the actual the present invention that is used for limiting.
And then under non-display mode, displacement impact damper 21 can see through sequence data input pin position SDI and receive the affirmation identification signal that microprocessing unit 10 is produced, and comes the acknowledge identification signal to give next chip for driving through sequence data output pin position SDO again.And what deserves to be mentioned is, the chip for driving U of present embodiment sees through breech lock activation pin position LE to receive drive characteristic steering order and output state information, and between the different driving chip, because the breech lock activation pin position LE of each chip for driving is connected in parallel, so in order to distinguish present drive characteristic steering order and output state information Control power actual is to be under the jurisdiction of which chip for driving to use, thereby can arrange in pairs or groups again and confirm the indication of identification signal, the chip for driving of confirming to confirm identification signal at present and being transferred to, and then determine whether its multiplexer 25 will start running, to transmit.
And confirm the design of identification signal about above-mentioned collocation, aspect that can be as described below.Wherein, suppose that light emitting diode drive controller design has 16 chip for driving, so in each chip for driving, designed 16 buffers (figure does not show) at the transmission path of sequence data input pin position.In addition, produced by microprocessing unit 10 that to be familiar with level signal really then be for example to be designed to 16 numeral 1 signals, and be transferred to the chip for driving of each serial connection in the sequence mode in regular turn.Therefore, judging wherein first buffer of 16 buffers when first chip for driving is when being digital 1 signal by digital 0 signal transition, represent that promptly present drive characteristic steering order and output state information Control power is to be under the jurisdiction of this first chip for driving, and can continue to carry out again the time (, then meet together and carry out 16 operation frequencies) of 15 numeral 1 signals if an operation frequency is to trigger numeral 1 signal.When first digit 1 signal of confirming identification signal by the time has been transferred to first buffer in second chip for driving, originally first buffer in the chip for driving promptly is to be digital 0 signal by digital 1 signal transition, so the drive characteristic steering order of this moment and output state information Control power promptly are under the jurisdiction of this second chip for driving.The rest may be inferred, confirms the design of identification signal to finish the collocation of drive characteristic steering order of the present invention and output state information.And this design promptly is similarly will confirm that identification signal is considered as a flag, and be transmitted to each chip for driving in regular turn in the sequence mode, and the chip for driving that is subjected to the flag indication by the time could be carried out relevant running, and receives drive characteristic steering order and output state information in view of the above.
Then, because under non-display mode, key control unit 24 sees through the switching of multiplexer 25 and is connected in breech lock activation pin position LE, therefore key control unit 24 just can receive the drive characteristic that drive characteristic steering order that breech lock activation pin position LE transmitted is adjusted drive current output port 23, perhaps sees through the status information that breech lock activation pin position LE returns the light emitting diode error detection and gives microprocessing unit 10.Wherein, key control unit 24 further comprises one and extends buffer 241, it is to be used for temporary key control unit 24 in order to a yield value of the drive characteristic of adjusting drive current output port 23, and temporary this is used for returning status information to the light emitting diode error detection of microprocessing unit 10.
Operation workflow when further specifying actual operation of the present invention and the detailed operation step under non-display mode refer again to Fig. 3, are the embodiment process flow diagram of the How It Works of light emitting diode drive controller of the present invention.As shown in the figure, present embodiment provides a kind of How It Works of light emitting diode drive controller, it is to do description with each chip for driving of being arranged in pairs or groups in the light emitting diode drive controller, the step of this How It Works comprises: at first, be with the default display mode (S301) that enters of light emitting diode drive controller on actual design, just can come to each chip for driving by the idsplay order that microprocessing unit produces a tool one image data.And at the same time, chip for driving can continue to judge whether to receive the pattern steering order (S303) that microprocessing unit produces.If the judged result of step (S303) is represented that then present running is normal, and is continued to operate under the display mode, and come the driven for emitting lights diode with image data displaying (S305) by chip for driving for not.
And if step (S303) judged result is for being, then unusual condition has taken place owing to light emitting diode in expression, so, just can enter so-called non-display mode (S307).After entering non-display mode, chip for driving promptly can be judged the pattern (S309) of non-display mode according to the output enable signal of the non-display mode that microprocessing unit produced.Present embodiment is to illustrate with luminance gain control model and error detection pattern.
When judging that the present non-display mode that enters is when belonging to the luminance gain control model, then can carry out corresponding switching running (described in the embodiment of Fig. 2) in the chip for driving, and judge whether the indication (S311) of confirmation of receipt identification signal.If the judged result of step (S311) is for being to represent that then present chip for driving has received the confirmation the indication of identification signal and can start running.So chip for driving just can receive the drive characteristic steering order and adjust drive characteristic (S313), with the brightness of increase and decrease light emitting diode.Otherwise if the judged result of step (S311) is not for, then expression does not receive the confirmation the indication of identification signal as yet at present and need not receive the drive characteristic steering order and carry out running, and after the indication that receives the confirmation identification signal, chip for driving operates.
In addition, when the judged result of step (S309) is to judge that the present non-display mode that enters is when belonging to the error detection pattern, then can carry out corresponding switching running (described in the embodiment of Fig. 2) in the chip for driving equally.And the same indication (S315) that also can judge whether the confirmation of receipt identification signal.If the judged result of step (S315) is for being to represent that then present chip for driving has received the confirmation the indication of identification signal and can start running.So chip for driving just can return wrong status information according to the light emitting diode error detection and give microprocessing unit (S317).Otherwise, if the judged result of step (S315) is for denying, the wrong status information of then representing not receive the confirmation the indication of identification signal as yet at present and need not exporting the light emitting diode that is detected, after the indication that receives the confirmation identification signal, chip for driving operates.
At last, after the execution of step (S313) or step (S317), a pattern steering order (S319) of jumping out that then can judge whether to receive microprocessing unit again and produced.Wherein, this pattern steering order of jumping out only is to be used for the corresponding design that enters the pattern steering order of non-display mode originally in order to indication in program design.If the judged result of step (S319) is for denying, then expression still has chip for driving not carry out the relevant running of non-display mode as yet, confirm that just identification signal is not passed to last chip for driving as yet, so just continue execution in step (S319), with the pattern steering order that continues to wait for that reception is jumped out.
And if the judged result of step (S319) is for being, then represent all relevant runnings of the intact non-display mode of executed of all chip for driving, show pattern so just can switch echo by the pattern steering order of jumping out, and continue execution in step again (S303) and step thereafter thereof.Whereby, to finish the How It Works of the light emitting diode drive controller that present embodiment provided.
Refer again to Fig. 4, operate on the embodiment timing waveform of luminance gain control model for the present invention respectively.As shown in the figure, its timing waveform is to do explanation with the state of the pin position in the chip for driving, and is broadly divided into three intervals in running, is respectively interval (1), interval (2) and interval (3).Wherein, during being to belong to mode detecting during this section of interval (1), be used for the output enable signal (output enable pin position OE transmits) of the pattern steering order (breech lock activation pin position LE and output enable pin position OE transmit) that produces according to microprocessing unit and non-display mode to decide the pattern aspect of present non-display mode.Wherein, present embodiment be design when output enable pin position OE is digital 0 signal, then be the luminance gain control model, so can find that the output enable pin position OE on the timing waveform is the state that is positioned at digital 0 signal when entering interval (2).
Then, sequence information input pin position SDI_1, SDI_2 ..., SDI_N then is meant the pin position of different driving chip (N) respectively, and because the sequence information input pin position between the different driving chip forms connected in series, and be that sequence transmission is confirmed identification signal, therefore on the timing waveform of interval (2), can find the different driving chip sequence information input pin position SDI_1, SDI_2 ..., SDI_N is the state that changes digital 1 signal in regular turn into, and can continues to have the time of N CLKs respectively.And when sequence information input pin position was the state of digital 1 signal, then expression was the indication which chip for driving to be received the confirmation identification signal by at present, so just can receive the yield value that is used for adjusting light emitting diode by corresponding this chip for driving.Wherein, because the breech lock activation pin position LE of each chip for driving belongs to be connected in microprocessing unit side by side, therefore breech lock activation pin position LE is used for receiving the yield value of each chip for driving in regular turn in interval (2).
At last, part in interval (3), then be because confirm that identification signal is passed to last chip for driving by first chip for driving, and the relevant running of the intact luminance gain control model of all chip for driving executeds, so can receive the so-called pattern steering order of jumping out, to jump out the running of luminance gain control model.
Refer again to Fig. 5, operate on the embodiment timing waveform of error detection pattern for the present invention.As shown in the figure, the timing waveform of present embodiment is to be used for illustrating that chip for driving operates on the state of error detection pattern.And to operate on the state of luminance gain control model identical with Fig. 4 haply, and operation principles is also identical.Difference wherein only is that output enable pin position OE represents the error detection pattern that enters with digital 1 signal, so can find that the output enable pin position OE on the timing waveform is the state that is positioned at digital 1 signal when entering interval (2).Secondly, because the present embodiment explanation operates on the error detection pattern, so the data when interval (2), transmitted of breech lock activation pin position LE, be the wrong status information that is used for exporting each chip for driving in regular turn.
In sum, the present invention improves on the framework of light emitting diode drive controller and driving element thereof, and running and control by whole light emitting diode drive controller, must not increase the pin of each driving element and controller position to reach, also need not reserve or increase the architecture design of feedback circuit, can allow light emitting diode drive controller reach the purpose of the control of carrying out display mode and non-display mode.Thus,, the employed circuit of whole light emitting diode drive controller just can comparatively be simplified by design of the present invention, and also can be comparatively flexible on using.
But; the above; only be the detailed description and the accompanying drawing of specific embodiments of the invention; be not in order to restriction the present invention; protection scope of the present invention should be as the criterion with the scope of claims; any those skilled in the art in the field of the invention, can think easily and variation or modify all can be encompassed within the protection domain of this case.