CN101807917A

CN101807917A - Signal offset cancellation module for multiple-data stream receiver

Info

Publication number: CN101807917A
Application number: CN 201010127551
Authority: CN
Inventors: 梁国锦; 贾金辉
Original assignee: GUANGZHOU XINULTRA ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: GUANGZHOU XINULTRA ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2010-03-19
Filing date: 2010-03-19
Publication date: 2010-08-18

Abstract

The invention relates to a signal offset cancellation module for a multiple-data stream receiver, which comprises a phase detector, a charge pump, a parallel data latch module, a voltage-controlled oscillator generating a multiphase clock and an adjustable time delay or phase interpolation module for adjusting the delay size, wherein the phase detector, the charge pump, voltage-controlled oscillator and the adjustable time delay or phase interpolation module are sequentially connected with each other, the parallel data latch module is connected with the voltage-controlled oscillator. The invention has the advantages that High-speed continuous data can be recovered from multiple transmission channels, and can more accurately and effectively lick and store and recover the data compared with the prior art.

Description

The signal bias cancellation module that is used for the multichannel data stream receiver

Technical field

The present invention relates to a kind of signal bias cancellation module, relate in particular to a kind of signal bias cancellation module that is used for the multichannel data stream receiver.

Background technology

In the multi-channel data transmission environment, because imperfect transmission medium influence such as similar fiber lengths difference, PCB track lengths difference and load difference, even data begin to transmit at transmitting terminal simultaneously, the time that arrives receiving terminal also can be different, and the difference of sequential makes data become difficult more in the recovery of receiving terminal in addition.Because the multichannel input signal can not be sampled by one road synchronised clock, each input data channel needs the independent clock of the aligned data eye pattern center of an energy the best, in addition, the sampling location also needs constantly adjustment to compensate because temperature and other factors cause to such an extent that input signal is offset.At present, there is several method to solve the uncertainty of data-bias in the different passages, data are recovered reliably at receiving terminal: first method is oversampling technique, it is sampled in each cycle data more than three times usually at least, selects one then as restore data from three sampled datas.The shortcoming of this oversampling technique is that the accuracy in sampling time is relatively poor, reason is that the optimum sampling time of acquisition minimum data error rate is the intermediate point of transfer of data, but oversampling technique can only be selected a sampling time point from three positions, so before arriving next optimum sampling phase place, if data center with respect to optimum sampling time point drift has taken place, the data error rate will increase.Second method is called the clock delay method, is admitted to before delay phase-locked loop (DLL) produces the multi-phase clock of the parallel data that is used to sample in clock signal, adopts a kind of adjustable delay element to come delay clock signals.Although this adjustable delay element can be placed on all sampling clocks the center of eye pattern accurately, but used phase-locked loop (PLL) that is used to produce clock and the delay phase-locked loop (DLL) that is used to generate leggy in this method, phase-locked loop (PLL) and delay phase-locked loop (DLL) thus all can bring shake to reduce sampling precision to sampling clock.While delay phase-locked loop (DLL) can take very big area usually, and power consumption is very high simultaneously.

Summary of the invention

The technical problem to be solved in the present invention is: a kind of signal bias cancellation module that is used for the multichannel data stream receiver is provided, make it from multiple transmission channel, the high-speed and continuous data be recovered out, than before technology, this module can be more accurately and is effectively latched and restore data.

The technical solution adopted for the present invention to solve the technical problems is: a kind of signal bias cancellation module that is used for the multichannel data stream receiver, comprise phase discriminator, charge pump, parallel data latch module, generate multi-phase clock voltage controlled oscillator, be used to adjust the adjustable delay or the phase interpolation module of time-delay size, wherein phase discriminator, charge pump, voltage controlled oscillator and adjustable delay or phase interpolation sequence of modules are connected, and the parallel data latch module is connected with voltage controlled oscillator.

Further: described adjustable delay or phase interpolation module comprise delay element.

The invention has the beneficial effects as follows that receiver can generate best heterogeneous sampling clock and recover input traffic reliably in each passage.

Description of drawings

The present invention is further described below in conjunction with drawings and Examples.

Fig. 1 is the module diagram that the present invention is used for the signal bias cancellation module of multichannel data stream receiver;

Fig. 2 is the sequential chart that the present invention is used for the signal bias cancellation module of multichannel data stream receiver;

Wherein: 1, phase discriminator, 2, charge pump, 3, voltage controlled oscillator, 4, controlled time-delay or phase interpolation module, 5, the parallel data latch module.

Embodiment

As shown in Figure 1, 2, the present invention includes phase discriminator 1, charge pump 2, voltage controlled oscillator 3, adjustable delay or phase interpolation module 4 and parallel data latch module 5.Input data (Data) are passed through the parallel data latch module by the parallel clock phase sample, these parallel clock phase places are equidistantly separated, each phase sample one digit number is according to conversion, the multiple sampling phase of voltage controlled oscillator 3 generations is sampled and is recovered to import data, feedback clock (Feedback Clock) from voltage controlled oscillator 3 has controlled delay, and the sequential correlation between sampling phase (Phase1, Phase2) and the input reference clock (Reference Clock) just becomes adjustable like this.Just can produce a synchronous and equally spaced sampling phase by the time-delay size voltage controlled oscillator 3 of adjusting the adjustable delay module, have the optimum sampling position simultaneously.What show among Fig. 1 recovers principle for the data of single channel data flow, for multichannel, only this principle need be repeated each circuit-switched data stream and gets final product.

Claims

1. signal bias cancellation module that is used for the multichannel data stream receiver, comprise phase discriminator (1), charge pump (2) and parallel data latch module (5), it is characterized in that: described cancellation module also comprises the voltage controlled oscillator (3) that generates multi-phase clock and is used to adjust the adjustable delay or the phase interpolation module (4) of time-delay size, wherein phase discriminator (1), charge pump (2), voltage controlled oscillator (3) and adjustable delay or phase interpolation module (4) are linked in sequence, and parallel data latch module (5) is connected with voltage controlled oscillator (3).

2. the signal bias cancellation module that is used for the multichannel data stream receiver according to claim 1 is characterized in that: described adjustable delay or phase interpolation module (4) comprise delay element.