CN101783098B - Serial transmission device and signal transmission method - Google Patents
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- CN101783098B CN101783098B CN2009100052109A CN200910005210A CN101783098B CN 101783098 B CN101783098 B CN 101783098B CN 2009100052109 A CN2009100052109 A CN 2009100052109A CN 200910005210 A CN200910005210 A CN 200910005210A CN 101783098 B CN101783098 B CN 101783098B
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Abstract
The invention relates to a serial transmission device and a signal transmission method. The serial transmission device comprises a plurality of data transmission devices which comprise a first shift register, an error detection circuit and a second shaft register. The second shift register is used for receiving a second serial input signal and generating output signals on the basis of a clock signal; the error detection circuit is used for receiving the output signals and first serial input signals from the second shift register and selecting one of the output signals and first serial input signals on the basis of the error detection result to generate output signals; the first shift register is used for receiving output signals from the error detection circuit and generating serial output signals on the basis of the clock signal, wherein the second serial input signal is a first serial input signal from at least the previous-level data transmission device, and the first serial input signal is the serial output signal from the previous-level data transmission device. The invention aims at achieving the effect that the serial transmission data are not interrupted during a fault of the transmission device.
Description
Technical field
The present invention relates to a kind of transmitting device, relate in particular to a kind of serial transmission device and method for transmitting signals thereof.
Background technology
Controller and peripheral unit or controller and the communications pattern between the controller are divided into parallel transmission (Parallel Communication) communicate by letter with serial transmission (the Serial Communication) that communicate by letter; Wherein, serial transmission communication only needs three transmission lines (clock cable, data signal line and latch signal line) can transmit and receive signal.Said transmission mode is the mode through a clock signal transmission one digit number certificate, in regular turn the serial data of input is delivered to the transmitting device of connection.After said serial data all was transferred to each transmitting device connected in series, said controller can produce a latch signal to latch and to produce a plurality of parallel output signals.
Serial transmission communication can be applicable to various electronic display units, for example with light emitting diode as the traffic sign of light emitting source or large-scale advertisement billboard etc.The large-scale advertisement billboard usually is to be arranged by the light emitting diode more than ten thousand to form, and therefore needs a plurality of transmitting devices connected in series to control the illuminated message of these light emitting diodes.Serial transmission communication also can be applicable to local light source control technology (Local Dimming Technology), with the diode backlight of control regional area.Figure 1A shows the synoptic diagram of conventional serial transmission device, and Figure 1B shows the circuit block diagram of each data transmission device.With reference to Figure 1B, said data transmission device 10 has clock signal terminal CLK, latch signal LAH, input end SDI, output terminal SDO and a plurality of parallel output terminal OUT
1, OUT
2... OUT
NSaid data transmission device 10 comprises shift register (shift register) 101 and latch (latch) 102.Said shift register 101 comprises N level register (register) to receive serial input data; The first order register of wherein said shift register 101 is connected to input end SDI, and the afterbody register of said shift register 101 is connected to output terminal SDO.Said shift register 101 moves the next stage register to shift register 101 of serial input data from input end SDI when each clock signal arrives said clock end CLK.The parallel output signal of said shift register 101 can be latched in the corresponding latch 102 when said latch signal LAH launches, and the output of said latch 102 each grades is connected to said parallel output terminal OUT
1, OUT
2... OUT
N
With reference to Figure 1A, said serial transmission device 11 comprises four data transmission device 131-134 that connect with serial mode.Each data transmission device 131-134 individual responses is in input signal 141-144 and clock signal, and output signal 151-154 is provided individually.Data-signal 141, clock signal and latch signal that said first data transmission device 131 receives are to be provided by controller 12.Because the output terminal of each data transmission device 131-133 is coupled to the input end of next data transmission device 132-134; Therefore the serial data signal of controller 12 outputs can be displaced to next stage data transmission device 132 via its shift register 101 after being received by first data transmission device 131, then is displaced to next stage data transmission device 133 via the shift register 101 of said level again.The rest may be inferred, and the output terminal SDO by the 4th data transmission device 134 sees said serial data signal off at last.Fig. 1 C shows the oscillogram of the input and output signal of said serial transmission device 11.Because each data transmission device 131-134 comprises a shift register 101, so it can store the input data of N position.When N clock signal arrived said clock end CLK, the shift register 101 of said first data transmission device 131 was deposited in the N bit data.Then when 2N clock signal arrived said clock end CLK, shift register 101 quilts of said first and second data transmission devices 131,132 were deposited in the N bit data.When 4N clock signal arrived said clock end CLK, the shift register 101 of each data transmission device 131-133 was deposited in the N bit data at last.The bit data that said shift register deposits in can be synchronized after said latch signal LAH triggers and be latched in the corresponding latch 102, so as to and the said bit data of line output to the output terminal OUT of each data transmission device 131-133
1, OUT
2... OUT
NAs stated, said conventional serial transmission device 11 can use the connected mode of serial to increase transmitting device with a large amount of transmission data.
Yet when said serial transmission device 11 one of them data transmission device malfunction and failure, the serial data of transmission just can produce interrupts and can't continue transmission.For instance, when said serial transmission device was applied to the large-scale advertisement billboard, the information that the fault of arbitrary transmitting device can cause showing was incomplete and be difficult to identification.Especially when said serial transmission device was applied to traffic sign or transaction message display device, the fault of arbitrary transmitting device may cause the loss of lives and properties.In the application of this external LED-backlit; As when adopting the serial transmission method to carry out the dynamic light adjustment data transmission of LED; The fault of arbitrary transmitting device may cause whole LED backlight module complete failure; Therefore, the present invention provides a kind of serial transmission device and method for transmitting signals thereof, the problem that data transmission is ended when avoiding above-mentioned disabled status to take place.
Summary of the invention
One embodiment of serial transmission device of the present invention comprises a plurality of data transmission devices that connect with serial mode, and wherein said data transmission device comprises first shift register, error detect circuit and second shift register.Said second shift register is in order to receiving second serial input signals, and produces the output signal according to clock signal.Said error detect circuit is in order to receiving the output signal and first serial input signals from said second shift register, and selects wherein one according to the error-detecting result to produce the output signal.Said first shift register is in order to the output signal of reception from said error detect circuit, and the said clock signal of foundation produces serial output signal.Said second serial input signals is from first serial input signals of previous stage data transmission device at least, and said first serial input signals is the serial output signal from the previous stage data transmission device.
Another embodiment of serial transmission device of the present invention comprises a plurality of data transmission devices that connect with serial mode, and wherein said data transmission device comprises first shift register, second shift register and error detect circuit.Said first shift register is in order to receiving first serial input signals, and produces first serial output signal according to clock signal.Said second shift register is in order to receiving second serial input signals, and produces second serial output signal according to clock signal.Said error detect circuit is in order to receiving the output signal of said first and second shift registers, and selects wherein one according to the error-detecting result to produce one group of parallel output signal.Said first serial input signals is from the previous stage or first serial output signal of prime data transmission device more, and said second serial input signals is from the back one-level or second serial output signal of back grade data transmitting device more.
One embodiment of serial signals transmission method of the present invention comprises following steps: a plurality of data transmission devices that connect with serial mode are provided, and wherein arbitrary data transmission device has the first serial data input port and the second serial data input port; The first serial data input port by previous stage data transmission device output forward-chaining data data transmission device up till now; The second serial data input port by the input forward-chaining data of previous stage data transmission device at least data transmission device up till now; Utilize error detect circuit to compare the data of said first serial data input port and the said second serial data input port, and select wherein one according to the error-detecting result to produce the actual serial input signals of serial output signal as present data transmission device; And data transmission device produces parallel output signal in order to the driven for emitting lights diode.
Another embodiment of serial signals transmission method of the present invention comprises following steps: a plurality of data transmission devices that connect with serial mode are provided, and wherein arbitrary data transmission device has the first serial data input port and the second serial data input port; By previous stage or the first serial data input port of prime data transmission device output forward-chaining data data transmission device up till now more; Export the second serial data input port of reverse serial data data transmission device up till now by back one-level or back grade data transmitting device; Utilize error detect circuit to compare the data of said first serial data input port and the said second serial data input port, and select wherein one according to the error-detecting result to produce parallel output signal so as to the driven for emitting lights diode.
Description of drawings
Figure 1A shows the synoptic diagram of conventional serial transmission device;
Figure 1B shows the circuit block diagram of each data transmission device;
Fig. 1 C shows the oscillogram of the input and output signal of said serial transmission device;
Fig. 2 A shows the synoptic diagram of serial transmission device according to an embodiment of the invention;
The circuit block diagram of the serial transmission device of Fig. 2 B displayed map 2A;
Fig. 2 C shows the oscillogram of the input and output signal of said serial transmission device;
Fig. 3 A shows the synoptic diagram according to the serial transmission device of one embodiment of the invention;
The circuit block diagram of the serial transmission device of Fig. 3 B displayed map 3A; And
Fig. 3 C shows the signal transmission form when said serial transmission device is nonserviceabled.
Embodiment
Fig. 2 A shows the synoptic diagram of serial transmission device according to an embodiment of the invention.For the sake of brevity, the data transmission device that Fig. 2 A connects with three grades of serial modes is the example explanation, and Fig. 2 B shows the circuit block diagram of each data transmission device.With reference to Fig. 2 B, said data transmission device 20 has clock signal terminal CLK, first input end DATA_in, the second input end DATA_pre, the first output terminal DATA_out and a plurality of parallel output terminal OUT
1, OUT
2... OUT
NIn the present embodiment, said data transmission device 20 comprises first shift register 201, second shift register 202, error detect circuit 203, latch 204 and latchs and produces circuit 205.The principle of work explanation of said serial transmission device 20 as follows.At first, serial input data is received by the first input end DATA_in of first data transmission device 211, and is transferred to the error detect circuit 203 in said first data transmission device 211.Simultaneously, said serial input data is also received by the second input end DATA_pre of second data transmission device 212, and is transferred to the error detect circuit 203 in said second data transmission device 212.After N clock signal arrived the clock end CLK of said first data transmission device 211, said serial input data exported and gets into the first input end DATA_in of said second data transmission device 212 through first shift register 201 in said first data transmission device 211.The signal of said first shift register 201 outputs is also supplied to the second input end DATA_pre of the 3rd data transmission device 213 simultaneously.
In the present embodiment, the error detect circuit 203 among the said data transmission device 211-213 has two input ends.Illustrate with second data transmission device 212; One of them input end is used for receiving the bit data of the first output terminal DATA_out of first order data transmission device 211; And another input end is used for receiving the output signal of second shift register 202 in self data transmission device, and optionally switches wherein first shift registers 201 in its data transmitting device of said two input ends.Whether in the present embodiment, said error detect circuit 203 can be a bit comparator, have identical in fact logic to change in order to two groups of a plurality of data bit of more said two input ends.Change if a plurality of bit data of the output signal of said second shift register 202 and a plurality of bit data of said first input end DATA_in are essentially different logical, so said error detect circuit 203 can be selected the output signal of said second shift register 202.In another embodiment, said error detect circuit 203 can be edge detector (edge detector), in order to the edge variation of the bit data of the first output terminal DATA_out that detects first order data transmission device 211.Because said serial input data is made up of the digital data of a plurality of logical zeros and logical one, when data transmission just often, said error detect circuit 203 can detect logical zero to 1, perhaps the edge variation of logical one to 0.When said error detect circuit 203 is read continuous a plurality of logical one or logic zero signal, run into the situation of circuit open circuit (stuck open), short circuit (stuck short) or transmitting device fault during the representative data transmission.Under above-mentioned condition; Said error detect circuit 203 optionally switches receiving the bit data of second shift register 202 in self data transmission device 212, and bypass (bypass) is from the error message of the bit data of the first output terminal DATA_out of prime data transmission device 211.When data transmission just often, said error detect circuit 203 optionally switches with the bit data of the first output terminal DATA_out that receives prime data transmission device 211 input signal as said first shift register 201.Through the aforesaid operations mode, when wherein malfunction and failures that said serial transmission device links, said serial input data can skip over the transmitting device of said fault and continue transmission.
Fig. 2 C shows the oscillogram of the input and output signal of said serial transmission device 21.In the present embodiment, being used for latching bit data that said first shift register 201 deposits in is to produce 205 generations of circuit by latching to the latch signal of corresponding latch 204.Said latch cicuit produces circuit 205 and receives said clock signal clk, and after each that treat said serial data was all deposited in corresponding shift register, said clock signal clk can be exported a particular level in a continuous time.Said latch produce circuit 205 and detect said particular level and keep a schedule time after, promptly produce a pulse signal with as said latch signal.In another embodiment of the present invention, said latch signal can be an external signal.
According to one embodiment of the invention, the second input end DATA_pre of said data transmission device 213 is the input data that are used for receiving the first input end DATA_in of prime data transmission device 212.According to another embodiment of the present invention, the second input end DATA_pre of said data transmission device 213 can be used to receive data transmission device 211 or more the input data of the first input end DATA_in of the data transmission device of prime (not shown) to increase the fault-tolerant ability of said serial transmission device 21.
Fig. 3 A shows the synoptic diagram of serial transmission device 31 according to an embodiment of the invention, and said serial transmission device 31 comprises a plurality of data transmission devices connected in series.For the sake of brevity, the data transmission device that Fig. 3 A connects with the level Four serial mode is the example explanation, and Fig. 3 B shows the circuit block diagram according to its inside.Said data transmission device 31 has clock signal terminal CLK, first input end SIN
1, the second input end SIN
2, the first output terminal SOUT
1, the second output terminal SOUT
2With a plurality of parallel output terminal OUT
1, OUT
2... OUT
NIn the present embodiment, said data transmission device comprises first shift register 301, error detect circuit 302, second shift register 303, latch 304 and latchs and produces circuit 305.Said first shift register 301 is in order to receive from first input end SIN
1Signal, and said second shift register 303 is in order to receive from the second input end SIN
2Signal.Said error detect circuit 302 has two input ends; One of them input end is used for receiving the output data of said first shift register 301; And another input end is used for receiving the output data of said second shift register 303; And optionally switch wherein one the bit data of said two input ends,, a latch signal latchs synchronously in the latch 304 of said data in correspondence after triggering.Each level of said latch 304 is electrically connected on parallel output terminal OUT
1, OUT
2... OUT
N, so as to the serial data of importing being converted into the output format of parallel type.Said latching produces circuit 305 in order to after detecting said clock signal clk and exporting a particular level and keep a continuous time, to produce said latch signal.
The principle of work explanation of said serial transmission device 31 as follows.At first, forward-chaining input data are by the first input end SIN of data transmission device 311
1Receive, and be transferred to first shift register 301 in the said data transmission device 311.Another reverse serial input data is by the second input end SIN of data transmission device 314
2Receive, and be transferred to second shift register 303 in the said data transmission device 314.The bit data of said reverse serial input data is with the reverse order output of the bit data of said forward-chaining input data, and for example, when said forward-chaining input data were (1,1,0,0,1,1,0), said reverse serial input data was (0,1,1,0,0,1,1).
In the present embodiment; Error detect circuit 302 among each data transmission device 311-314 is a bit comparator; Whether there is identical in fact logic to change in order to two groups of a plurality of data bit of more said two input ends, it is said that and the fan-in factor of choosing is passed to said latch 304.In another embodiment, said error detect circuit 302 is an edge detector, changes in order to the logic of the bit data that detects said first shift register 301 output.When error detect circuit 302 is read continuous a plurality of logical one or logic zero signal or first serial input signals and the second serial input signals logic not simultaneously; Run into the situation of previous stage transmitting device fault during the representative data transmission, error detect circuit 302 selects second serial input signals as real serial input signals.With Fig. 3 C is the example explanation, and the transmission line between the said data transmission device 312 and 313 runs into open loop state, and therefore, the error detect circuit 302 of said data transmission device 313 can optionally switch to receive from data transmission device 314 second output terminal SOUT
2Data, and bypass is from said data transmission device 312 first output terminal SOUT
1Error message.In addition; In another embodiment; The failure message of data transmission device can be when said serial transmission device 31 be switched on (Power On); See a forward initialize signal and a reverse initialize signal off by controller, said forward initialize signal can be transferred to said data transmission device 314 by said data transmission device 311, and said reverse initialize signal can be transferred to said data transmission device 311 by said data transmission device 314.When wherein malfunction and failures that said serial transmission device links, said serial input data can be learnt the transmitting device of fault through said error detect circuit 302.
According to one embodiment of the invention, the first input end SIN of said data transmission device 313
1Be the first output terminal SOUT that is used for receiving prime data transmission device 312
1Output data.According to another embodiment of the present invention, the first input end SIN of data transmission device 313
1Can be used to receive preceding second level data transmission device 311 or the first output terminal SOUT of prime more
1Output data, to increase the fault-tolerant ability of said serial transmission device 31.Similarly, the second input end SIN of data transmission device 313
2Can be used to receive the afterwards second level or the more second output terminal SOUT of back grade data transmitting device (not shown)
2Output data.
Technology contents of the present invention and technical characterstic disclose as above, yet the those skilled in the art still maybe be based on teaching of the present invention and announcement and done all replacement and modifications that does not break away from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to embodiment and disclose, and should comprise various do not break away from replacement of the present invention and modifications, and is contained by appending claims.
Claims (22)
1. serial transmission device, it comprises a plurality of data transmission devices that connect with serial mode, it is characterized in that wherein said data transmission device comprises:
Second shift register in order to receiving second serial input signals, and produces the output signal according to clock signal;
Error detect circuit in order to receiving the output signal and first serial input signals from said second shift register, and selects wherein one to produce the output signal according to the error-detecting result; And
First shift register, in order to the output signal of reception from said error detect circuit, and according to said clock signal generation serial output signal;
Wherein, said second serial input signals is from the input signal of previous stage data transmission device at least, and said first serial input signals is the serial output signal from the previous stage data transmission device.
2. serial transmission device according to claim 1 is characterized in that wherein said data transmission device further comprises latch, in order to latch the parallel output signal from said first shift register according to latch signal.
3. serial transmission device according to claim 2; It is characterized in that wherein said data transmission device further comprises latchs the generation circuit, and said latching produces circuit and just produce said latch signal based on said clock signal output particular level and after keeping setting-up time.
4. serial transmission device according to claim 1; It is characterized in that wherein said error detect circuit is a bit comparator, whether have identical logic to change in order to a plurality of bit data of the output signal of more said second shift register and a plurality of bit data of said first serial input signals.
5. serial transmission device according to claim 4; If it is characterized in that a plurality of bit data of a plurality of bit data and said first serial input signals of the output signal of wherein said second shift register are that different logical changes, so said error detect circuit is selected the output signal of said second shift register.
6. serial transmission device according to claim 1 is characterized in that wherein said error detect circuit is an edge detect circuit, in order to detect the logic level change of said first serial input signals.
7. serial transmission device according to claim 6 is continuous a plurality of logical one or logic zero signal if it is characterized in that the logic of wherein said first serial input signals, and so said error detect circuit is selected the output signal of said second shift register.
8. serial transmission device according to claim 2 is characterized in that wherein said parallel output signal is coupled to light emitting diode.
9. a serial transmission device is characterized in that it comprises a plurality of data transmission devices that connect with serial mode, and wherein said data transmission device comprises:
First shift register in order to receiving first serial input signals, and produces first serial output signal according to clock signal;
Second shift register in order to receiving second serial input signals, and produces second serial output signal according to clock signal; And
Error detect circuit in order to receiving the output signal of said first and second shift registers, and selects wherein one to produce serial output signal according to the error-detecting result;
Wherein, said first serial input signals is first serial output signal from previous stage data transmission device at least, and said second serial input signals is from second serial output signal of back one-level data transmission device at least.
10. serial transmission device according to claim 9 is characterized in that wherein said first serial input signals and said second serial input signals have the output order of opposite bit data.
11. serial transmission device according to claim 9 is characterized in that wherein said data transmission device further comprises latch, in order to latch the parallel output signal from said error detect circuit according to latch signal.
12. serial transmission device according to claim 11; It is characterized in that wherein said data transmission device further comprises latchs the generation circuit, and said latching produces circuit and just produce said latch signal based on said clock signal output particular level and after keeping setting-up time.
13. serial transmission device according to claim 9; It is characterized in that wherein said error detect circuit is a bit comparator, whether have identical logic to change in order to a plurality of bit data of the output signal of a plurality of bit data of the output signal of more said first shift register and said second shift register.
14. serial transmission device according to claim 9 is characterized in that wherein said error detect circuit is an edge detect circuit, in order to the logic level change of the output signal that detects said first shift register and said second shift register.
15. serial transmission device according to claim 14; If it is characterized in that the logic of the output signal of wherein said second shift register is continuous a plurality of logical one or logic zero signal, so said error detect circuit is selected the output signal of said first shift register; If the logic of the output signal of said first shift register is continuous a plurality of logical one or logic zero signal, so said error detect circuit is selected the output signal of said second shift register.
16. serial transmission device according to claim 11 is characterized in that wherein said parallel output signal is coupled to light emitting diode.
17. a serial signals transmission method is characterized in that it comprises following steps:
A plurality of data transmission devices that connect with serial mode are provided, and wherein arbitrary data transmission device has the first serial data input port and the second serial data input port;
The said first serial data input port by previous stage data transmission device output forward-chaining data data transmission device up till now;
The said second serial data input port by the input forward-chaining data of previous stage data transmission device at least data transmission device up till now;
Utilize error detect circuit to compare the data of said first serial data input port and the said second serial data input port, and select wherein one according to the error-detecting result to produce the actual serial input signals of serial output signal as said present data transmission device; And
Said data transmission device produces parallel output signal in order to the driven for emitting lights diode.
18. serial signals transmission method according to claim 17; It is characterized in that whether a plurality of bit data of data of a plurality of bit data and the said second serial data input port that wherein said error-detecting comparison step comprises the data of the more said first serial data input port have identical logic to change, or the data of more said first serial data input port and the said second serial data input port whether logic is continuous a plurality of logical one or logic zero signal.
19. serial signals transmission method according to claim 18; If it is characterized in that the logic of the data of the wherein said first serial data input port is continuous a plurality of logical one or logic zero signal, so said error detect circuit is selected the data of the said second serial data input port; If the logic of the data of the said second serial data input port is continuous a plurality of logical one or logic zero signal, so said error detect circuit is selected the data of the said first serial data input port.
20. a serial signals transmission method is characterized in that it comprises following steps:
A plurality of data transmission devices that connect with serial mode are provided, and wherein arbitrary data transmission device has the first serial data input port and the second serial data input port;
By the previous stage or the said first serial data input port of prime data transmission device output forward-chaining data data transmission device up till now more;
Export the said second serial data input port of reverse serial data data transmission device up till now by back one-level or back grade data transmitting device;
Utilize error detect circuit to compare the data of said first serial data input port and the said second serial data input port, and select wherein one according to the error-detecting result; And
Produce parallel output signal in order to the driven for emitting lights diode.
21. serial signals transmission method according to claim 20; It is characterized in that whether a plurality of bit data of data of a plurality of bit data and the said second serial data input port that wherein said error-detecting comparison step comprises the data of the more said first serial data input port have identical logic to change, or the data of more said first serial data input port and the said second serial data input port whether logic is continuous a plurality of logical one or logic zero signal.
22. serial signals transmission method according to claim 21; If it is characterized in that the logic of the data of the wherein said first serial data input port is continuous a plurality of logical one or logic zero signal, so said error detect circuit is selected the data of the said second serial data input port; If the logic of the data of the said second serial data input port is continuous a plurality of logical one or logic zero signal, so said error detect circuit is selected the data of the said first serial data input port.
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| CN101964171B (en) * | 2010-09-16 | 2013-05-22 | 深圳市明微电子股份有限公司 | Data transmission method |
| CN103857106B (en) | 2012-11-29 | 2016-05-18 | 利亚德光电股份有限公司 | Led drive circuit and control system |
| KR102435257B1 (en) * | 2015-08-04 | 2022-08-25 | 삼성디스플레이 주식회사 | Gate protection circuit and display device including the same |
| CN105141315A (en) * | 2015-09-11 | 2015-12-09 | 江苏万邦微电子有限公司 | Multifunctional anti-radiation serial-parallel conversion device |
| CN112652277B (en) * | 2020-12-22 | 2022-05-17 | 北京奕斯伟计算技术有限公司 | Sampler, display driving chip and display device |
| CN117373377B (en) * | 2023-12-06 | 2024-02-09 | 深圳市绿源半导体技术有限公司 | Signal transmission system and signal transmission control method thereof |
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