CN101748459A - Method for depositing copper film on semiconductor wafer super-uniformly - Google Patents
Method for depositing copper film on semiconductor wafer super-uniformly Download PDFInfo
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- CN101748459A CN101748459A CN200810203809A CN200810203809A CN101748459A CN 101748459 A CN101748459 A CN 101748459A CN 200810203809 A CN200810203809 A CN 200810203809A CN 200810203809 A CN200810203809 A CN 200810203809A CN 101748459 A CN101748459 A CN 101748459A
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- 238000000034 method Methods 0.000 title claims abstract description 96
- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 50
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 50
- 239000010949 copper Substances 0.000 title claims abstract description 50
- 238000000151 deposition Methods 0.000 title description 37
- 239000013078 crystal Substances 0.000 claims abstract description 43
- 238000004070 electrodeposition Methods 0.000 claims abstract description 14
- 239000003792 electrolyte Substances 0.000 claims abstract description 8
- 229910000365 copper sulfate Inorganic materials 0.000 claims abstract 4
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical group [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 claims abstract 4
- 239000008151 electrolyte solution Substances 0.000 claims description 65
- 238000009713 electroplating Methods 0.000 claims description 39
- 238000005516 engineering process Methods 0.000 claims description 22
- 230000008021 deposition Effects 0.000 description 33
- 239000011248 coating agent Substances 0.000 description 11
- 238000000576 coating method Methods 0.000 description 11
- 239000012530 fluid Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000011049 filling Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005518 electrochemistry Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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Abstract
The invention discloses a method applied in electrochemical deposition equipment described in the current invention and provided with two or more than electrodes. The method can prepare uniform copper films with WFNU less than 2.5 percent on the surface of the semiconductor wafer of a large impedance seed crystal layer within a thickness from 50 to the scope; wherein the adopted electrolyte is copper sulfate electrolyte with conductivity from 0.02 to 0.8S/cm.
Description
Relevant patent citation
Present patent application is the extendible portion of the United States Patent (USP) (number of patent application is 09/232,864, and the existing patent No. is 6391166) of submission on January 15th, 1999.The U.S. Provisional Application that United States Patent (USP) 6391166 has been stated on February 12nd, 1998 and submitted to number is 60/074,466 United States Patent (USP) and the U.S. Provisional Application of submission on July 27th, 1998 number is the interests of 60/094,215 United States Patent (USP).The global patent No. that this application has simultaneously also been stated on November 2nd, 2007 and submitted to is the interests of the global patent of PCT/CN2007/071008.All the elements of above-mentioned patent are incorporated in this patent.
The field
The present invention relates in general to a kind of method that adopts electrochemical deposition in super large-scale integration is made, the even copper film of preparation on ultra-thin big impedance inculating crystal layer semiconductor workpiece.
Background
On semiconductor wafer, use a plurality of different treatment steps to make transistor and interconnection element.In forming the process of interconnection element, semiconductor wafer may be through for example: mask, and processing such as etching and deposition, thus form semiconductor transistor and needed electronic circuit, connect these transistor terminal.Particularly, can carry out repeatedly mask, ion implantation, annealing and plasma etching and chemistry and physical vapor deposition step and form narrow groove, transistor well, grid, polysilicon circuit and interconnection line structure, as through hole and groove.
After forming as through hole and groove, the deposition electricity is led the transistor that material connects the bottom in these structures.Remove unnecessary electricity and lead material, make this conductive structures form required circuit.In super large-scale integration was made, employing electrochemical deposition layer of metal film floor on ultrafine big anti-resistance inculating crystal layer formed the electrical lead road, and this metallic diaphragm is copper film normally.But this depositing operation filling vias structure, the mixed structure of groove structure or two kinds of structures.When these structures were filled, copper deposited and forms a skim continuously on semiconductor wafer surface.The final copper film uniformity coefficient that forms is most important, and this is because follow-up usefulness removes the exigent uniformity coefficient of processing step (normally planarisation step CMP) of unnecessary copper, thereby obtains identical electrical property between the device that makes final output and the device.Advanced Technology generally can be controlled at unevenness in the film (WFNU is the ratio of thickness standard deviation and thickness mean value) in 2.5%.
Big WFNU has negative impact to the subsequent CMP processing step, will cause that the local residual or too much dielectric substance of copper is in the loss of throwing copper process.As polishing process the copper on the wafer is removed equally, the initial copper film of Waffer edge is thicker relatively, thereby causes copper or blocking layer remaining at this place, and this non-technology of removing fully will cause the device short circuit.If the copper and the blocking layer of adopting polishing to remove Waffer edge significantly, the dielectric substance of center wafer near zone is excessive loss then, and the height of groove and through hole is reduced, and the resistance on the wafer between interconnection line produces difference.These two kinds of influences all have very big infringement to the yield of device.
For satisfying the update of manufacturing technology, constantly development, wafer size changes 300mm into from 200mm, and inculating crystal layer thickness continues to reduce, thereby the inculating crystal layer ohmic resistance on the semiconductor wafer is significantly increased.(refer generally to electroplate) in the traditional electrical chemical deposition process, power supply provides curtage to single working electrode and the wafer substrate of being with inculating crystal layer.Wafer substrate, working electrode, power supply and electrolytic solution form an electrolyzer.Because the phenomenon of a kind of being called " fringing effect ", the current density on the ultra-thin big impedance wafer is uneven, and is higher relatively at the edge.The even property of this current unevenness makes rate of deposition at the Waffer edge height, and center wafer is low, and then makes the copper layer deposition on the wafer surface in uneven thickness.After inculating crystal layer thickness reduced, and wafer size increases, fringing effect was more remarkable.In serious situation, deposition occurs over just Waffer edge.
Fringing effect can improve by the ionogen that adopts low relatively acid, shown in Fig. 3 a-3d.But along with technical development, it is inhomogeneous only to adopt low acid electrolyte still can't solve by the plating of fringing effect generation.Usually, this ununiformity can be improved by improving coating film thickness, shown in Fig. 3 c-3d.But this will seriously limit the production capacity of processing unit, and increase the cost that subsequent planarization technology is removed excess stock greatly.
In existing patent, existing many designs are applied in the processing unit to solve the non-uniformity problem that fringing effect produces.United States Patent (USP) 6391166 (1999.1.15) has disclosed electroplating device and method, adopts independent current source control electrode system, to overcome the uneven problem of rate of deposition on the ultra-thin inculating crystal layer of semiconductor wafer.United States Patent (USP) 6755954 (2004.6.29) has disclosed a kind of electroplating device and method galvanic deposit copper film, can obtain less relatively thickness deviation, in the example therein, is being with 400
Deposit 0.6um (6000 on the 300mm wafer of inculating crystal layer
) copper film, the copper film thickness deviation that obtains is 394
General introduction
The present invention has disclosed and has been used for a kind of method with electrochemical deposition equipment of a multi-electrode and a power control system.In text of the present invention and diagram, claim that this equipment is described equipment.The example of this equipment was once described in United States Patent (USP) 6391166 and global patent PCT/CN2007/071008.
It is 50 that institute's revealing method is applied to inculating crystal layer thickness
To 900
Wafer electroplating, the specific conductivity of the electrolytic solution that adopts is 0.02 to 0.8S/cm.
Institute's revealing method can be with 350
(thickness deviation is 42 to prepare in the wafer unevenness on the wafer of inculating crystal layer and only be 0.33%
) the electrochemistry copper plating film, than the little several times of previous patent revealing method gained unevenness.
The accompanying drawing summary
The synoptic diagram of equipment described in the existing invention that the present method of describing Fig. 1 adopts;
Fig. 2 describes the partial schematic diagram of unitary electrode electroplating device;
Fig. 3 a-3d describes the deposition profile that adopts the unitary electrode electroplating device to obtain;
Fig. 4 describes the partial schematic diagram with two electroplating equipment for electrode;
Fig. 5 a and 5b describe the oscillogram that two electrode equipments are adopted;
Fig. 6 a and 6b describe the deposition profile that adopts two electrode equipments to obtain;
Fig. 7 describes the partial schematic diagram with three electroplating equipment for electrode;
Fig. 8 a and 8b describe the oscillogram of the employing of three electrode equipments;
Fig. 9 a and 9b describe the deposition profile that adopts three electrode equipments to obtain;
Figure 10 describes the partial schematic diagram with four electroplating equipment for electrode;
Figure 11 a and 11b describe the oscillogram that four electrode equipments adopt;
Figure 12 a and 12b describe the deposition profile that adopts four electrode equipments to obtain;
Figure 13 describes the deposition profile that adopts ten electrode equipments to obtain;
Figure 14 describes the deposition profile that calculates;
Describe in detail
The of the present invention announcement is used for a kind of method with electrochemical deposition equipment of a multi-electrode and a power control system.It is 50 that institute's revealing method is applied to inculating crystal layer thickness
To 900
Wafer electroplating, the specific conductivity of the electrolytic solution that adopts is 0.02 to 0.8S/cm.This method will be implemented in the equipment that United States Patent (USP) 6391166 is disclosed.
The inventive method may further comprise the steps:
Inject the electrolyte into described equipment, electrolyte flow rate is in 1 to 20LPM scope;
Wafer handling to the wafer holding unit, can be conducted electricity between this device and wafer;
Wafer is applied a little bias voltage;
Wafer is delivered in the electrolytic solution, and the front surface of wafer is contacted fully with electrolytic solution;
To each electrode power supply stream; Each power supply that links to each other with each electrode can switch to current-mode from voltage mode in the moment that requires;
Provide a relative less current or voltage to each electrode, total current is advisable with 2A to 10A, and the current density ratio between the electrode is 0.5: 1 to 300: 1;
Provide a relatively large curtage to each electrode, total current is advisable with 10A to 40A, and the current density ratio between the electrode is 0.5: 1 to 300: 1;
Switching to a little bias mode is applied on the described semiconductor wafer;
Wafer is taken out electrolytic solution;
Stop the power supply supply, and remove the residual electrolytic solution of wafer surface.
In above-mentioned the 6th step and the 7th step, according to the number of electrodes of using, electrolytic conductivity makes on each electrode that current density ratio changes between the distribution of current and electrode among a small circle.In following example, will specify these scopes at special electrodes quantity and electrolytic conductivity.
In one example, disclosed a kind of method that is applied to described two electrode equipments, wherein the electrolytic conductivity that adopts is 0.02-0.2S/cm.
In one example, disclosed a kind of method that is applied to described two electrode equipments, wherein the electrolytic conductivity that adopts is 0.2-0.8S//cm.
In one example, disclosed a kind of method that is applied to described three electrode equipments, wherein the electrolytic conductivity that adopts is 0.02-0.2S/cm.
In one example, disclosed a kind of method that is applied to described three electrode equipments, wherein the electrolytic conductivity that adopts is 0.2-0.8S//cm.
In one example, disclosed a kind of method that is applied to described four electrode equipments, wherein the electrolytic conductivity that adopts is 0.02-0.2S/cm.
In one example, disclosed a kind of method that is applied to described four electrode equipments, wherein the electrolytic conductivity that adopts is 0.2-0.8S//cm.
In one example, disclosed a kind of method that is applied to described ten electrode equipments, wherein the electrolytic conductivity that adopts is 0.02-0.2S/cm.
In one example, disclosed a kind of method that is applied to described ten electrode equipments, wherein the electrolytic conductivity that adopts is 0.2-0.8S//cm.
Fig. 2 has described a traditional electrical coating apparatus that has single electrode 201.The deposition profile of Fig. 3 a-3d for adopting this single electrode electroplating device on the 300mm semiconductor wafer surface, to obtain.Particularly, to have described tape thickness be 350 to Fig. 3 a-3b
To 900
Inculating crystal layer on semiconductor wafer, deposit 3000
The deposition profile of thick copper film has adopted low conductivity and high conductivity electrolytic solution respectively.Fig. 3 c-3d has described and has been with 350
Be deposited as 3000 on the semiconductor wafer of inculating crystal layer
To 6000
The deposition profile of thick copper film has adopted low conductivity and high conductivity electrolytic solution respectively.
List in table 1 by the WFNU value that the thickness profile among Fig. 3 a-3b calculates.The WFNU value reduces and increases with inculating crystal layer thickness, has illustrated, when inculating crystal layer is very thin, is difficult in semiconductor wafer surface depositing copper film equably.When inculating crystal layer thickness less than 700
The time, adopt traditional single electrode electroplating device can't make the WFNU value less than 2.5%.When electrolytic conductivity increased, situation was poorer.
Table 1
Shown in Fig. 3 c-3d, identical 350
On the inculating crystal layer, WFNU increases with the electroplating film layer thickness and improves.Analog value is listed in surface 2.This phenomenon is because the rete ohmic resistance that thickens in the deposition process reduces, thereby has reduced fringing effect.At electroplating thickness less than 5000
Situation under, the WFNU value is greater than 2.5%, under the high situation of the specific conductivity of electrolytic solution, the WFNU value is much larger than 2.5%.Can improve WFNU though increase electroplating thickness,, thereby not allow depositional coating blocked up because the subsequent CMP step in the IC technical process need expensively remove unnecessary copper film.
Table 2
All analyses of the present invention are all based on thinner inculating crystal layer (350
) and electroplating thickness (3000
), such combination makes the method that discloses have very high susceptibility.
Example 1
In a demonstration example of the present invention, disclosed the method for uniform deposition copper film on a kind of semiconductor wafer that is applied to equipment shown in Figure 4.This equipment is a demonstration example of Fig. 1 invention, and it comprises the first electrode 401a and the second electrode 401b, and wherein first electrode area is the 50%-90% of total electrode area, and the ratio of all electrode area summations and semiconductor wafer area is greater than 0.85.This method may further comprise the steps:
Step 1: open fluid control device 423a and 423b, to control the flow velocity of each electrode work area, in the work area of 401a, flow velocity is 5 to 20LPM, and in the work area of 401b, flow velocity is 1 to 15LPM.In a demonstration example of the present invention, fluid control device 423a and 423b open simultaneously, and in another demonstration example of the present invention, fluid control device 423a opens in the different time with 423b;
Step 2: transmit on the semiconductor wafer the have inculating crystal layer wafer holding unit 421 in the equipment, this device contacts with the semiconductor wafer inculating crystal layer and can be its conduction;
Step 3: described semiconductor wafer is applied a little bias voltage, and its scope is at 0.01-10V;
Step 4: with the wafer holding unit wafer is delivered in the electrolytic solution, and made the front surface of wafer immerse electrolytic solution fully;
Step 5: to electrode 401a and 401b power supply stream, and keep electrode 401a to go up voltage for just, the last voltage of 401b is plus or minus (the relative wafer of the sign of voltage herein); The working current of electrode 401a is 5 to 20A, and the working current of electrode 401b is 0.01 to 10A.Current density ratio on electrode 401a and the 401b is 1: 1 to 300: 1.This step continues 5 to 30 seconds, the through hole and the groove on filling semiconductor wafer 422 surfaces.In a demonstration example of the present invention, the power supply that links to each other with 401b with electrode 401a switches to current-mode from voltage mode simultaneously; In another demonstration example of the present invention, switch to current-mode in the different time from voltage mode with the power supply that electrode 401a links to each other with 401b;
Step 6: to electrode 401a and 401b power supply stream, and keep electrode 401a to go up voltage for just, the last voltage of 401b is plus or minus; The working current of electrode 401a is 15 to 40A, and the working current of electrode 401b is 0.01 to 20A.Current density ratio on electrode 401a and the 401b is 1: 1 to 300: 1.This step applies relatively large electric current on electrode 401a and 401b, thereby improves the efficient of electrochemical deposition.When the thick film that deposition obtains requiring, stop this step.
Step 7: on described semiconductor wafer, apply a little bias voltage.In a demonstration example of the present invention, electrode 401a and 401b switch to voltage mode from current-mode simultaneously; In another demonstration example of the present invention, electrode 401a switches to voltage mode in the different time from current-mode with 401b;
Step 8: wafer is taken out electrolytic solution, and the residual electrolytic solution of wafer surface is removed in rotation;
In above-mentioned step 5 and step 6, the sign symbol of electrode 401b voltage is by the electrochemical deposition conditional decision.For example, when the specific conductivity of electrolytic solution is low, the semiconductor wafer surface conductance layer is thick, and counter electrode 401a and 401b apply positive voltage simultaneously, shown in Fig. 5 a; When the specific conductivity height of electrolytic solution, the semiconductor wafer surface conductance layer is thin, and counter electrode 401a applies positive voltage, and counter electrode 401b applies negative voltage, shown in Fig. 5 b.
In the step 5, be 200 to 2000 at inculating crystal layer
The 300mm semiconductor wafer on uniformly-coating the copper film current density ratio and each the electrode voltage sign symbol that are adopted, specifically be provided with as table 3,
The electrolytic conductivity that is adopted is respectively 0.02-0.2S/cm and 0.2-0.8S/cm:
Table 3
When sedimentary copper film thickness reaches 1500
After, beginning step 6.At inculating crystal layer is 200 to 2000
The 300mm semiconductor wafer on uniformly-coating the copper film current density ratio and each the electrode voltage sign symbol that are adopted, specifically be provided with as table 4, the electrolytic conductivity that is adopted is respectively 0.02-0.2S/cm and 0.2-0.8S/cm:
Table 4
Fig. 6 a and 6b have described 350
Electroplate 3000 on the inculating crystal layer
The deposition profile of thick copper film, the electrolytic solution that is adopted are respectively low conductivity and high conductivity electrolytic solution.Wherein, the profile of method 1 is for adopting the processing parameter gained in table 3 and the table 4, and the profile of method 2 is for adopting table 3 and the described extraneous processing parameter gained of table 4.The WFNU value is listed in the table 5.Shown in Fig. 6 a-6b and table 5, the method that is disclosed makes and adopts high conductivity and low conductivity electrolytic solution deposition 3000
The WFN U of rete is all improved significantly.The WFN U of deposition profile calculates and gets rid of 2.3mm zone, edge on the described 300mm semiconductor wafer, and this calculates strict a lot than 3.0 to the 6.5mm zones, eliminating edge of adopting in the common industry.
Table 5
Adopt under the situation of high conductivity and low conductivity electrolytic solution, revealing method (method 1) all makes WFN U be able to remarkable improvement than traditional method (method 2).Especially under the situation that adopts low conductivity electrolytic solution, the WFNU that obtains is less than 2.5%.
Example 2
In a demonstration example of the present invention, disclosed the method for uniform deposition copper film on a kind of semiconductor wafer that is applied to equipment shown in Figure 7.This equipment is a demonstration example of Fig. 1 invention, it comprises the first electrode 701a, the second electrode 701b, with third electrode 701c, wherein first electrode area is the 40%-60% of total electrode area, and the ratio of all electrode area summations and semiconductor wafer area is greater than 0.85.This method may further comprise the steps:
Step 1: open fluid control device 723a, 723b and 723c are to control the flow velocity of each electrode work area, in the work area of 701a, flow velocity is 5 to 20LPM, in the work area of 701b, flow velocity is 5 to 20LPM, and in the work area of 701c, flow velocity is 1 to 15LPM.In a demonstration example of the present invention, fluid control device 723a, 723b and 723c open simultaneously, in another demonstration example of the present invention, fluid control device 723a, 723b opens in the different time with 723c;
Step 2: transmit on the semiconductor wafer the have inculating crystal layer wafer holding unit 721 in the equipment, this device contacts with the semiconductor wafer inculating crystal layer and can be its conduction;
Step 3: described semiconductor wafer is applied a little bias voltage, and its scope is at 0.01-10V;
Step 4: with the wafer holding unit wafer is delivered in the electrolytic solution, and made the front surface of wafer immerse electrolytic solution fully;
Step 5: to electrode 701a, 701b and 701c power supply stream, and keep electrode 701a and 701b to go up voltage for just, the last voltage of 701c is plus or minus; The working current of electrode 701a is 2 to 20A, and the working current of electrode 701b is 0.01 to 20A, and the working current of electrode 701c is 0.01 to 20A.Current density ratio on electrode 701a and the 701b is 1: 1 to 50: 1, and the current density ratio on electrode 701a and the 701c is 1: 1 to 300: 1.This step continues 5 to 30 seconds, the through hole and the groove on filling semiconductor wafer 722 surfaces.In a demonstration example of the present invention, with electrode 701a, the power supply that 701b links to each other with 701c switches to current-mode from voltage mode simultaneously; In another demonstration example of the present invention, with electrode 701a, the power supply that 701b links to each other with 701c switches to current-mode in the different time from voltage mode;
Step 6: to electrode 701a, 701b and 701c power supply stream, and keep electrode 701a and 701b to go up voltage for just, the last voltage of 701c is plus or minus; The working current of electrode 701a is 4 to 30A, and the working current of electrode 701b is 4 to 30A, and the working current of electrode 701c is 0.1 to 20A.Current density ratio on electrode 701a and the 701b is 1: 1 to 50: 1, and the current density ratio on electrode 701a and the 701b is 1: 1 to 300: 1.This step applies relatively large electric current at electrode 701a on 701b and the 701c, thereby improves the efficient of electrochemical deposition.When the thick film that deposition obtains requiring, stop this step.
Step 7: on described semiconductor wafer, apply a little bias voltage.In a demonstration example of the present invention, electrode 701a, 701b and 701c switch to voltage mode from current-mode simultaneously; In another demonstration example of the present invention, electrode 701a, 701b switches to voltage mode in the different time from current-mode with 701c;
Step 8: wafer is taken out electrolytic solution, and the residual electrolytic solution of wafer surface is removed in rotation;
In above-mentioned step 5 and step 6, the sign symbol of electrode 701c voltage is by the electrochemical deposition conditional decision.For example, when the specific conductivity of electrolytic solution is low, the semiconductor wafer surface conductance layer is thick, counter electrode 701a, and 701b and 701c apply positive voltage simultaneously, shown in Fig. 8 a; When the specific conductivity height of electrolytic solution, the semiconductor wafer surface conductance layer is thin, and counter electrode 701a and 701b apply positive voltage, and counter electrode 701c applies negative voltage, shown in Fig. 8 b.
In the step 5, be 150 to 2000 at inculating crystal layer
The 300mm semiconductor wafer on uniformly-coating the copper film current density ratio and each the electrode voltage sign symbol that are adopted, specifically be provided with as table 6, the electrolytic conductivity that is adopted is respectively 0.02-0.2S/cm and 0.2-0.8S/cm:
Table 6
When sedimentary copper film thickness reaches 1500
After, beginning step 6.At inculating crystal layer is 50 to 2000
The 300mm semiconductor wafer on uniformly-coating the copper film current density ratio and each the electrode voltage sign symbol that are adopted, specifically be provided with as table 7, the electrolytic conductivity that is adopted is respectively 0.02-0.2S/cm and 0.2-0.8S/cm:
Table 7
Fig. 9 a and 9b have described 350
Electroplate 3000 on the inculating crystal layer
The deposition profile of thick copper film, the electrolytic solution that is adopted are respectively low conductivity and high conductivity electrolytic solution.Wherein, the profile of method 1 is for adopting the processing parameter gained in table 6 and the table 7, and the profile of method 2 is for adopting table 6 and the described extraneous processing parameter gained of table 7.WFN U value is listed in the table 8.Shown in Fig. 9 a-9b and table 8, the method that is disclosed makes and adopts high conductivity and low conductivity electrolytic solution deposition 3000
The WFNU of rete is all improved significantly.The WFNU of deposition profile calculates and gets rid of 2.3mm zone, edge on the described 300mm semiconductor wafer, and this calculates strict a lot than 3.0 to the 6.5mm zones, eliminating edge of adopting in the common industry.
Table 8
Adopt under the situation of high conductivity and low conductivity electrolytic solution, revealing method (method 1) all makes WFNU be able to remarkable improvement than traditional method (method 2).Especially under the situation that adopts low conductivity electrolytic solution, the WFNU that obtains is less than 2.5%.
Example 3
In a demonstration example of the present invention, disclosed the method for uniform deposition copper film on a kind of semiconductor wafer that is applied to equipment shown in Figure 10.This equipment is a demonstration example of Fig. 1 invention, it comprises the first electrode 1001a, the second electrode 1001b, third electrode 1001c and the 4th electrode 1001d, wherein first electrode area is the 30%-50% of total electrode area, and the ratio of all electrode area summations and semiconductor wafer area is greater than 0.85.This method may further comprise the steps:
Step 1: open fluid control device 1023a, 1023b, 1023c and 1023d, to control the flow velocity of each electrode work area, at 1001a, in the work area of 1001b and 1001c, flow velocity is 5 to 20LPM, and in the work area of 1001d, flow velocity is 1 to 15LPM.In a demonstration example of the present invention, fluid control device 1023a, 1023b, 1023c and 1023d open simultaneously, in another demonstration example of the present invention, fluid control device 1023a, 1023b, 1023c opens in the different time with 1023d;
Step 2: transmit on the semiconductor wafer the have inculating crystal layer wafer holding unit 1021 in the equipment, this device contacts with the semiconductor wafer inculating crystal layer and can be its conduction;
Step 3: described semiconductor wafer is applied a little bias voltage, and its scope is at 0.01-10V;
Step 4: with the wafer holding unit wafer is delivered in the electrolytic solution, and made the front surface of wafer immerse electrolytic solution fully;
Step 5: to electrode 1001a, 1001b, 1001c and 1001d power supply stream, and keep electrode 1001a, 1001b and 1001c to go up voltage for just, the last voltage of 1001d is plus or minus; The working current of electrode 1001a is 1 to 15A, and the working current of electrode 1001b is 0.5 to 10A, and the working current of electrode 1001c and 1001d is 0.01 to 10A.Current density ratio on electrode 1001a and the 1001b is 0.5: 1 to 10: 1, and the current density ratio on electrode 1001a and the 1001c is 0.5: 1 to 50: 1, and the current density ratio on electrode 1001a and the 1001d is 1: 1 to 300: 1.This step continues 5 to 30 seconds, the through hole and the groove on filling semiconductor wafer 1022 surfaces.In a demonstration example of the present invention, with electrode 1001a, 1001b, the power supply that 1001c links to each other with 1001d switches to current-mode from voltage mode simultaneously; In another demonstration example of the present invention, with electrode 1001a, 1001b, the power supply that 1001c links to each other with 1001d switches to current-mode in the different time from voltage mode;
Step 6: to electrode 1001a, 1001b, 1001c and 1001d power supply stream, and keep electrode 1001a, 1001b and 1001c to go up voltage for just, the last voltage of 1001d is plus or minus; The working current of electrode 1001a is 2 to 30A, and the working current of electrode 1001b is 1 to 30A, and the working current of electrode 1001c is 1 to 30A, and the working current of electrode 1001d is 0.01 to 20A.Current density ratio on electrode 1001a and the 1001b is 0.5: 1 to 10: 1, and the current density ratio on electrode 1001a and the 1001c is 0.5: 1 to 50: 1, and the current density ratio on electrode 1001a and the 1001d is 1: 1 to 300: 1.This step is at electrode 1001a, and 1001b applies relatively large electric current on 1001c and the 1001d, thereby improves the efficient of electrochemical deposition.When the thick film that deposition obtains requiring, stop this step.
Step 7: on described semiconductor wafer, apply a little bias voltage.In a demonstration example of the present invention, electrode 1001a, 1001b, 1001c and 1001d switch to voltage mode from current-mode simultaneously; In another demonstration example of the present invention, electrode 1001a, 1001b, 1001c switches to voltage mode in the different time from current-mode with 1001d;
Step 8: wafer is taken out electrolytic solution, and the residual electrolytic solution of wafer surface is removed in rotation;
In above-mentioned step 5 and step 6, the sign symbol of electrode 1001d voltage is by the electrochemical deposition conditional decision.For example, when the specific conductivity of electrolytic solution is low, the semiconductor wafer surface conductance layer is thick, counter electrode 1001a, and 1001b, 1001c and 1001d apply positive voltage simultaneously, shown in Figure 11 a; When the specific conductivity height of electrolytic solution, the semiconductor wafer surface conductance layer is thin, counter electrode 1001a, and 1001b and 1001c apply positive voltage, and counter electrode 1001d applies negative voltage, shown in Figure 11 b.
In the step 5, be 50 to 2000 at inculating crystal layer
The 300mm semiconductor wafer on uniformly-coating the copper film current density ratio and each the electrode voltage sign symbol that are adopted, specifically be provided with as table 9, the electrolytic conductivity that is adopted is respectively 0.02-0.2S/cm and 0.2-0.8S/cm:
Table 9
When sedimentary copper film thickness reaches 1500
After, beginning step 6.At inculating crystal layer is 50 to 2000
The 300mm semiconductor wafer on uniformly-coating the copper film current density ratio and each the electrode voltage sign symbol that are adopted, specifically be provided with as table 10, the electrolytic conductivity that is adopted is respectively 0.02-0.2S/cm and 0.2-0.8S/cm:
Table 10
Figure 12 a and 12b have described 350
Electroplate 3000 on the inculating crystal layer
The deposition profile of thick copper film, the electrolytic solution that is adopted are respectively low conductivity and high conductivity electrolytic solution.Wherein, the profile of method 1 is for adopting the processing parameter gained in table 9 and the table 10, and the profile of method 2 is for adopting table 9 and the described extraneous processing parameter gained of table 10.The WFNU value is listed in the table 11.Shown in Figure 12 a-12b and table 11, the method that is disclosed makes and adopts high conductivity and low conductivity electrolytic solution deposition 3000
The WFNU of rete is all improved significantly.The WFNU of deposition profile calculates and gets rid of 2.3mm zone, edge on the described 300mm semiconductor wafer, and this calculates strict a lot than 3.0 to the 6.5mm zones, eliminating edge of adopting in the common industry.
Table 11
Adopt under the situation of high conductivity and low conductivity electrolytic solution, revealing method (method 1) all makes WFNU be able to remarkable improvement than traditional method (method 2).Especially under the situation that adopts low conductivity electrolytic solution, the WFNU that obtains is less than 2.5%.
Example 4
Aforesaid method of the present invention is used for the simple electrode structural device that United States Patent (USP) 6391166 discloses, revealing method of the present invention is also pressed conceptual design similarly, be applied to have in the equipment more than the electrode structure of four electrodes, wherein, first electrode area of this structure is the 5%-30% of total electrode area, and the ratio of all electrode area summations and semiconductor wafer area is greater than 0.85.
At inculating crystal layer is 50 to 2000
The 300mm semiconductor wafer on uniformly-coating 100
To 1500
The current density ratio that thick copper film adopted and each electrode voltage sign symbol specifically make as table 12, and the electrolytic conductivity that is adopted is respectively 0.02-0.2S/cm and 0.2-0.8S/cm.In the case, electroplating device has N electrode, and N can change between 5 to 15.
Table 12
Afterwards, be 50 to 2000 at inculating crystal layer
The 300mm semiconductor wafer on uniformly-coating remainder the copper film current density ratio and each the electrode voltage sign symbol that are adopted, specifically be provided with as table 13, the electrolytic conductivity that is adopted is respectively 0.02-0.2S/cm and 0.2-0.8S/cm:
Table 13
Table 13 has been described and has been adopted respectively under the situation of low conductivity electrolytic solution 1 and high conductivity electrolytic solution 2, with described equipment 350
Electroplate 3000 on the inculating crystal layer
The deposition profile of thick copper film.Wherein, described demonstration example equipment has ten independent controllable electrodes.The WFNU value that obtains with the inventive method is significantly less than 2.5%, and being respectively in the electrolytic solution 1 is 0.26%, is 0.59% in the electrolytic solution 2.
On the basis of the method that the present invention discloses, the WFNU that obtains can increase with number of electrodes N and improve.When adopting number of electrodes, be with 350 with these methods greater than 1 equipment
Electroplating copper film can obtain the WFNU less than 2.5% on the inculating crystal layer wafer.When N is increased to 4, on same wafer and inculating crystal layer, electroplate the WFNU that obtains and reduce to 0.33%.
The method of the present invention's announcement and the method for United States Patent (USP) 6755954 announcements are compared.Keep all conditions identical: (1) multiple electrode structure (2) electrolytic conductivity=0.5S/cm, (3) inculating crystal layer thickness=400
, (4) total electroplating thickness=6000
, and (5) eliminating Waffer edge 2.7mm zone copper is thick.For direct comparison, the used thickness homogeneity range replaces WFNU.Figure 14 has described the deposition profile that the method that discloses with the present invention calculates.The correlative value of thickness homogeneity range is listed in table 14
Table 14
The WFNU of the depositing copper film that revealing method of the present invention obtains is 0.72%, and the thickness homogeneity range is 138.4
, compare with United States Patent (USP) 6755954 revealing methods and to have improved 2 times.
Claims (30)
1. a method that is used to have the electrochemical deposition uniform copper film device of two electrodes may further comprise the steps, and wherein first electrode area is the 50%-90% of total electrode area,
Copper sulfate electrolyte is injected described equipment, and flow is 1 to 20LPM;
Semiconductor wafer is sent on the wafer holding unit, makes this device and wafer conductance layer have conduction to contact;
Opening power, for semiconductor wafer provides maximum can be to the bias voltage of 10V;
Semiconductor wafer delivered in the electrolytic solution contact with it;
Keep the relative wafer of first electrode voltage for just;
The first step electroplating technology, the total current of 2A to 10A is provided and is to each electrode, when the relative wafer of second electrode voltage is timing, first electrode is 1 with second electrode current density ratio: 1-30: 1, when the relative wafer of second electrode voltage when negative, first electrode is 2 with second electrode current density ratio: 1-30: 1;
The second step electroplating technology, the total current of 10A to 40A is provided and is to each electrode, when the relative wafer of second electrode voltage is timing, first electrode is 1 with second electrode current density ratio: 1-30: 1, when the relative wafer of second electrode voltage when negative, first electrode is 10 with second electrode current density ratio: 1-30: 1;
Switching power provides the maximum can be to the bias voltage of 10V to semiconductor wafer;
Semiconductor wafer is taken out electrolytic solution.
2. the method for claim 1, wherein the total area of all electrodes and the ratio of chip area are greater than 0.85.
3. the method for claim 1, when wherein advancing the first step electroplating technology, when the relative wafer of voltage of second electrode for negative, be in 0.02 to the 0.2S/cm electrolytic solution in specific conductivity, first electrode is 15 with second electrode current density ratio: 1-30: 1.
4. the method for claim 1, when wherein advancing the first step electroplating technology, when the relative wafer of voltage of second electrode for negative, be in 0.2 to the 0.8S/cm electrolytic solution in specific conductivity, first electrode is 2 with second electrode current density ratio: 1-15: 1.
5. the method for claim 1 wherein advanced for second step during electroplating technology, when the relative wafer of voltage of second electrode for negative, be in 0.02 to the 0.2S/cm electrolytic solution in specific conductivity, first electrode is 15 with second electrode current density ratio: 1-30: 1.
6. the method for claim 1 wherein advanced for second step during electroplating technology, when the relative wafer of voltage of second electrode for negative, be in 0.2 to the 0.8S/cm electrolytic solution in specific conductivity, first electrode is 10 with second electrode current density ratio: 1-20: 1.
7. the method for claim 1, wherein semiconductor wafer inculating crystal layer thickness is 50to
8. the method for claim 1, wherein the WFNU of electroplating copper film can be adjusted in 0.2% to 2.5% scope on the semiconductor wafer.
9. the method for claim 1, wherein each electrode can place same vertical height.
10. the method for claim 1, wherein each electrode can place different vertically height.
11. a method that is used to have the electrochemical deposition uniform copper film device of three electrodes may further comprise the steps, wherein first electrode area is the 40%-60% of total electrode area,
Copper sulfate electrolyte is injected described equipment, and flow is 1 to 20LPM;
Semiconductor wafer is sent on the wafer holding unit, makes this device and wafer conductance layer have conduction to contact;
Opening power, for semiconductor wafer provides maximum can be to the bias voltage of 10V;
Semiconductor wafer delivered in the electrolytic solution contact with it;
Keep the relative wafer of first electrode voltage for just;
The first step electroplating technology, the total current of 2A to 10A is provided and is to each electrode, when the relative wafer of third electrode voltage is timing, first electrode is 1 with second electrode current density ratio: 1-2: 1, first electrode and third electrode current density ratio are 1: 1-300: 1, when the relative wafer of third electrode voltage when negative, first electrode is 1 with second electrode current density ratio: 1-20: 1, the first electrode and third electrode current density ratio are 2: 1-40: 1;
The second step electroplating technology, the total current of 10A to 40A is provided and is to each electrode, when the relative wafer of third electrode voltage is timing, first electrode is 1 with second electrode current density ratio: 1-2: 1, first electrode and third electrode current density ratio are 1: 1-300: 1, when the relative wafer of third electrode voltage when negative, first electrode is 1 with second electrode current density ratio: 1-2: 1, the first electrode and third electrode current density ratio are 20: 1-300: 1;
Switching power provides the maximum can be to the bias voltage of 10V to semiconductor wafer;
Semiconductor wafer is taken out electrolytic solution.
12. method as claimed in claim 11, wherein the total area of all electrodes and the ratio of chip area are greater than 0.85.
13. method as claimed in claim 11, when wherein advancing the first step electroplating technology, when the relative wafer of voltage of third electrode for negative, in specific conductivity is in 0.02 to the 0.2S/cm electrolytic solution, first electrode is 1 with second electrode current density ratio: 1-2: 1, the first electrode and third electrode current density ratio are 10: 1-40: 1.
14. method as claimed in claim 11, when wherein advancing the first step electroplating technology, when the relative wafer of voltage of third electrode for negative, in specific conductivity is in 0.2 to the 0.8S/cm electrolytic solution, first electrode is 5 with second electrode current density ratio: 1-20: 1, the first electrode and third electrode current density ratio are 2: 1-10: 1.
15. method as claimed in claim 11, wherein advanced for second step during electroplating technology, when the relative wafer of voltage of third electrode for negative, in specific conductivity is in 0.02 to the 0.2S/cm electrolytic solution, first electrode is 1 with second electrode current density ratio: 1-2: 1,, first electrode and third electrode current density ratio are 50: 1-300: 1.
16. method as claimed in claim 11, wherein advanced for second step during electroplating technology, when the relative wafer of voltage of third electrode for negative, in specific conductivity is in 0.2 to the 0.8S/cm electrolytic solution, first electrode is 1 with second electrode current density ratio: 1-2: 1, the first electrode and third electrode current density ratio are 20: 1-80: 1.
17. method as claimed in claim 11, wherein semiconductor wafer inculating crystal layer thickness is 50to
18. the method for claim 1, wherein the WFNU of electroplating copper film can be adjusted in 0.2% to 2.5% scope on the semiconductor wafer.
19. method as claimed in claim 11, wherein each electrode can place same vertical height.
20. method as claimed in claim 11, wherein each electrode can place different vertically height.
21. a method that is used to have the electrochemical deposition uniform copper film device of four or more electrode may further comprise the steps, wherein first electrode area is the 5%to 50% of total electrode area,
Copper sulfate electrolyte is injected described equipment, and flow is 1 to 20LPM;
Semiconductor wafer is sent on the wafer holding unit, makes this device and wafer conductance layer have conduction to contact;
Opening power, for semiconductor wafer provides maximum can be to the bias voltage of 10V;
Semiconductor wafer delivered in the electrolytic solution contact with it;
Keep the relative wafer of first electrode voltage for just;
The first step electroplating technology, the total current of 2A to 10A is provided and is to each electrode, when an end relative wafer of electrode voltage is timing, first electrode is 0.5 with second electrode current density ratio: 1-10: 1, first electrode is 1 with an end electrode current density ratio: 1-300: 1, first electrode is 0.5 with other electrode current density ratio: 1-2: 1, when an end relative wafer of electrode voltage when negative, first electrode is 0.5 with second electrode current density ratio: 1-2: 1, first electrode is 1 with an end electrode current density ratio: 1-300: 1, the first electrode is 0.5 with other electrode current density ratio: 1-30: 1;
The second step electroplating technology, the total current of 10A to 40A is provided and is to each electrode, when an end relative wafer of electrode voltage is timing, first electrode is 0.5 with second electrode current density ratio: 1-10: 1, first electrode is 1 with an end electrode current density ratio: 1-300: 1, first electrode is 0.8 with other electrode current density ratio: 1-2: 1, when an end relative wafer of electrode voltage when negative, first electrode is 0.5 with second electrode current density ratio: 1-2: 1, first electrode is 1 with an end electrode current density ratio: 1-300: 1, the first electrode is 0.5 with other electrode current density ratio: 1-10: 1;
Switching power provides the maximum can be to the bias voltage of 10V to semiconductor wafer;
Semiconductor wafer is taken out electrolytic solution.
22. method as claimed in claim 21, wherein the total area of all electrodes and the ratio of chip area are greater than 0.85.
23. method as claimed in claim 21, when wherein advancing the first step electroplating technology, when the relative wafer of voltage of an end electrode for negative, in specific conductivity is in 0.02 to the 0.2S/cm electrolytic solution, first electrode is 0.5 with second electrode current density ratio: 1-3: 1, first electrode is 10 with an end electrode current density ratio: 1-100: 1, the first electrode is 0.5 with other electrode current density ratio: 1-2: 1.
24. method as claimed in claim 21, when wherein advancing the first step electroplating technology, when the relative wafer of voltage of an end electrode for negative, in specific conductivity is in 0.2 to the 0.8S/cm electrolytic solution, first electrode is 4 with second electrode current density ratio: 1-40: 1,, first electrode is 2 with an end electrode current density ratio: 1-100: 1, the first electrode is 1 with other electrode current density ratio: 1-2: 1.
25. method as claimed in claim 21, wherein advanced for second step during electroplating technology, when the relative wafer of voltage of an end electrode for negative, in specific conductivity is in 0.02 to the 0.2S/cm electrolytic solution, first electrode is 0.5 with second electrode current density ratio: 1-10: 1, first electrode is 10 with an end electrode current density ratio: 1-200: 1, the first electrode is 0.5 with other electrode current density ratio: 1-2: 1.
26. method as claimed in claim 21, wherein advanced for second step during electroplating technology, when the relative wafer of voltage of an end electrode for negative, in specific conductivity is in 0.2 to the 0.8S/cm electrolytic solution, first electrode is 1 with second electrode current density ratio: 1-2: 1,, first electrode is 1 with an end electrode current density ratio: 1-300: 1, the first electrode is 1 with other electrode current density ratio: 1-2: 1.
27. method as claimed in claim 21, wherein semiconductor wafer inculating crystal layer thickness is 50 to
28. method as claimed in claim 21, wherein the WFNU of electroplating copper film can be adjusted in 0.2% to 2.5% scope on the semiconductor wafer.
29. method as claimed in claim 21, wherein each electrode can place same vertical height.
30. method as claimed in claim 21, wherein each electrode can place different vertically height.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102021523A (en) * | 2010-09-29 | 2011-04-20 | 吴江南玻华东工程玻璃有限公司 | Method for eliminating edge effect of coated glass |
| CN106567130A (en) * | 2015-10-10 | 2017-04-19 | 盛美半导体设备（上海）有限公司 | Method for improving roughness of wafers |
| CN108345057A (en) * | 2018-03-23 | 2018-07-31 | 中国科学院长春光学精密机械与物理研究所 | A kind of preparation method and preparation system of large-area metal grating |
| WO2022111210A1 (en) * | 2020-11-26 | 2022-06-02 | Acm Research (Shanghai) , Inc. | Plating apparatus and plating method |
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|---|---|---|---|---|
| CN1290310A (en) * | 1998-02-12 | 2001-04-04 | Acm研究公司 | Plating apparatus and method |
| US7351315B2 (en) * | 2003-12-05 | 2008-04-01 | Semitool, Inc. | Chambers, systems, and methods for electrochemically processing microfeature workpieces |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1290310A (en) * | 1998-02-12 | 2001-04-04 | Acm研究公司 | Plating apparatus and method |
| US7351315B2 (en) * | 2003-12-05 | 2008-04-01 | Semitool, Inc. | Chambers, systems, and methods for electrochemically processing microfeature workpieces |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102021523A (en) * | 2010-09-29 | 2011-04-20 | 吴江南玻华东工程玻璃有限公司 | Method for eliminating edge effect of coated glass |
| CN106567130A (en) * | 2015-10-10 | 2017-04-19 | 盛美半导体设备（上海）有限公司 | Method for improving roughness of wafers |
| CN108345057A (en) * | 2018-03-23 | 2018-07-31 | 中国科学院长春光学精密机械与物理研究所 | A kind of preparation method and preparation system of large-area metal grating |
| WO2022111210A1 (en) * | 2020-11-26 | 2022-06-02 | Acm Research (Shanghai) , Inc. | Plating apparatus and plating method |
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