CN101738794B - Liquid crystal panel - Google Patents
Liquid crystal panel Download PDFInfo
- Publication number
- CN101738794B CN101738794B CN 200810174837 CN200810174837A CN101738794B CN 101738794 B CN101738794 B CN 101738794B CN 200810174837 CN200810174837 CN 200810174837 CN 200810174837 A CN200810174837 A CN 200810174837A CN 101738794 B CN101738794 B CN 101738794B
- Authority
- CN
- China
- Prior art keywords
- sweep trace
- sweep
- liquid crystal
- crystal panel
- pixel column
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 68
- 239000002184 metal Substances 0.000 claims description 24
- 239000010408 film Substances 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 abstract description 24
- 230000000694 effects Effects 0.000 abstract description 13
- 230000009977 dual effect Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 101100006548 Mus musculus Clcn2 gene Proteins 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 101150037603 cst-1 gene Proteins 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 101100496114 Caenorhabditis elegans clc-2 gene Proteins 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000819 phase cycle Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a liquid crystal panel, which is provided with N scanning lines and N pixel columns. The liquid crystal panel comprises the ith scanning line, the (i+1)th scanning line, the (i+3)th scanning line, a first transistor and a first capacitor, wherein the ith scanning line is used for scanning the ith pixel column; the (i+1)th scanning line is used for scanning the (i+1)th pixel column; the (i+3)th scanning line is used for scanning the (i+3)th pixel column; and the ith pixel column is adjacent to the (i+1)th pixel column. The first transistor is coupled between the ith scanning line and the (i+3)th scanning line, and a gate of the first transistor is coupled with the (i+1)th scanning line. The first capacitor is coupled between the ith scanning line and the common end to reduce the feed-through effect on the ith scanning line, wherein N and i are positive integers, and i is less than or equal to N-3.
Description
Technical field
The present invention relates to the liquid crystal panel of a kind of Pixel-level multiplexed (Pixel Level Multiplexing, PLM) framework, and be particularly related to a kind of liquid crystal panel that reduces required gate drivers (gate driver) number.
Background technology
(FPD) is of a great variety for present flat-panel screens, as liquid crystal display (LCD), organic electroluminescence optical display unit (OLED) and plasma scope (PDP) etc.Yet, no matter be which kind of flat-panel screens, the framework all similar of its display panel, namely dispose crisscross sweep trace (scan line) and data line (data line) on substrate (substrate), and each sweep trace and data line infall configuration one pixel (pixel).Pixel receives sweep signal determining whether be enabled or conducting via sweep trace, and when it is switched on via the data line reception of data signal to show image.
The resolution of liquid crystal panel is higher, its required grid drive chip will be more, and each sweep trace all needs to arrange corresponding pad (pad) to be connected to grid drive chip, and this not only needs considerable layout area, also can increase extra manufacturing cost simultaneously.Therefore, how in the situation that keep the pin count that equal resolution reduces required grid drive chip, be one of important development direction of present liquid crystal panel Driving technique.
Fig. 1 is the local circuit schematic diagram according to the liquid crystal panel of known technology.local circuit 100 in liquid crystal panel comprises that many data lines are (as DL1, DL2) and N bar sweep trace (as SEi, SOi, i wherein, N is positive integer, i is the index value of sweep trace, and 0＜i≤N/2), wherein odd scan line SOi is corresponding to strange pixel column 110, even sweep trace SEi is corresponding to dual pixel row 120, wherein dual pixel row 120 comprise respectively that with strange pixel column 110 a plurality of pixel cells are (as 111, 112, 121 and 122), each pixel cell comprises transistor, the element such as liquid crystal capacitance and storage capacitors, pixel cell can adopt known dot structure, pixel cell in Fig. 1 is (as 111, 112, 121 and 122) be only schematic.
Take dual pixel row 120 with strange pixel column 110 as example, dual pixel row 120 are coupled to even sweep trace SEi, strange pixel column 110 is coupled to odd scan line SOi, the other end of odd scan line SOi is coupled to the end of transistor M1, the other end of transistor M1 is coupled to next even sweep trace SEi+1, and the grid of transistor M1 is coupled to even sweep trace SEi.When even sweep trace SEi and SEi+1 all enable (during logic high potential), strange pixel column 110 all can open with dual pixel row 120 so that data line (as DL1, DL2) writing pixel data extremely in corresponding pixel cell (as 111,112).Then, when only having even sweep trace SEi to enable, strange pixel column 110 close and remaining dual pixel row 120 are opened so as data line (as DL
1, DL
2) the writing pixel data to the pixel cell (as 121,122) of pixel column 120 to upgrade the pixel voltage in pixel column 120.All the other odd scan lines, even sweep trace can be analogized with the circuit structure of corresponding pixel cell, do not add at this and give unnecessary details.In addition, it should be noted that transistor M1, M2 in Fig. 1 can be formed at fanout area 150 or non-effective district (the non-active area) of liquid crystal panel.
The waveform of the sweep signal that odd scan line SOi and even sweep trace SEi+1 receive (being the sweep signal that gate drivers institute must export) as shown in Figure 2, Fig. 2 is the sweep signal oscillogram according to Fig. 1, wherein in the front semiperiod of second phase T2, even sweep trace SEi and SEi+1 all enable, at this moment, strange pixel column 110 all can be opened with pixel column 120.Then, interim in the second half of second phase T2, even sweep trace SEi keeps and enables, and even sweep trace SEi+1 is forbidden, and at this moment, only surplus pixel column 120 is opened, and utilizes above-mentioned sequential, just the pixel data in noveler pixel column 110 and dual pixel row 120 sequentially.
Then, even sweep trace SE
i+1Enable in T3 between the third phase in order to upgrade corresponding strange pixel column and dual pixel row, and in first period T1, even sweep trace SE
iCoordinate an even sweep trace SE
i-1Sweep signal, enable in order to upgrade corresponding odd scan line SO in the front semiperiod of first period T1
i-1Strange pixel column (as even sweep trace SE
i+1The front semiperiod at second phase T2 coordinates even sweep trace SE
iAnd enable the same).It should be noted that above-mentioned first period T1, second phase T2 and between the third phase cycle of T3 identical, the sweep signal of all the other sweep traces can the rest may be inferred to upgrade the pixel of whole panel.Utilize the panel framework of Fig. 1, only need the sweep signal of half to drive all pixel cells, also just can reduce the use number of grid drive chip.
In the process that drives, pixel cell can be influenced because of the potential change of sweep signal, namely so-called feedthrough effect (feed through effect).But in second phase T2, dual pixel row 120 only are subject to even sweep trace SE
iThe impact of the negative edge 201 feedthrough effect that produces, strange pixel column 110 can be subject to even sweep trace SE
iThe negative edge 201 and next even sweep trace SE of sweep signal
i+1The impact of the negative edge 202 feedthrough effect that produces of sweep signal.Therefore, in the driving process, the suffered feedthrough effect of strange pixel column 110 is greater than dual pixel row 120.If whole picture gives same grayscale, because the difference of above-mentioned feedthrough effect will cause image quality uneven.
Fig. 3 is the local equivalent circuit diagram according to the liquid crystal panel 100 of Fig. 1.Wherein pixel cell 111 comprises transistor M111, liquid crystal capacitance Clc2 and storage capacitors Cst2, and capacitor C gs2 is used for representing the equivalent capacity between the gate-to-source of transistor M111, and capacitor C gsf is used for representing the equivalent capacity between the gate-to-source of transistor M1.The circuit structure of pixel cell 121 is identical with pixel cell 111, does not add tired stating at this.Equivalent capacity in cooperation Fig. 3 and the signal waveforms of Fig. 2 can calculate the change in voltage (by high voltage Vgh to Vgl) of sweep signal to the impact of the pixel voltage (being the upper stored pixel voltage of liquid crystal capacitance Clc2 and Clc1) of pixel cell 111 and 121.
In second phase T2, pixel voltage on pixel cell 121 only is subject to the impact of the negative edge 201 (please refer to Fig. 2) of even sweep trace SEi, the voltage drop that namely causes via capacitor C gs1, its feed-trough voltage (feed through voltage) Δ V1 can be expressed as follows:
Wherein Cgs1, Clc and the Cst1 in following formula (1) represents corresponding equivalent capacitance value.
Wherein, in following formula (2), n represents the number of the pixel cell in dual pixel row 120, and CX represents the value that Cgs2 connects with (Clc2+Cst2).
By above-mentioned formula (1) and (2) as can be known, the feed-trough voltage Δ V2 that causes due to sweep signal of the pixel cell 111 feed-trough voltage Δ V1 that can cause due to sweep signal greater than pixel cell 121.Therefore, in the driving process, pixel cell 111 can have different change in voltage because of sweep signal from pixel voltage on pixel cell 121, and this can affect quality and stability of demonstration.
In addition, as even sweep trace SE
iDuring forbidding, odd scan line SO
iCan be in the state of float (floating), because many circuit lines or electric capacity etc. are arranged near the grid of transistor M111, the grid voltage that can cause transistor M111 is subject to these electrical couplings effects and drifts to common voltage Vcom and affect pixel voltage on liquid crystal capacitance C1c2.
Summary of the invention
The invention provides a kind of liquid crystal panel, utilize two sweep traces at interval, drive pixel cell with required gate drivers (pin) number of minimizing liquid crystal panel in the mode that coordinates, and the drive waveforms of setting up electric capacity or changing its sweep signal on sweep trace reduces sweep signal to the impact of pixel voltage.
The present invention also provides a kind of liquid crystal panel, set up control line and corresponding transistor (switch) between sweep trace, as long as can scan all sweep traces by control line, reduce thus required gate drivers (pin) number, and reduce thus sweep signal to the feedthrough effect difference of each pixel cell, to increase the display quality of liquid crystal panel.
From the above, the present invention proposes a kind of liquid crystal panel, has a N bar sweep trace and N pixel column, N is positive integer, this liquid crystal panel comprises i sweep trace, i+1 sweep trace, the first transistor and the first electric capacity, wherein said i sweep trace is in order to scan the i pixel column, and described i+1 sweep trace is in order to scan the i+1 pixel column, and wherein said i pixel column is adjacent with described i+1 pixel column; The i+3 sweep trace is in order to scan the i+3 pixel column.The drain electrode of described the first transistor and source electrode are respectively coupled to described i sweep trace and described i+3 sweep trace, and the grid of described the first transistor is coupled to described i+1 sweep trace, and described the first electric capacity is coupled between described i sweep trace and common terminal; Wherein, described i pixel column, described i+1 pixel column and described i+3 pixel column comprise respectively a plurality of pixel cells, and wherein i is that positive integer and i are less than or equal to N-3.
In embodiments of the present invention, this i sweep trace in described liquid crystal panel is odd scan line, and this i+1 sweep trace is even sweep trace.
In embodiments of the present invention, this i sweep trace in described liquid crystal panel is even sweep trace, and this i+1 sweep trace is odd scan line.
In embodiments of the present invention, described common terminal is earth terminal or common voltage end.
In embodiments of the present invention, wherein said the first electric capacity can be formed by the first metal layer, insulation course, the second metal level, passivating film, transparency electrode and at least one through hole (via).Wherein, described insulation course is formed on described the first metal layer, described the second metal level is formed on described the first metal layer, passivating film is formed on described the second metal level, described transparency electrode be formed on described passivating film and described through hole in order to connect described the first metal layer and described transparency electrode.
In embodiments of the present invention, wherein said i+1 sweep trace receives the first sweep signal, and described i+3 sweep trace receives the second sweep signal, and wherein in the front semiperiod of first period, described the first sweep signal enables; During the second, described the first sweep signal enables and described the second sweep signal enabled in the front semiperiod of the described second phase; In between the third phase, described the second sweep signal enables.Described first period, the described second phase was before between the described third phase, and equal in length between described first, second and the third phase before the described second phase.
In embodiments of the present invention, wherein said the first transistor is thin film transistor (TFT), and is formed on fanout area.
The present invention also proposes a kind of liquid crystal panel, has a N bar sweep trace and N pixel column, and N is positive integer, and this liquid crystal panel comprises i sweep trace, i+1 sweep trace, i+3 sweep trace and the first transistor.Wherein, described i sweep trace is in order to scan the i pixel column; Described i+1 sweep trace is in order to scan the i+1 pixel column, and wherein said i pixel column is adjacent with described i+1 pixel column; Described i+3 sweep trace is in order to scan the i+3 pixel column; The drain electrode of described the first transistor and source electrode are respectively coupled to described i sweep trace and described i+3 sweep trace, and the grid of described the first transistor is coupled to described i+1 sweep trace; Wherein, described i+1 sweep trace receives the first sweep signal, and described i+3 sweep trace receives the second sweep signal, and in the front semiperiod of first period, described the first sweep signal enables; During the second, described the first sweep signal enables and described the second sweep signal enabled in the front semiperiod of the described second phase, and in the described second phase, the first enable voltage of described the first sweep signal is greater than the second enable voltage of described the second sweep signal, and wherein i is that positive integer and i are less than or equal to N-3.
In embodiments of the present invention, in between the third phase after the described second phase, described the second sweep signal enables, and described second enable voltage of described the second sweep signal between the described third phase equals described first enable voltage of described the first sweep signal in the described second phase.Described first period, the described second phase was before between the described third phase, and equal in length between described first, second and the third phase before the described second phase.
In embodiments of the present invention, described i pixel column, described i+1 pixel column and described i+3 pixel column comprise respectively a plurality of pixel cells.
In embodiments of the present invention, this i sweep trace in described liquid crystal panel is odd scan line, and this i+1 sweep trace is even sweep trace.
In embodiments of the present invention, this i sweep trace in described liquid crystal panel is odd scan line, and this i+1 sweep trace is even sweep trace.
The present invention also proposes a kind of liquid crystal panel, has a N bar sweep trace and N pixel column, and N is positive integer, and this liquid crystal panel comprises the first control line, the second control line, the 3rd control line, the first transistor and transistor seconds.Wherein said the first control line correspondence is in described i sweep trace and described i+1 sweep trace; Described the second control line correspondence is in i+2 sweep trace and i+3 sweep trace; Described the 3rd control line correspondence is in i+4 sweep trace and i+5 sweep trace; The drain electrode of described the first transistor and source electrode are respectively coupled to described i sweep trace and the second control line, and the grid of described the first transistor is coupled to described the first control line; The drain electrode of described transistor seconds and source electrode are respectively coupled to described i+1 sweep trace and described the first control line, and the grid of described transistor seconds is coupled to described the 3rd control line, wherein, described i sweep trace is adjacent with described i+1 sweep trace, described i+2 sweep trace is adjacent with described i+3 sweep trace, described i+4 sweep trace is adjacent with described i+5 sweep trace, and wherein i is that positive integer and i are less than or equal to N-5.
In embodiments of the present invention, wherein in the scan period of described the first gated sweep line, described the first gated sweep line enables, and described the second control line enables in the front semiperiod of described scan period, and described the 3rd control strip sweep trace enables the second half of described scan period is interim.
In embodiments of the present invention, wherein each of these sweep traces corresponds respectively to a pixel column, and described pixel column has respectively a plurality of pixel cells.
In embodiments of the present invention, this i sweep trace in described liquid crystal panel is odd scan line, and this i+1 sweep trace is even sweep trace.
In embodiments of the present invention, this i sweep trace in described liquid crystal panel is odd scan line, and this i+1 sweep trace is even sweep trace.
The present invention is owing to adopting the multi-strip scanning line mutually arrange in pairs or groups or drive pixel cell with indirect mode, thereby reduce required gate drivers (pin) number of panel, and reduce by the drive waveforms of setting up electric capacity or changing its sweep signal the feedthrough effect that the voltage transitions because of sweep signal causes, and reduce sweep signal to the impact of pixel voltage.
For feature and advantage of the present invention can become apparent more, preferred embodiment cited below particularly, and by reference to the accompanying drawings, be described in detail below.
Description of drawings
Fig. 1 is the liquid crystal panel local circuit schematic diagram according to known technology;
Fig. 2 is the sweep signal oscillogram according to Fig. 1;
Fig. 3 is the local equivalent circuit diagram according to the liquid crystal panel 100 of Fig. 1;
Fig. 4 is the local circuit schematic diagram according to the described liquid crystal panel of first embodiment of the invention;
Fig. 5 is the structural drawing according to the capacitor C st of first embodiment of the invention;
Fig. 6 is the sweep signal oscillogram according to second embodiment of the invention;
Fig. 7 is the local circuit schematic diagram according to the liquid crystal panel of third embodiment of the invention;
Fig. 8 is the sweep signal oscillogram according to Fig. 7;
[primary clustering symbol description]
100,700: the local circuit of liquid crystal panel
110,710: strange pixel column
120,720: the dual pixel row
111,112,121,122: pixel cell
150: fanout area
201: negative edge
202: negative edge
502: through hole
510: insulation course
520: passivating film
610,620: enable voltage
711,712,721,722: pixel cell
810,820: the pulse of sweep signal
DL
1, DL
2: data line
SO
i～SO
i+2: odd scan line
SE
i～SE
i+2: even sweep trace
SC
i～SC
i+2: control line
M1, M2, M111, M121: transistor
M701, M702, M703: transistor
T1: first period
T2: the second phase
T3: between the third phase
Clc1, Clc2: liquid crystal capacitance
Cst2, Cst1: storage capacitors
Cgs2: the equivalent capacity between the gate-to-source of transistor M111
Cgs1: the equivalent capacity between the gate-to-source of transistor M121
Cgsf: the equivalent capacity between the gate-to-source of transistor M1
Cst: electric capacity
M1: the first metal layer
M2: the second metal level
ITO: transparency electrode
Vgh1, Vgh2: the enable voltage value of sweep signal
Vgl: the magnitude of voltage during the sweep trace forbidding
T
s: scan period
T
S1: scan period T
sThe front semiperiod
T
S2: scan period T
sThe later half cycle
Embodiment
The first embodiment
Referring to figs. 1 through Fig. 3, in order to reduce the feed-trough voltage Δ V2 of pixel cell 111, the present embodiment is at odd scan line SO simultaneously
iUpper connection capacitor C st, as shown in Figure 4, Fig. 4 is the local circuit schematic diagram according to the described liquid crystal panel of first embodiment of the invention.Wherein, capacitor C st and odd scan line SO
iOn pixel cell 111 parallel connections, to increase the capacitance after its parallel connection.With reference to above-mentioned formula (2), after setting up capacitor C st, in formula (2) ((Cgs+n * CX+Cst), namely its numerical value becomes large to Cgs+n * CX) become, so feed-trough voltage Δ V2 will reduce and levels off to feed-trough voltage Δ V1.Because capacitor C st is parallel to odd scan line SO
iOn all pixel cells (as 112), so capacitor C st has too and reduces odd scan line SO
iOn the effect of feed-trough voltage of other pixel cell (as 112).
In other odd scan line (as SO
i+1) on, the present embodiment is capacitor C st in parallel equally thereon, to reduce sweep signal to the impact of each (strange or even) sweep trace.The other end of capacitor C st can be coupled to common voltage end Vcom or earth terminal, as long as can increase odd scan line SO
iOn equivalent capacitance value get final product., be not repeated at this as the explanation of above-mentioned Fig. 1 and Fig. 2 about the remaining circuit of Fig. 4 and mode of operation thereof.In addition, because the capacitor C st that large capacitance is arranged exists, so odd scan line more can not be subject to the impact of other circuit and change its magnitude of voltage.
Because capacitor C st must be enough to affect odd scan line SO
iUpper all pixel cells therefore must have larger capacitance, but larger capacitance need usually large tracts of land just can reach.Therefore, the present embodiment designs this capacitor C st in the sandwich construction mode of sandwich, with reference to Fig. 5, Fig. 5 is the structural drawing according to the capacitor C st of the present embodiment, wherein the first metal layer M1 and the second metal level M2 are the two ends of capacitor C st, transparency electrode ITO is positioned at the opposite side of the second metal level M2, and is connected to the first metal layer M1 via through hole 502.Between transparency electrode ITO and the first metal layer M1, therefore can form larger overlapping area to form larger capacitance due to the second metal level M2.Wherein, have passivating film 520 between transparency electrode ITO and the second metal level M2, and have dielectric film 510 between the first metal layer M1 and the second metal level M1.Generally speaking, the material of passivating film (passivation film) 520 is for example silicon dioxide (SiO2), and the material of gate insulating film (gate insulation film) 510 is for example silicon nitride (SiNx).The structure of the capacitor C st of Fig. 5 can be formed by general liquid crystal panel technique, is not repeated at this.
The second embodiment
Except reducing odd scan line SO via setting up capacitor C st
iWith even sweep trace SE
iBetween difference outside, the present embodiment also proposes a kind of drive waveforms via adjusting sweep signal and reduces the method that retracts the difference between voltage Δ V1, Δ V2.
With reference to Fig. 6 and Fig. 1, Fig. 6 is the sweep signal oscillogram according to second embodiment of the invention, is applicable to drive the liquid crystal panel as Fig. 1 simultaneously.Wherein, in second phase T2, make even sweep trace SE
iThe magnitude of voltage of enable voltage 620 be Vgh2, and even sweep trace SE
i+1The magnitude of voltage of enable voltage 610 be Vgh1, wherein Vgh2 is greater than Vgh1.Vgl is even sweep trace SE
i+1Or even sweep trace SE
iMagnitude of voltage during forbidding (or being called logic low potential).Due to even sweep trace SE
i, SE
i+1The sweep signal waveform change, so in known technology formula (1) and formula (2) can be revised as respectively formula (3) as follows with formula (4):
.......................(4)
Via above-mentioned formula (4) as can be known, when magnitude of voltage Vgh1 descended, the voltage Δ V2 that retracts that retracts on voltage Δ V1 and pixel cell 111 on pixel cell 121 can be comparatively approaching.During pixel cell in scanning on whole panel, its sweep signal is as the even sweep trace SE in Fig. 6
iWith even sweep trace SE
i+1Shown in, its sweep signal has time delay, or is called scan period, sequentially with the identical whole panel zone of waveform scanning.Via of the present invention open, can know easily the corresponding sweep signal waveform of all the other sweep traces and sequential thereof by inference those skilled in the art, be not repeated at this.
The 3rd embodiment
Fig. 7 is the circuit diagram according to the liquid crystal panel of third embodiment of the invention, and in Fig. 7, the local circuit 700 in liquid crystal panel comprises that many data lines are (as DL
1, DL
2), control line SC
i, odd scan line SO
iAnd even sweep trace SE
i, wherein i is the index value of sweep trace, if liquid crystal panel comprises N bar sweep trace, and 0＜i≤N/2, i, N are all positive integer.Wherein, each control line is all corresponding to an odd scan line and an even sweep trace, with control line SC
iBe example, its correspondence be odd scan line SO
iWith even sweep trace SE
i, odd scan line SO
iIn order to scanning strange pixel column 710, and even sweep trace SE
iIn order to scan dual pixel row 720, wherein strange pixel column 710 comprises respectively a plurality of pixel cells (as 711,712,721,722) with dual pixel row 720.Structure in pixel cell is identical with known technology, namely has the structures such as liquid crystal capacitance, storage capacitors (not shown) and transistor, can adopt different dot structures according to different demands, is not repeated at this.
Transistor M701 is coupled to odd scan line SO
iWith gated sweep line SC
i+1Between, and the grid of transistor M701 couples i bar control line SL
iTransistor M703 is coupled to even sweep trace SE
iWith i+2 bar control line SC
i+2Between, and the grid of transistor M703 couples i+1 bar control line SC
i+1, all the other strange, even sweep traces and corresponding gated sweep line annexation can the rest may be inferred, be not repeated.
The scan mode of Fig. 7 can be with reference to Fig. 8, and Fig. 8 is the sweep signal oscillogram according to Fig. 7.Local circuit 700 in liquid crystal panel comprises control line SC
i, odd scan line SO
iAnd even sweep trace SE
iControl line SC
iAt its scan period T
sIn enable, at this moment, transistor M701 conducting, next control line SC
i+1At scan period T
sThe first half cycle T
S1In enable to open odd scan line SO
iThen next control line SC next,
i+2At scan period T
sLater half cycle T
S2Enable with turn-on transistor M703 to open even sweep trace SE
iSo, at scan period T
sIn can complete the writing pixel data to corresponding control line SC
i Strange pixel column 710 and dual pixel row 720 on pixel cell (as 711,712,721,722).On liquid crystal panel, the scan mode of all the other even sweep traces and odd scan line can be analogized, and repeats no more.
In other words, in the present embodiment, gate drivers only need drive all control lines and can all pixel cells be scanned (i.e. all odd scan line and the even sweep traces of corresponding scanning), and control line SC
iNumber half number of (comprising even sweep trace and odd scan line) of all sweep traces in liquid crystal panel is only arranged, can reduce thus driving the required gate drivers number of panel.In addition, it should be noted that the odd scan line described in above-described embodiment and even sweep trace are mainly to distinguish two adjacent sweep traces, the present invention is not limited with its title, and in another embodiment of the present invention, its placement position also can be exchanged.
Due to control line SC
iCan directly not go to the on-pixel unit, but with lower two control line SC
i+1, SC
i+2Cooperatively interact, enable corresponding odd scan line SO with indirect mode
iWith even sweep trace SE
iTherefore, control line SC
iOn sweep signal have two pulses 810,820, wherein pulse 810 is to coordinate front two control line SC
i-1, SC
i-2, and pulse 820 is only to open corresponding to control line SC
i Strange pixel column 710 and dual pixel row 720.
Due in the process that drives, strange pixel column 710 is identical with its circuit structure with the type of drive of dual pixel row 720, so the suffered feedthrough effect of its pixel cell (as 711 and 721) is consistent, namely control line SC
i, SC
i+1, SC
i+2On sweep signal identical with 721 impact on pixel cell 711.Strange pixel column 710 is subjected to scan mode with pixel cell on dual pixel row 720 and to affect the degree of its pixel voltage more consistent, so the quality of its picture disply is comparatively stable.And compared to known technology, the present embodiment only need use the sweep signal of half can drive all pixel columns, does not resemble known technology, and each pixel column all needs a sweep signal to drive.By technological means of the present invention, can reduce the fanout area area of the number, number of scanning lines and the panel that drive the required grid drive chip of panel.
In addition, it should be noted that transistor M701～M703 is the same with transistor M1, M2 in Fig. 1, all can be formed in fanout area 150.Certainly, if the layout areas of panel still has living space, also can according to deviser's demand, it be arranged at suitable zone.
Fig. 7 only illustrates the part of driving circuit, and remaining control line can be listed as corresponding to a strange pixel column and a dual pixel equally, and its structure and type of drive are as described in above-mentioned Fig. 7 and Fig. 8, those skilled in the art, via of the present invention open, should analogize easily, be not repeated at this.
In addition, it should be noted that the odd scan line SO described in above-described embodiment
iWith even sweep trace SE
iBe only the position relationship of describing between sweep trace, the present invention is not limited with it.If have N bar sweep trace in liquid crystal panel, odd scan line SO
iWith even sweep trace SE
iAlso can represent with i sweep trace and i+1 sweep trace respectively, wherein N, i are that positive integer and i are less than N.Those skilled in the art via disclosing of the present embodiment, should know the expression mode of all the other applicable scan line position by inference easily, do not repeat them here.
In sum, the present invention is according to the principle of feedthrough effect, proposes respectively with new increase electric capacity, changes the waveform of its sweep signal and directly adjust the mode such as its driving circuit and reduce sweep signal to the impact of different pixels row.By technological means of the present invention, can improve the problem of image quality inequality and reduce the potential change of sweep signal to the impact of pixel voltage.
Although the present invention discloses preferred embodiment as above; yet it is not to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the present invention; when can make various modifications and variations, so protection scope of the present invention should be as the criterion with the scope of appended claims.
Claims (15)
1. a liquid crystal panel, have a N bar sweep trace and N pixel column, and N is positive integer, and this liquid crystal panel comprises:
The i sweep trace, in order to scan the i pixel column, wherein i is that positive integer and i are less than or equal to N-3;
The i+1 sweep trace, in order to scan the i+1 pixel column, wherein said i pixel column is adjacent with described i+1 pixel column;
The i+3 sweep trace is in order to scan the i+3 pixel column;
The first transistor, the drain electrode of described the first transistor and source electrode are respectively coupled to described i sweep trace and described i+3 sweep trace, and the grid of described the first transistor is coupled to described i+1 sweep trace; And
The first electric capacity is coupled between described i sweep trace and common terminal;
Wherein, described i pixel column, described i+1 pixel column and described i+3 pixel column comprise respectively a plurality of pixel cells.
2. liquid crystal panel according to claim 1, wherein, described i sweep trace is odd scan line, described i+1 sweep trace is even sweep trace.
3. liquid crystal panel according to claim 2, wherein, described i sweep trace is even sweep trace, described i+1 sweep trace is odd scan line.
4. liquid crystal panel according to claim 1, wherein, described common terminal is earth terminal or common voltage end.
5. liquid crystal panel according to claim 1, wherein, described the first electric capacity comprises:
The first metal layer;
Insulation course is formed on described the first metal layer;
The second metal level is formed on described the first metal layer;
Passivating film is formed on described the second metal level;
Transparency electrode is formed on described passivating film; And
At least one through hole is in order to connect described the first metal layer and described transparency electrode.
6. liquid crystal panel according to claim 1, wherein, described i+1 sweep trace receives the first sweep signal, and described i+3 sweep trace receives the second sweep signal, and wherein in the front semiperiod of first period, described the first sweep signal enables; During the second, described the first sweep signal enables and described the second sweep signal enabled in the front semiperiod of the described second phase; In between the third phase, described the second sweep signal enables.
7. liquid crystal panel according to claim 6, wherein, described first period, the described second phase was before between the described third phase, and equal in length between described first, second and the third phase before the described second phase.
8. liquid crystal panel according to claim 1, wherein, described the first transistor is formed on fanout area.
9. liquid crystal panel according to claim 1, wherein, described the first transistor is thin film transistor (TFT).
10. a liquid crystal panel, have a N bar sweep trace and N pixel column, and N is positive integer, and described liquid crystal panel comprises:
The i sweep trace, in order to scan the i pixel column, wherein i is that positive integer and i are less than or equal to N-3;
The i+1 sweep trace, in order to scan the i+1 pixel column, wherein said i pixel column is adjacent with described i+1 pixel column;
The i+3 sweep trace is in order to scan the i+3 pixel column; And
The first transistor, the drain electrode of described the first transistor and source electrode are respectively coupled to described i sweep trace and described i+3 sweep trace, and the grid of described the first transistor is coupled to described i+1 sweep trace;
Wherein, described i+1 sweep trace receives the first sweep signal, and described i+3 sweep trace receives the second sweep signal, and in the front semiperiod of first period, described the first sweep signal enables; During the second, described the first sweep signal enables and described the second sweep signal enabled in the front semiperiod of the described second phase, and in the described second phase, the first enable voltage of described the first sweep signal is greater than the second enable voltage of described the second sweep signal.
11. liquid crystal panel according to claim 10, wherein, in between the third phase, described the second sweep signal enables, and described second enable voltage of described the second sweep signal between the described third phase equals described first enable voltage of described the first sweep signal in the described second phase.
12. liquid crystal panel according to claim 11, wherein, described first period, the described second phase was before between the described third phase, and equal in length between described first, second and the third phase before the described second phase.
13. liquid crystal panel according to claim 10, wherein, described i pixel column, described i+1 pixel column and described i+3 pixel column comprise respectively a plurality of pixel cells.
14. a liquid crystal panel has a N bar sweep trace and N pixel column, N is positive integer, and described liquid crystal panel comprises:
The first control line, corresponding to i sweep trace and i+1 sweep trace, wherein i is that positive integer and i are less than or equal to N-5;
The second control line is corresponding to i+2 sweep trace and i+3 sweep trace;
The 3rd control line is corresponding to i+4 sweep trace and i+5 sweep trace;
The first transistor, the drain electrode of described the first transistor and source electrode are respectively coupled to described i sweep trace and the second control line, and the grid of described the first transistor is coupled to described the first control line; And
Transistor seconds, the drain electrode of described transistor seconds and source electrode are respectively coupled to described i+1 sweep trace and described the first control line, and the grid of described transistor seconds is coupled to described the 3rd control line,
Wherein, described i sweep trace is adjacent with described i+1 sweep trace, and described i+2 sweep trace is adjacent with described i+3 sweep trace, and described i+4 sweep trace is adjacent with described i+5 sweep trace.
15. liquid crystal panel according to claim 14, wherein, in the scan period of described the first control line, described the first control line enables, and described the second control line enabled in the front semiperiod of described scan period, and described the 3rd control line enables the second half of described scan period is interim.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810174837 CN101738794B (en) | 2008-11-07 | 2008-11-07 | Liquid crystal panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810174837 CN101738794B (en) | 2008-11-07 | 2008-11-07 | Liquid crystal panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101738794A CN101738794A (en) | 2010-06-16 |
| CN101738794B true CN101738794B (en) | 2013-11-06 |
Family
ID=42462454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810174837 Expired - Fee Related CN101738794B (en) | 2008-11-07 | 2008-11-07 | Liquid crystal panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101738794B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102096256B (en) * | 2010-11-09 | 2012-06-27 | 华映视讯（吴江）有限公司 | Pixel array structure |
| KR101883922B1 (en) * | 2012-05-17 | 2018-08-01 | 엘지디스플레이 주식회사 | Organic light emitting diode display and its driving method |
| CN107845364B (en) * | 2016-09-19 | 2019-10-18 | 上海和辉光电有限公司 | Pixel compensation circuit and display device |
| US20210272530A1 (en) * | 2018-07-13 | 2021-09-02 | Sakai Display Products Corporation | Control device and liquid crystal display device |
| CN111435200A (en) * | 2019-01-11 | 2020-07-21 | 惠科股份有限公司 | Liquid crystal display device, liquid crystal display panel and driving method thereof |
| CN112820237B (en) * | 2019-10-31 | 2022-08-26 | 京东方科技集团股份有限公司 | Electronic substrate, driving method thereof and display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5287095A (en) * | 1988-12-09 | 1994-02-15 | Hitachi, Ltd. | Display device and its displaying method |
| CN1637488A (en) * | 2003-12-23 | 2005-07-13 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and driving method thereof |
| CN101261376A (en) * | 2007-03-09 | 2008-09-10 | 中华映管股份有限公司 | Display panel, display apparatus and drive method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6909415B2 (en) * | 2000-04-24 | 2005-06-21 | Matsushita Electric Industrial Co., Ltd. | Display unit and drive method therefor |
| US6897908B2 (en) * | 2001-11-23 | 2005-05-24 | Chi Mei Optoelectronics Corporation | Liquid crystal display panel having reduced flicker |
-
2008
- 2008-11-07 CN CN 200810174837 patent/CN101738794B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5287095A (en) * | 1988-12-09 | 1994-02-15 | Hitachi, Ltd. | Display device and its displaying method |
| CN1637488A (en) * | 2003-12-23 | 2005-07-13 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and driving method thereof |
| CN101261376A (en) * | 2007-03-09 | 2008-09-10 | 中华映管股份有限公司 | Display panel, display apparatus and drive method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101738794A (en) | 2010-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6845140B2 (en) | Method of driving a shift register, a shift register, a liquid crystal display device having the shift register | |
| US10102793B2 (en) | Built-in gate driver and display device using the same | |
| US10115366B2 (en) | Liquid crystal display device for improving the characteristics of gate drive voltage | |
| CN100476941C (en) | Method of driving a shift register, a shift register, a liquid crystal display device having the shift register | |
| US10276121B2 (en) | Gate driver with reduced number of thin film transistors and display device including the same | |
| CN100461253C (en) | LCD and its driving method | |
| US10210836B2 (en) | Gate driver and display device using the same | |
| KR100987589B1 (en) | Liquid crystal display device and its driving method | |
| US8242996B2 (en) | Display device with storage electrode driver to supply a boosting and sustaining voltage | |
| KR101769400B1 (en) | Device for driving gate and display device comprising the same | |
| CN107111981A (en) | Flexible display apparatus with plate inner grid circuit | |
| CN101738794B (en) | Liquid crystal panel | |
| KR20160087893A (en) | Gate driver circuit and driving method | |
| US9978330B2 (en) | Display driving method using overlapping scan mode with reduced coupling effect | |
| US8786584B2 (en) | Liquid crystal display device having output transistor having large capacitor component | |
| CN104036731A (en) | Pixel circuit and display device | |
| KR20190036461A (en) | Organic Light Emitting Diode display panel and Organic Light Emitting Diode display device using the same | |
| US6587089B1 (en) | LCD panel and LCD device equipped therewith | |
| TWI385454B (en) | Liquid crystal display panel | |
| CN101359109A (en) | Pixel, display panel and drive method thereof | |
| US11562707B2 (en) | Liquid crystal display device configured for speeding up gate drive of pixel transistors | |
| KR101980749B1 (en) | Display device | |
| KR20180003703A (en) | Display panel and display device using the same | |
| KR20200081185A (en) | Touch display device, driving circuit, and driving method | |
| CN101655626B (en) | Pixel structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| C53 | Correction of patent of invention or patent application | ||
| CB02 | Change of applicant information |
Address after: Miaoli County, Taiwan, China Applicant after: INNOLUX DISPLAY CORP. Address before: Miaoli County, Taiwan, China Applicant before: CHI MEI OPTOELECTRONICS CORP. |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: APPLICANT; FROM: QIMEI ELECTRONIC CO LTD TO: INNOLUX DISPLAY CORPORATION |
|
| GR01 | Patent grant | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20131010 Address after: Miaoli County, Taiwan, China Applicant after: CHI MEI OPTOELECTRONICS CORP. Address before: Tainan County, Taiwan, China Applicant before: CHI MEI OPTOELECTRONICS CORP. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131106 Termination date: 20181107 |