CN101729240B - Method and device for realizing time synchronization - Google Patents
Method and device for realizing time synchronization Download PDFInfo
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- CN101729240B CN101729240B CN200910237498A CN200910237498A CN101729240B CN 101729240 B CN101729240 B CN 101729240B CN 200910237498 A CN200910237498 A CN 200910237498A CN 200910237498 A CN200910237498 A CN 200910237498A CN 101729240 B CN101729240 B CN 101729240B
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Abstract
The invention discloses a method and a device for realizing time synchronization. Both a timestamp counter and a reference timestamp counter perform synchronous counting, so the difference between an external synchronous clock frequency and a clock frequency generated by a local FPGA can be reduced smoothly, which avoids a phenomenon of a reverse order of a timestamp field. Moreover, because an enabling bit for setting a timestamp forcibly is set, if the enabling bit is 1, a set initial timestamp value is loaded to the timestamp counter and the reference timestamp counter simultaneously and immediately; if the enabling bit is not 1, the set initial timestamp value is loaded to the reference timestamp counter immediately; and the timestamp counter slowly adjusts a frequency in accordance with that of the reference timestamp counter according to an adjustment mechanism so that the adjustment of the timestamp is more smooth. Under the assurance of a handshake mechanism, the time error of a system is ensured in a required precision range so as to improve the precision of the system.
Description
Technical field
The present invention relates to the Time synchronization technique field, particularly a kind of method and apparatus of realizing time synchronized.
Background technology
In data collecting field, need the data that integrated circuit board collects be added upward sending to upper layer software (applications) behind the time stamp, with the time-delay of calculated data in network.A kind of method commonly used is to adopt field programmable gate array (FPGA, Field-Programmable Gate Array) to produce time stamp at present.
Referring to Fig. 1, it is the existing handling process sketch map of beating timestamp for data flow.Have in FPGA inside second counter and nanosecond counter, the two constitutes time stamp counter.Current time value is got in driving from upper system, this value is set in the FPGA initial registers again, and FPGA begins counting with the counting initial value that this value is loaded on two counters as counter.For example, driving is taken out from upper system and was write FGPA initial registers position second as initial value 00 o'clock on the 1st January in 1970.When nanosecond, rolling counters forward reached second, the nanosecond counter O reset was with second of time counter set.Behind the packet that integrated circuit board collects, add the time stamp territory that above-mentioned two counters produce in real time, deliver to upper system afterwards and do further processing in the packet header of packet.Whole system has the principal and subordinate to be provided with under the situation of many integrated circuit boards: the second counter of main card leans on nanosecond counter carry pulse second counting, leans on carry pulse counting second of main card from counter second of card, to reach the synchronous purpose of time stamp between many integrated circuit boards.
In the prior art; System time often needs and network time carries out synchronously; And this synchronizing process must cause the FPGA initial registers need frequently be set, and when between system time and the inner time stamp counter of FPGA when variant, causes phenomenon (the normal packet receiving of time stamp territory, the packet header inverted sequence that collects packet through regular meeting; The bag time stamp territory of receiving earlier as time goes by is little, after the bag time stamp territory of receiving big; Inverted sequence is meant that the bag time stamp territory of receiving earlier is big, after the bag time stamp territory of receiving little).
In addition; The time precision of upper system setting has only a second level; Driving exists when getting system time seizes CPU, CPU time sheet wheel commentaries on classics and direct memory access (DMA) (DMA under the multi-process; DirectMemory Access) time-delay that brings of Interrupt Process, because the existence of time-delay, it is bigger to cause the time stamp initial value that time error is set.Under the situation of many integrated circuit boards, if get the situation that system time is striden second, can cause the mistake that time stamp time interval between principal and subordinate's card differed from 1 second all the time.
Summary of the invention
The embodiment of the invention is to provide a kind of method and apparatus of realizing time synchronized, to solve the problem of time stamp territory inverted sequence in the prior art, improves the time precision that initial value is provided with simultaneously.
The embodiment of the invention provides a kind of method that realizes time synchronized, comprising:
The time stamp counter is set and with reference to the time stamp counter in FPGA, when normally moving, said with reference to the time stamp counter according to first preset clock cycle carry at the uniform velocity; Said method also comprises:
Calculate said time stamp counter and said in real time with reference to the direct difference of time stamp counter;
If it is interval that said difference exceeds preset difference; And the current time stamp Counter Value of said time stamp counter smaller or equal to said with reference to the current reference time stamp Counter Value of time stamp counter; Then control said time stamp counter according to second preset clock cycle carry at the uniform velocity; Up to said time stamp counter and said with reference to the direct difference of time stamp counter in preset difference interval the time, control said time stamp counter according to first preset clock cycle carry at the uniform velocity; The said second preset clock cycle is greater than the first preset clock cycle;
If it is interval that said difference exceeds preset difference; And the current time stamp Counter Value of said time stamp counter greater than said with reference to the current reference time stamp Counter Value of time stamp counter; Then control said time stamp counter according to the 3rd preset clock cycle carry at the uniform velocity; Up to said time stamp counter and said with reference to the direct difference of time stamp counter in preset difference interval the time, control said time stamp counter according to first preset clock cycle carry at the uniform velocity; The said the 3rd preset clock cycle is less than the first preset clock cycle.
Wherein, said method also comprises: the enable register control bit is set on FPGA;
When initial setting up, said enable register control bit is set to " enabled ", and driving will be arranged on the time stamp counter and simultaneously with reference on the time stamp counter from the time initial value that upper system is obtained;
When non-initial setting up, said enable register control bit is set to " disable state ", drives to be arranged on reference on the time stamp counter from the time initial value that upper system is obtained.
Wherein, said method also comprises: the status register control bit is set on FPGA;
Judge to be used to represent whether the synchronous ring of integrated circuit board synchronous regime connects,, then said status register is placed the state that connects if connect, otherwise, said status register is placed disconnected good state.
Wherein,, judge whether the integrated circuit board synchronous ring connects, connect if receive then through detecting whether receive a second carry pulse, otherwise, do not connect.
Wherein, said method also comprises:
When normally moving, driving was worth in the T1 moment from the current time of taking out the time stamp counter, was worth in the current time of the T2 moment from upper system taking-up upper system, sent the said T1 moment and T2 pairing time value of the moment to FPGA constantly at T3; Said T1＜T2＜T3;
Whether FPGA judges T3 and T1 difference constantly smaller or equal to preset precision threshold, if, then T2 moment time corresponding value is written among the FPGA, otherwise, error message returned.
Wherein, said method also comprises:
When having a plurality of integrated circuit board; When loading FPGA, all integrated circuit boards all are set to main card, afterwards; Earlier of being provided with in a plurality of integrated circuit boards of the master-slave register through FPGA is main card; All the other are from card, and then will be set to the FPGA from the time that upper system is got, and the time that main card is set from the time of card again is set earlier.
The embodiment of the invention also provides a kind of device of realizing time synchronized, comprising:
FPGA is provided with the time stamp counter and with reference to the time stamp counter in the said FPGA, when normally moving, said with reference to the time stamp counter according to first preset clock cycle carry at the uniform velocity;
Difference calculating module is used for calculating in real time said time stamp counter and said with reference to the direct difference of time stamp counter;
The analysis and Control module; It is interval to be used for exceeding preset difference in said difference; And the current time stamp Counter Value of said time stamp counter is smaller or equal to said during with reference to the current reference time stamp Counter Value of time stamp counter; Control said time stamp counter according to second preset clock cycle carry at the uniform velocity, up to said time stamp counter with said with reference to the direct difference of time stamp counter in preset difference interval the time, control said time stamp counter and preset clock cycle carry at the uniform velocity according to first; The said second preset clock cycle is greater than the first preset clock cycle; It is interval to be used for exceeding preset difference in said difference; And the current time stamp Counter Value of said time stamp counter is greater than said during with reference to the current reference time stamp Counter Value of time stamp counter; Control said time stamp counter according to the 3rd preset clock cycle carry at the uniform velocity; Up to said time stamp counter and said with reference to the direct difference of time stamp counter in preset difference interval the time, control said time stamp counter according to first preset clock cycle carry at the uniform velocity; The said the 3rd preset clock cycle is less than the first preset clock cycle.
Wherein, said device also comprises:
Initial value is provided with control module, is used for when initial setting up, and the enable register on the FPGA is set to " enabled ", will be arranged on the time stamp counter simultaneously from the time initial value that upper system is obtained and with reference on the time stamp counter; When non-initial setting up, the enable register on the FPGA is set to " disable state ", will be arranged on from the time initial value that upper system is obtained with reference on the time stamp counter.
Wherein, said device also comprises:
Whether the synchronous regime detection module is used to detect the synchronous ring of representing the integrated circuit board synchronous regime and connects, if connect, then status register is placed the state that connects, otherwise, said status register is placed disconnected good state.
Wherein, said device also comprises:
The protection module of shaking hands; Be used for when normal operation; Be worth in the T1 moment from the current time of taking out the time stamp counter, be worth, send the said T1 moment and T2 pairing time value of the moment to FPGA constantly at T3 in the T2 moment from the current time that upper system takes out upper system; Said T1＜T2＜T3; When FPGA judges T3 and T1 difference constantly whether during smaller or equal to preset precision threshold, with T2 constantly the time corresponding value be written among the FPGA, when FPGA judges T3 and T1 difference constantly whether during greater than the precision threshold preset, return error message.
The method and apparatus of the realization time synchronized that the application embodiment of the invention provides; Because the time stamp counter and with reference to two counters of time stamp counter all in synchronous counting; Do like this can be level and smooth the clock frequency that produces of minimizing external sync clock frequency and local FPGA between difference, guaranteed can not occur the phenomenon of time stamp territory inverted order.Have again; Force to be provided with the time stamp enable bit owing to be provided with, as when this position is 1, the time stamp initial value while of setting is loaded into the time stamp counter and at once with reference in the time stamp counter; Otherwise; The time stamp initial value that is provided with is loaded into reference to the time stamp counter at once, the time stamp counter then according to above-mentioned adjustment mechanism slowly with frequency adjust to consistent with reference to the time stamp counter till, make that the adjustment of time stamp is more level and smooth.Under the assurance of handshake mechanism, guaranteed the system time error in desired accuracy rating, thereby made system accuracy be improved.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention and technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment and the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the existing handling process sketch map of beating timestamp for data flow;
Fig. 2 plays the handling process sketch map of timestamp according to the embodiment of the invention for data flow;
Fig. 3 is the method flow diagram according to the realization time synchronized of the embodiment of the invention;
Fig. 4 is the protection mechanism realization sketch map of shaking hands according to the embodiment of the invention;
Fig. 5 is the apparatus structure sketch map according to the realization time synchronized of the embodiment of the invention.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
In the embodiment of the invention method and apparatus of related realization time synchronized actual be to guarantee the synchronous method and apparatus of timestamp.
In order to realize the present invention, at first need do some and be provided with, concrete is provided with explanation as follows:
The time stamp counter is set and with reference to the time stamp counter in FPGA, when normally moving, said with reference to the time stamp counter according to first preset clock cycle carry at the uniform velocity.
Driving is provided with as follows interface between the upper system:
A. increase by one lock in time initial value function is set, by upper procedure fixed time initial value and master slave relation. the time initial value that guarantees all cards is identical;
B., initial value is set is in proper order: all times from card are set earlier, the time of main card is set at last;
C. during operate as normal,, get current time value from upper system by driving if do the time synchronized operation;
D. increase a definite integrated circuit board and whether support the driving interface of synchronization mechanism;
E. increase a driving interface of judging that synchronous ring is whether in proper working order, wherein, detect the synchronous regime that synchronous ring promptly representes to detect integrated circuit board.Concrete, judge through whether receiving a second carry pulse whether synchronous ring connects, if connect, show that then synchronous ring is in proper working order, can guarantee simultaneous operation, if do not connect, show that then synchronous ring is unusual, can not guarantee simultaneous operation.
The function of above-mentioned setting can use three interface functions to realize:
The function of time (SetTime ()) is set, is used to be provided with the master slave relation of time initial value and a plurality of integrated circuit boards, all are supported that synchronous integrated circuit board is provided with by upper system, identical with assurance time initial value, and guarantee to be provided with from card earlier, main card is set at last;
Wheel synchronization type function (GetSyncType ()) is set, and this function is used for like the state of synchronous register, obtaining integrated circuit board and whether supporting synchronous information, and return to show whether support synchronous state value to caller through obtaining the state of appointment register.
Detect synchronous regime function (CheckSyncStatus ()), be used to check the synchronous regime of integrated circuit board, promptly check whether operate as normal of synchronous ring, concrete, can support synchronous integrated circuit board all to call one time to all, if all successes explain that then synchronous ring is in proper working order.
Driving is provided with as follows the interface of FPGA:
A. increase the enable register control bit, when this control bit representes to enable (enable), allow directly to be provided with the time of integrated circuit board; Come into force; Promptly when this control bit is represented enable, the time stamp counter can be set and with reference to the time value of time stamp counter, and come into force; When this control bit was represented disable (disable), the time of setting reached the time value of setting over time, promptly when this control bit is represented disable, the time value with reference to the time stamp counter can only be set, and the time value of time stamp counter can not be set;
B. increase a status register control bit,, judge whether synchronous ring connects through judging whether to receive a second carry pulse.
Below in conjunction with accompanying drawing the embodiment of the invention is elaborated again.
Referring to Fig. 2, its be according to the embodiment of the invention play the handling process sketch map of timestamp for data flow, referring to Fig. 3, it is the method flow diagram according to the realization time synchronized of the embodiment of the invention.In conjunction with Fig. 2 and Fig. 3, specifically comprise: the time stamp counter is set and with reference to the time stamp counter in FPGA, when normally moving, said with reference to the time stamp counter according to first preset clock cycle carry at the uniform velocity; Said method also comprises:
Step 301 is calculated said time stamp counter and said with reference to the direct difference of time stamp counter in real time;
For example, two counters are set in FPGA: one " time stamp counter ", do the nanosecond and a second counting of beating time stamp; " with reference to the time stamp counter ", the nanosecond and a second counting of doing reference.The nanosecond of " with reference to the time stamp counter " is all the time according to 1 clock cycle 20ns carry at the uniform velocity; And the nanosecond of " time stamp counter " is according to the certain rule carry.
" time stamp counter " and " with reference to the time stamp counter " always real-time calculated difference have two kinds of situation:
(1) time stamp Counter Value＜=with reference to the time stamp Counter Value; The clock frequency of representing the local FPGA generation of external sync clock frequency ratio this moment is fast; This moment, the time stamp counter was according to the speed carry of 1 clock cycle 40ns, up to time stamp counter and the difference of calculating in real time with reference to the time stamp counter near 0 o'clock, as-5ns to+this interval of 5ns constantly; Return to speed carry, reach synchronous purpose according to 1 clock cycle 20ns;
(2) time stamp Counter Value＞with reference to the time stamp Counter Value; The clock frequency of representing the local FPGA generation of external sync clock frequency ratio this moment is slow, and for fear of beating the inverted sequence mistake that time stamp occurs, the time stamp counter is according to the speed carry of 1 clock cycle 10ns; Up to time stamp counter and the difference of calculating in real time with reference to the time stamp counter near 0 o'clock; As-5ns to+5ns this when interval, return to speed carry according to 1 clock cycle 20ns, reach synchronous purpose.
Because the time stamp counter and with reference to two counters of time stamp counter all in synchronous counting; Do like this can be level and smooth the clock frequency that produces of minimizing external sync clock frequency and local FPGA between difference, but also guaranteed can not occur the phenomenon of time stamp territory inverted order.
Need to prove, for embodiment illustrated in fig. 3, can also comprise: the enable register control bit is set on FPGA; When initial setting up, said enable register control bit is set to " enabled ", as is set to 1, and driving will be arranged on the time stamp counter and simultaneously with reference on the time stamp counter from the time initial value that upper system is obtained; When non-initial setting up, said enable register control bit is set to " disable state ", as is set to 0, and drive and can only be arranged on reference on the time stamp counter from the time initial value that upper system is obtained this moment.
Force to be provided with the time stamp enable bit owing to be provided with; As when this position is 1; The time stamp initial value that is provided with is loaded into the time stamp counter and simultaneously at once with reference in the time stamp counter; Otherwise the time stamp initial value of setting is loaded into reference to the time stamp counter at once, the time stamp counter then according to above-mentioned adjustment mechanism slowly with frequency adjust to consistent with reference to the time stamp counter till.Like this, make that the adjustment of time stamp is more level and smooth.
Need to prove, for embodiment illustrated in fig. 3, can also comprise: the status register control bit is set on FPGA; Whether receive second carry pulse through detection and judge to be used to represent whether the synchronous ring of integrated circuit board synchronous regime connects,, then said status register is placed the state that connects if connect, otherwise, said status register is placed disconnected good state.Like this, can better guarantee synchronous stability, avoid owing to connectivity problem cause asynchronous.
Need to prove, for embodiment illustrated in fig. 3, can also comprise the protection mechanism of shaking hands, referring to Fig. 4, it is the protection mechanism realization sketch map of shaking hands according to the embodiment of the invention, and this mechanism specifically comprises:
When normally moving, driving was worth in the T1 moment from the current time of taking out the time stamp counter, was worth in the current time of the T2 moment from upper system taking-up upper system, sent the said T1 moment and T2 pairing time value of the moment to FPGA constantly at T3; Said T1＜T2＜T3;
Whether FPGA judges T3 and T1 difference constantly smaller or equal to preset precision threshold, if, then T2 moment time corresponding value is written among the FPGA, otherwise, error message returned.
For example, time-delay is set less than 1ms for what make system time, the protection mechanism of shaking hands that is adopted comprises: drive before getting upper system time T 2, take out the time stamp counter earlier in T1 value constantly, then with T1, the value of T2 writes the FPGA register.FPGA side time stamp counter receives T1 constantly at T3, after the value of T2, and the difference of T3 and T1 relatively at once, when their difference during less than 1ms, the T2 value is effective initial value, and it is set to reference in the time stamp counter; Otherwise explain that the time-delay of T2 value is excessive, FPGA returns failure signal is set, and abandons this initial value setting, initiates initial value once more by driving side action is set, till success.Like this, guaranteed the system time error in desired accuracy rating, thereby made system accuracy be improved.
Need to prove, for above-mentioned all embodiment, when having a plurality of integrated circuit board; When loading FPGA, all integrated circuit boards all are set to main card, afterwards; Earlier of being provided with in a plurality of integrated circuit boards of the master-slave register through FPGA is main card; All the other are from card, and then will be set to the FPGA from the time that upper system is got, and the time that main card is set from the time of card again is set earlier.
The embodiment of the invention also provides a kind of device of realizing time synchronized, referring to Fig. 5, specifically comprises:
FPGA501 is provided with the time stamp counter and with reference to the time stamp counter in the said FPGA, when normally moving, said with reference to the time stamp counter according to first preset clock cycle carry at the uniform velocity;
Analysis and Control module 503; It is interval to be used for exceeding preset difference in said difference; And the current time stamp Counter Value of said time stamp counter is smaller or equal to said during with reference to the current reference time stamp Counter Value of time stamp counter; Control said time stamp counter according to second preset clock cycle carry at the uniform velocity, up to said time stamp counter with said with reference to the direct difference of time stamp counter in preset difference interval the time, control said time stamp counter and preset clock cycle carry at the uniform velocity according to first; The said second preset clock cycle is greater than the first preset clock cycle; It is interval to be used for exceeding preset difference in said difference; And the current time stamp Counter Value of said time stamp counter is greater than said during with reference to the current reference time stamp Counter Value of time stamp counter; Control said time stamp counter according to the 3rd preset clock cycle carry at the uniform velocity; Up to said time stamp counter and said with reference to the direct difference of time stamp counter in preset difference interval the time, control said time stamp counter according to first preset clock cycle carry at the uniform velocity; The said the 3rd preset clock cycle is less than the first preset clock cycle.
Said apparatus can also comprise:
Initial value is provided with control module 504, is used for when initial setting up, and the enable register on the FPGA is set to " enabled ", will be arranged on the time stamp counter simultaneously from the time initial value that upper system is obtained and with reference on the time stamp counter; When non-initial setting up, the enable register on the FPGA is set to " disable state ", will be arranged on from the time initial value that upper system is obtained with reference on the time stamp counter.
Said apparatus can also comprise:
Whether synchronous regime detection module 505 is used to detect the synchronous ring of representing the integrated circuit board synchronous regime and connects, if connect, then status register is placed the state that connects, otherwise, said status register is placed disconnected good state.
Said apparatus can also comprise:
The protection module 506 of shaking hands; Be used for when normal operation; Be worth in the T1 moment from the current time of taking out the time stamp counter, be worth, send the said T1 moment and T2 pairing time value of the moment to FPGA constantly at T3 in the T2 moment from the current time that upper system takes out upper system; Said T1＜T2＜T3; When FPGA judges T3 and T1 difference constantly whether during smaller or equal to preset precision threshold, with T2 constantly the time corresponding value be written among the FPGA, when FPGA judges T3 and T1 difference constantly whether during greater than the precision threshold preset, return error message.
The device of the realization time synchronized that the application embodiment of the invention provides; Because the time stamp counter and with reference to two counters of time stamp counter all in synchronous counting; Do like this can be level and smooth the clock frequency that produces of minimizing external sync clock frequency and local FPGA between difference, guaranteed can not occur the phenomenon of time stamp territory inverted order.Have again; Force to be provided with the time stamp enable bit owing to be provided with, as when this position is 1, the time stamp initial value while of setting is loaded into the time stamp counter and at once with reference in the time stamp counter; Otherwise; The time stamp initial value that is provided with is loaded into reference to the time stamp counter at once, the time stamp counter then according to above-mentioned adjustment mechanism slowly with frequency adjust to consistent with reference to the time stamp counter till, make that the adjustment of time stamp is more level and smooth.Under the assurance of handshake mechanism, guaranteed the system time error in desired accuracy rating, thereby made system accuracy be improved.
For device embodiment, because it is basically similar in appearance to method embodiment, so description is fairly simple, relevant part gets final product referring to the part explanation of method embodiment.
Need to prove; In this article; Relational terms such as first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint relation or the order that has any this reality between these entities or the operation.And; Term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability; Thereby make and comprise that process, method, article or the equipment of a series of key elements not only comprise those key elements; But also comprise other key elements of clearly not listing, or also be included as this process, method, article or equipment intrinsic key element.Under the situation that do not having much more more restrictions, the key element that limits by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises said key element and also have other identical element.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All any modifications of within spirit of the present invention and principle, being done, be equal to replacement, improvement etc., all be included in protection scope of the present invention.
Claims (10)
1. a method that realizes time synchronized is characterized in that, comprising:
The time stamp counter is set and with reference to the time stamp counter in FPGA, when normally moving, said with reference to the time stamp counter according to the speed of 1 clock cycle first step-length carry at the uniform velocity; Said method also comprises:
Calculate said time stamp counter and said in real time with reference to the direct difference of time stamp counter;
If it is interval that said difference exceeds preset difference; And the current time stamp Counter Value of said time stamp counter smaller or equal to said with reference to the current reference time stamp Counter Value of time stamp counter; Then control said time stamp counter according to the speed of 1 clock cycle second step-length carry at the uniform velocity; Up to said time stamp counter and said with reference to the direct difference of time stamp counter in preset difference interval the time, control said time stamp counter according to the speed of 1 clock cycle first step-length carry at the uniform velocity; The speed of said 1 clock cycle second step-length is greater than the speed of 1 clock cycle first step-length;
If it is interval that said difference exceeds preset difference; And the current time stamp Counter Value of said time stamp counter greater than said with reference to the current reference time stamp Counter Value of time stamp counter; Then control said time stamp counter according to the speed of 1 clock cycle the 3rd step-length carry at the uniform velocity; Up to said time stamp counter and said with reference to the direct difference of time stamp counter in preset difference interval the time, control said time stamp counter according to the speed of 1 clock cycle first step-length carry at the uniform velocity; The speed of said 1 clock cycle the 3rd step-length is less than the speed of 1 clock cycle first step-length.
2. method according to claim 1 is characterized in that, said method also comprises: the enable register control bit is set on FPGA;
When initial setting up, said enable register control bit is set to " enabled ", and driving will be arranged on the time stamp counter and simultaneously with reference on the time stamp counter from the time initial value that upper system is obtained;
When non-initial setting up, said enable register control bit is set to " disable state ", drives to be arranged on reference on the time stamp counter from the time initial value that upper system is obtained.
3. method according to claim 1 is characterized in that, said method also comprises: the status register control bit is set on FPGA;
Judge to be used to represent whether the synchronous ring of integrated circuit board synchronous regime connects,, then said status register is placed the state that connects if connect, otherwise, said status register is placed disconnected good state.
4. method according to claim 3 is characterized in that, through detecting whether receive a second carry pulse, judges whether the integrated circuit board synchronous ring connects, connect if receive then, otherwise, do not connect.
5. according to claim 1,2 or 3 described methods, it is characterized in that said method also comprises:
When normally moving, driving was worth in the T1 moment from the current time of taking out the time stamp counter, was worth in the current time of the T2 moment from upper system taking-up upper system, sent the said T1 moment and T2 pairing time value of the moment to FPGA constantly at T3; Said T1＜T2＜T3;
Whether FPGA judges T3 and T1 difference constantly smaller or equal to preset precision threshold, if, then T2 moment time corresponding value is written in the reference time stamp counter of FPGA, otherwise, error message returned.
6. method according to claim 5 is characterized in that, said method also comprises:
When having a plurality of integrated circuit board; When loading FPGA, all integrated circuit boards all are set to main card, afterwards; Earlier of being provided with in a plurality of integrated circuit boards of the master-slave register through FPGA is main card; All the other are from card, and then will be set to the FPGA from the time that upper system is got, and the time that main card is set from the time of card again is set earlier.
7. a device of realizing time synchronized is characterized in that, comprising:
FPGA is provided with the time stamp counter and with reference to the time stamp counter in the said FPGA, when normally moving, said with reference to the time stamp counter according to the speed of 1 clock cycle first step-length carry at the uniform velocity;
Difference calculating module is used for calculating in real time said time stamp counter and said with reference to the direct difference of time stamp counter;
The analysis and Control module; It is interval to be used for exceeding preset difference in said difference; And the current time stamp Counter Value of said time stamp counter is smaller or equal to said during with reference to the current reference time stamp Counter Value of time stamp counter; Control said time stamp counter according to the speed of 1 clock cycle second step-length carry at the uniform velocity; Up to said time stamp counter and said with reference to the direct difference of time stamp counter in preset difference interval the time, control said time stamp counter according to the speed of 1 clock cycle first step-length carry at the uniform velocity; The speed of said 1 clock cycle second step-length is greater than the speed of 1 clock cycle first step-length; It is interval to be used for exceeding preset difference in said difference; And the current time stamp Counter Value of said time stamp counter is greater than said during with reference to the current reference time stamp Counter Value of time stamp counter; Control said time stamp counter according to the speed of 1 clock cycle the 3rd step-length carry at the uniform velocity; Up to said time stamp counter and said with reference to the direct difference of time stamp counter in preset difference interval the time, control said time stamp counter according to the speed of 1 clock cycle first step-length carry at the uniform velocity; The speed of said 1 clock cycle the 3rd step-length is less than the speed of 1 clock cycle first step-length.
8. device according to claim 7 is characterized in that, said device also comprises:
Initial value is provided with control module, is used for when initial setting up, and the enable register on the FPGA is set to " enabled ", will be arranged on the time stamp counter simultaneously from the time initial value that upper system is obtained and with reference on the time stamp counter; When non-initial setting up, the enable register on the FPGA is set to " disable state ", will be arranged on from the time initial value that upper system is obtained with reference on the time stamp counter.
9. device according to claim 7 is characterized in that, said device also comprises:
Whether the synchronous regime detection module is used to detect the synchronous ring of representing the integrated circuit board synchronous regime and connects, if connect, then status register is placed the state that connects, otherwise, said status register is placed disconnected good state.
10. according to claim 7,8 or 9 described devices, it is characterized in that said device also comprises:
The protection module of shaking hands; Be used for when normal operation; Be worth in the T1 moment from the current time of taking out the time stamp counter, be worth, send the said T1 moment and T2 pairing time value of the moment to FPGA constantly at T3 in the T2 moment from the current time that upper system takes out upper system; Said T1＜T2＜T3; When FPGA judges T3 and T1 difference constantly smaller or equal to preset precision threshold; T2 moment time corresponding value is written in the reference time stamp counter of FPGA; When FPGA judges T3 and T1 difference constantly greater than preset precision threshold, return error message.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN102868515B (en) * | 2012-09-27 | 2015-04-29 | 烽火通信科技股份有限公司 | System time synchronization device and method in packet transport network |
| CN111008239B (en) * | 2018-10-07 | 2023-03-24 | 上海希路智能科技有限公司 | Data synchronization method and system of asynchronous system and terminal equipment |
| CN111158867B (en) * | 2018-11-07 | 2023-05-16 | 阿里巴巴集团控股有限公司 | Time synchronization processing method, thread scheduling method, device and electronic equipment |
| CN111366834B (en) * | 2020-01-15 | 2021-09-14 | 海光信息技术股份有限公司 | Signal delay control method and device and test system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1306358A (en) * | 2000-01-20 | 2001-08-01 | 华为技术有限公司 | Method and device for transmitting and receiving data via data bus |
| CN1937574A (en) * | 2005-09-19 | 2007-03-28 | 北京大学 | Network flow classifying, state tracking and message processing device and method |
| CN1960242A (en) * | 2006-10-17 | 2007-05-09 | 中控科技集团有限公司 | Method, device, system for implementing clock synchronization, and distribution system |
| CN101272501A (en) * | 2008-05-07 | 2008-09-24 | 北京数码视讯科技股份有限公司 | Video/audio encoding and decoding method and device |
| CN101336520A (en) * | 2006-12-31 | 2008-12-31 | 中兴通讯股份有限公司 | Method for measuring relative time delay of data service in optical transmission network |
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| KR20020052490A (en) * | 2000-12-26 | 2002-07-04 | 엘지전자 주식회사 | Au3 signal creation apparatus of tiu |
| KR100424850B1 (en) * | 2001-08-08 | 2004-03-27 | 엘지전자 주식회사 | System of Transferring Data Transmission Velocity |
| KR100996421B1 (en) * | 2007-03-15 | 2010-11-24 | 삼성전자주식회사 | Apparatus and method for synchronizing channel card in wireless communication system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1306358A (en) * | 2000-01-20 | 2001-08-01 | 华为技术有限公司 | Method and device for transmitting and receiving data via data bus |
| CN1937574A (en) * | 2005-09-19 | 2007-03-28 | 北京大学 | Network flow classifying, state tracking and message processing device and method |
| CN1960242A (en) * | 2006-10-17 | 2007-05-09 | 中控科技集团有限公司 | Method, device, system for implementing clock synchronization, and distribution system |
| CN101336520A (en) * | 2006-12-31 | 2008-12-31 | 中兴通讯股份有限公司 | Method for measuring relative time delay of data service in optical transmission network |
| CN101272501A (en) * | 2008-05-07 | 2008-09-24 | 北京数码视讯科技股份有限公司 | Video/audio encoding and decoding method and device |
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