CN101727800B - Semiconductor grid drive circuit and drive method thereof - Google Patents
Semiconductor grid drive circuit and drive method thereof Download PDFInfo
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- CN101727800B CN101727800B CN2008101667996A CN200810166799A CN101727800B CN 101727800 B CN101727800 B CN 101727800B CN 2008101667996 A CN2008101667996 A CN 2008101667996A CN 200810166799 A CN200810166799 A CN 200810166799A CN 101727800 B CN101727800 B CN 101727800B
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Abstract
The invention discloses a semiconductor grid drive circuit which receives a plurality of frequency signals and comprises a plurality of drive units which are connected in series, wherein each drive unit is used for driving a load and comprises an input end, an output end, a first switch and a second switch; the first switch is provided with a first end coupled with the input end, a second end coupled with a first node and a control end for receiving the first frequency signal and is switched on when the first frequency signal is in a high potential; the second switch is provided with a first end for receiving the second frequency signal, a second end coupled with the output end and a control end coupled with the first node; when the first node is in a high potential, the second frequency signal charges and discharges the load by the second switch; and the output end of each drive unit is coupled to the input end of the next stage drive unit.
Description
Technical field
The present invention relates to a kind of gate driver circuit, particularly relate to a kind of semiconductor grid drive circuit that is used for LCD.
Background technology
For image quality that LCD is shown is more clear, the resolution of LCD is raised apace, and therefore the number of required driving circuit increases, and causes manufacturing cost also to improve simultaneously.Please, can be made in same substrate simultaneously through gate driver circuit and picture element matrix 91 in the prior art, be referred to as semiconductor grid drive circuit 92 ', reduce cost of manufacture thus LCD 9 ' with reference to shown in the 1b figure.Yet owing to be formed with numerous gate line, data line and pixel cell simultaneously on a substrate, the space that can supply to form gate driver circuit is limited, so the structure of this semiconductor grid drive circuit 92 ' must simplify as far as possible, to boost productivity.
A kind of semiconductor grid drive circuit of prior art; Like United States Patent (USP) the 5th; 222; 082 disclosed " being used as the shift register (Shift register useful as aselect line scanner for liquid crystal display) of the selection wire scanner of LCD ", it comprises a plurality of driving stages that are connected in series.Each driving stage comprises input end, output terminal and output circuit, and this output circuit is used so that the voltage of this output terminal switches between noble potential and electronegative potential.First node switches this output terminal according to input signal, and Section Point remains electronegative potential with this output terminal between this incoming frequency and a frequency.Yet,, have complicated structure and need bigger making space because each driving stage of this shift register still includes six thin film transistor (TFT)s.
Therefore, the present invention provides a kind of semiconductor grid drive circuit, and it can significantly reduce circuit structure complexity, minimizing making space and reduce cost.
Summary of the invention
One object of the present invention is to provide a kind of semiconductor grid drive circuit, and wherein each driver element only needs two switch modules, thereby has better simply circuit structure, lower cost of manufacture and less circuit space.
Another object of the present invention is to provide a kind of semiconductor grid drive circuit, wherein discharging and recharging through same switch module of each driver element output voltage carried out, and can eliminate the problem of switch module critical voltage skew.
A purpose more of the present invention is to provide a kind of semiconductor grid drive circuit, and wherein each driver element can be combined with mu balanced circuit in addition, to stablize the output voltage of this semiconductor grid drive circuit.
In order to achieve the above object, the present invention provides a kind of semiconductor grid drive circuit, and it receives a plurality of frequency signals and comprises a plurality of driver elements that are connected in series.Each driver element is used to drive load and comprises signal input part, output terminal, first switch and second switch.This first switch has first end that couples this signal input part, second end that couples a first node and receives the control end of first frequency signal, and this first switch is connected during for noble potential at said first frequency signal.This second switch has first end that receives the second frequency signal, couple second end of this output terminal and couple the control end of this first node; Wherein when this first node was noble potential, this second frequency signal charged to this load through this second switch and discharges; Wherein the output terminal of each driver element is coupled to the signal input part of next stage driver element.
Semiconductor grid drive circuit of the present invention can comprise the electric capacity between second end of second end that is coupled to this first switch and this second switch in addition and be coupled to second end of this second switch and the mu balanced circuit between this output terminal.
According to another characteristics of the present invention, the present invention also provides a kind of gate driver circuit, and it has signal input part and output terminal and is made up of first switch and second switch.This first switch has first end that couples this signal input part, second end that couples a node and receives the control end of first frequency signal, and this first switch is connected during for noble potential at said first frequency signal.This second switch has first end that receives the second frequency signal, couple second end of this output terminal and couple the control end of this node, and wherein this second switch is connected during for noble potential at said node, so that this second frequency signal is coupled to this output terminal.
According to another characteristics of the present invention, the present invention also provides a kind of gate driver circuit that is used to drive load.This gate driver circuit comprises signal input part, output terminal, first switch and second switch.This first switch has first end that couples this signal input part, second end that couples a node and receives the control end of first frequency signal, and this first switch is connected during for noble potential at said first frequency signal.This second switch has first end that receives the second frequency signal, couple second end of this output terminal and couple the control end of this node, and wherein when this node was noble potential, this second frequency signal charged to this load through this second switch and discharges.
According to another characteristics of the present invention, the present invention also provides a kind of driving method of semiconductor grid drive circuit, and this semiconductor grid drive circuit comprises a plurality of driver elements that are connected in series.Each driver element is used to drive load and comprises signal input part, output terminal, first switch and second switch.This driving method comprises: the first frequency signal is coupled to first switch of driver element, connects this first switch when this first frequency signal during for noble potential and through this first switch input signal is coupled to a node with the signal input part at this driver element; The second frequency signal is coupled to the second switch of this driver element; When the current potential of this node is connected this second switch during for noble potential,, this second frequency signal comes this load is charged and discharged to export signal so that being coupled to this output terminal through this second switch; And will export the signal input part that signal is coupled to the next stage driver element.
In semiconductor grid drive circuit of the present invention, said frequency signal is provided by frequency generator, and this frequency generator can be included in or be not included in this semiconductor grid drive circuit.In addition, this frequency generator can provide three or five frequency signals.
Description of drawings
Fig. 1 a is the block scheme of prior art LCD;
Fig. 1 b is the block scheme of another prior art LCD, and wherein the gate driver circuit of LCD is a semiconductor grid drive circuit;
Fig. 2 a is the block scheme according to the semiconductor grid drive circuit of the embodiment of the invention, and it uses 3 frequency signals;
Fig. 2 b is the frequency plot of the frequency signal that frequency generator produced among Fig. 2 a;
Fig. 3 a is the block scheme according to the semiconductor grid drive circuit of the embodiment of the invention, and it uses 5 frequency signals;
Fig. 3 b is the frequency plot of the frequency signal that frequency generator produced among Fig. 3 a;
Fig. 4 is the circuit diagram according to first driver element of first embodiment of the invention;
Fig. 5 a is the frequency plot of each signal in first driver element of Fig. 4;
Fig. 5 b is according to first switch of Fig. 5 a and the running synoptic diagram of second switch;
Fig. 6 is that it also includes mu balanced circuit according to the circuit diagram of first driver element of second embodiment of the invention;
Fig. 7 a is a kind of embodiment of the mu balanced circuit of Fig. 6;
Fig. 7 b is the another kind of embodiment of the mu balanced circuit of Fig. 6.
[primary clustering symbol description]
10 semiconductor grid drive circuits, 11 first driver elements
11 ' second driver element 11 " the 3rd driver element
12,12 ', 12 " signal input part 13, and 13 ', 13 " output terminal
16 mu balanced circuits, 20,20 ' frequency generator
The M1 first switch M2 second switch
Cx electric capacity X1 first node
Z1 Section Point Z2 the 3rd node
Input input signal Output exports signal
CLOAD load capacitance RLOAD pull-up resistor
M3～M8 switch VSS first current potential
VDD second current potential
T1, T2, T3 is during T4 drives
CK1, CK2, CK3, CK4, CK5 frequency signal
9,9 ' LCD, 91 picture element matrixs
92,92 ' gate driver circuit, 93 source electrode drive circuits
Embodiment
In order to make above and other objects of the present invention, characteristic and advantage more obvious, hereinafter will combine embodiment shown in the drawings to be elaborated.In addition, in the description of various embodiments of the present invention, identical or similar assembly uses identical symbolic representation.
Please with reference to Fig. 2 a, it shows the block scheme according to the semiconductor grid drive circuit 10 of the embodiment of the invention.This semiconductor grid drive circuit 10 comprises a plurality of driver elements that are connected in series; First driver element 11 (as first order driver element), second driver element 11 ' and the 3rd driver element 11 shown in for example scheming ", or the like; and receiving inputted signal and a plurality of frequency signal; wherein this frequency signal is provided by frequency generator 20, and this frequency generator 20 can comprise or be not included in this semiconductor grid drive circuit 10.
Each driver element, for example first driver element 11 includes signal input part 12 and output terminal 13 and receives two frequency signal CK1 and CK2.The output terminal of each grade driver element is coupled to the signal input part of next stage driver element; For example the output terminal 13 of this first driver element 11 is coupled to the signal input part 12 ' of this second driver element 11 '; The output terminal 13 ' of this second driver element 11 ' is coupled to the 3rd driver element 11 " signal input part 12 "; And because this first driver element 11 is the first order driver element of the driver element that is connected in series, the signal input part 12 of this first driver element 11 receives the input signal that these semiconductor grid drive circuits 10 are received.
With reference to Fig. 2 b; It shows the sequential chart of the frequency signal that the semiconductor grid drive circuit 10 according to the embodiment of the invention received; These frequency generator 20 generations three frequency signal CK1, CK2 and CK3, and this frequency signal at this moment have phase differential to each other, for example a pulse length.
Please with reference to Fig. 3 a, it shows the block scheme of the semiconductor grid drive circuit 10 of one alternate embodiment according to the present invention.This semiconductor grid drive circuit 10 comprises a plurality of driver elements that are connected in series equally, and receiving inputted signal and a plurality of frequency signal.The difference of Fig. 3 a and Fig. 2 a is, five frequency signals that this gate driver circuit 10 receives by frequency generator 20 ' provided.Likewise, this frequency generator 20 ' can comprise or be not included in this semiconductor grid drive circuit 10.
Please with reference to Fig. 3 b; The sequential chart of the frequency signal that its semiconductor grid drive circuit 10 that shows the alternate embodiment according to the present invention is received; This moment, this frequency generator 20 ' produced five frequency signal CK1, CK2, CK3, CK4 and CK5; Wherein this frequency signal CK1, CK2 and CK3 have phase differential to each other, for example a pulse length; The frequency of these frequency signals CK4 and CK5 for example can be frequency signal CK1, CK2 and CK3 frequency 1.5 times and frequency signal CK4 and CK5 has phase differential to each other, for example a pulse length.
Please with reference to Fig. 4, it shows the circuit diagram according to the driver element of the semiconductor grid drive circuit 10 of the embodiment of the invention, is that example describes with first driver element 11 here.This first driver element 11 has signal input part 12, output terminal 13, the first switch M1 and second switch M2, and wherein this first switch M1 and second switch M2 for example can be TFT or semiconductor switching component.This first driver element 11 is used to drive a row pixel cell, here with resistance R
LOADAnd capacitor C
LOADEquivalence one row pixel cell.This first switch M1 has first end that is coupled to this signal input part 12, is used to receive the input signal of this semiconductor grid drive circuit 10; Be coupled to second end of first node X; And be used to receive the control end of this frequency signal CK1.This second switch M2 has in order to receive first end of this second frequency signal CK2; Couple second end of this output terminal 13; And couple the control end of this first node X.In addition, the output terminal 13 of this first driver element 11 is coupled to the signal input part 12 ' of this second driver element 11 ', so the output signal of this first driver element 11 is as the input signal of this second driver element 11 '.In addition, this semiconductor grid drive circuit 10 can comprise the electric capacity that is coupled between this first node X and this output terminal 13 in addition, is used to reduce the effect that couples between stray capacitance and the signal of this first switch M1 and this second switch M2.
Please with reference to Fig. 5 a and 5b, it shows the driving method of the semiconductor grid drive circuit 10 of the embodiment of the invention.Fig. 5 a is the driver element of this semiconductor grid drive circuit 10; The signal timing diagram of current potential, this second frequency signal CK2 and this output terminal 13 of this signal input part 12, this first frequency signal CK1, this first node X in this first driver element 11 for example, Fig. 5 b then is with respect to this first switch M1 of Fig. 5 a and the mode of operation of this second switch M2.In addition, for ease of explanation, this sentences a resistance R
LOADAn and capacitor C
LOADThe load of this first driver element 11 of equivalence.And in following explanation, noble potential for example can be 15 volts; Electronegative potential for example can be-10 volts, but it is not in order to limit the present invention.
T1 between the first phase at first; The input signal Input that this signal input part 12 received is that noble potential and this first frequency signal CK1 also are noble potential; Therefore this first switch M1 connects, and this input signal Input is coupled to this first node X and also the current potential of this nodes X is charged to noble potential, therefore; This second switch M2 connects, and this second frequency signal CK2 is coupled to this output terminal 13.At this moment, because this second frequency signal CK2 is an electronegative potential, the output signal Output of these output terminal 13 output electronegative potentials.
At second phase T2, this input signal Input and this first frequency signal CK1 are electronegative potential, so this first switch M1 turn-offs.By the stray capacitance of this second switch M2, the current potential of this first node X still remains on noble potential, so this second switch M2 still is in on-state, and this second frequency signal CK2 continues to be coupled to this output terminal 13.At this moment, because this second frequency signal CK2 is a noble potential, the load capacitance C of this output terminal 13
LOADBe recharged to noble potential to export the output signal Output of a noble potential, it has a phase delay with respect to this input signal Input, for example the delay of a pulse length.
T3 between the third phase, this input signal Input and this first frequency signal CK1 are electronegative potential, and this first switch M1 keeps shutoff.By the stray capacitance of this second switch M2, the current potential of this first node X still maintains noble potential, so this second switch M2 still is in on-state.At this moment, because this second frequency signal CK2 is an electronegative potential, this load capacitance C
LOADBe discharged to the output signal Output of electronegative potential through this second switch M2 with the output electronegative potential.
T4 between the fourth phase, this first frequency signal CK1 are that noble potential is to connect this first switch M1.At this moment, because this input signal Input is an electronegative potential, this first node X is discharged to electronegative potential through this first switch M1 makes this second switch M2 turn-off.Because this load capacitance C
LOADT3 between the third phase be discharged to electronegative potential and not between the fourth phase T4 be recharged so output signal Output of this output terminal 13 output electronegative potentials once again.
Because driver element of the present invention only needs two switch modules (M1 and M2), therefore can effectively reduce circuit complexity and circuit space; In addition, this load capacitance C
LOADDischarge and recharge through same switch and carry out, can and then reduce the problem of switch module critical voltage skew.
Please with reference to Fig. 6 figure, it shows the semiconductor grid drive circuit 10 according to second embodiment of the invention, and it also includes second end that is coupled in this second switch M2 and the mu balanced circuit 16 between this output terminal 13, to reduce the problem that output voltage floats.
Please with reference to Fig. 7 a, it shows a kind of embodiment of mu balanced circuit.This mu balanced circuit 16 ' comprises the 3rd switch M3, the 4th switch M4 and the 5th switch M5, and this switch for example can be TFT or semiconductor switching component.The 3rd switch M3 has first end that is coupled to Section Point Z1, for example be coupled to second end and the control end that is coupled to this output terminal 13 of-10 volts the first current potential VSS.The 4th switch M4 have the second current potential VDD that for example is coupled to 15 volts first end, be coupled to second end of this Section Point Z1 and the control end that is coupled to its first end.The 5th switch M5 has first end that is coupled to this output terminal 13, second end that is coupled to this first current potential VSS and the control end that is coupled to this Section Point Z1.When the current potential of this output terminal 13 is electronegative potential; The 3rd switch M3 turn-offs, the 4th switch M4 connects and make the current potential of this Section Point Z1 be recharged to noble potential to connect the 5th switch M5, so the current potential of this output terminal 13 can be stablized and remains in electronegative potential.Otherwise when the current potential of this output terminal 13 is a noble potential, the 3rd switch M3 and the 4th switch M4 all connect and make the current potential of this Section Point Z1 be discharged to electronegative potential turn-offing the 5th switch M5, so the current potential of this output terminal 13 can be stablized and remains in noble potential.In addition, scrutable is that this mu balanced circuit 16 ' is coupled to after the output terminal of each driver element.
Please with reference to Fig. 7 b figure, it shows the another kind of embodiment of mu balanced circuit.This mu balanced circuit 16 " be coupled between two adjacent driver elements, for example between the output terminal 13 ' of the output terminal 13 of this first driver element 11 and second driver element 11 '.This mu balanced circuit 16 " include the 6th switch M6, minion pass M7 and octavo pass M8, and this switch for example can be TFT or semiconductor switching component.The 6th switch M6 has first end that is coupled to the 3rd node Z2, for example be coupled to second end and the control end that is coupled to the output terminal 13 of this first driver element 11 of-10 volts the first current potential VSS.This minion is closed M7 and is had first end that is coupled to the 3rd node Z2, is coupled to second end that this minion is closed the control end of M7 and is coupled to the output terminal 13 ' of this second driver element 11 '.This octavo is closed M8 and is had first end of the output terminal 13 that is coupled to this first driver element 11, the control end that is coupled to second end of this first current potential VSS and is coupled to the 3rd node Z2.Can know that by Fig. 5 a in the driver element that all are connected in series, the noble potential that the noble potential that the next stage driver element is exported is exported with respect to the upper level driver element has a phase delay.The output potential of the output terminal 13 ' of the output potential of therefore, supposing the output terminal 13 of this first driver element 11 here is 0100 (wherein 0 expression electronegative potential and 1 expression noble potential) and this second driver element 11 ' is 0010.When this output terminal 13 is that noble potential and this output terminal 13 ' is during for electronegative potential; The 6th switch M6 connects and makes the 3rd node Z2 be discharged to electronegative potential and turn-off the 8th switch; And this minion is closed M7 and is also turn-offed, so the current potential of this output terminal 13 can be stablized and remains in noble potential; During next; This output terminal 13 is a noble potential for this output terminal 13 ' of electronegative potential; The 6th switch M6 turn-offs and this minion is closed M7 and connected, and the 3rd node Z2 is recharged and connects this octavo to noble potential and close M8, so the current potential of this output terminal 13 can be stablized and remains in electronegative potential; During next; This output terminal 13 and this output terminal 13 ' are electronegative potential; The 6th switch M6 and minion are closed M7 and are all turn-offed, and the current potential of the 3rd node Z2 was still connected this octavo for noble potential and closed M8 this moment, so the current potential of this output terminal 13 can be stablized and remains in electronegative potential.Hence one can see that, and the noble potential output of the output terminal 13 of this first driver element 11 can be kept till the output terminal 13 ' of this second driver element 11 ' is output as noble potential.In addition, this mu balanced circuit can include the capacitor C that is coupled between the 3rd node Z2 and this first current potential VSS in addition.
In sum, because semiconductor grid drive circuit needs simple circuit configuration and less circuit production space, so the present invention proposes a kind of gate driver circuit that only needs two switches, can effectively reduce cost.In addition, owing to semiconductor grid drive circuit of the present invention only discharges and recharges load through single switch, and can eliminate the problem that the switch module critical voltage squints.
Though described the present invention through the foregoing description, yet the present invention is not limited thereto, the those of ordinary skill of technical field is not breaking away from the spirit and scope of the present invention under any the present invention, can make various modifications and modification.Therefore protection scope of the present invention is limited by the accompanying claims.
Claims (14)
1. a gate driver circuit has signal input part and output terminal, and said gate driver circuit is made up of following assembly:
First switch, the control end that it has first end that couples said signal input part, second end that couples first node and receives the first frequency signal, said first switch is connected during for noble potential at said first frequency signal; And
Second switch; It has first end that receives the second frequency signal, the control end that couples second end of said output terminal and couple said node; Wherein said second switch is connected during for noble potential at said node, so that said second frequency signal is coupled to said output terminal.
2. gate driver circuit according to claim 1, wherein said first switch and second switch are TFT.
3. gate driver circuit according to claim 1 has phase differential between wherein said first frequency signal and the said second frequency signal.
4. gate driver circuit according to claim 1, wherein when said first node was noble potential, said second frequency signal charged to load through said second switch and discharges.
5. gate driver circuit according to claim 4 also comprises the electric capacity between second end that is coupled in said first node and said second switch.
6. gate driver circuit according to claim 4 also comprises second end that is coupled in said second switch and the mu balanced circuit between the said output terminal.
7. semiconductor grid drive circuit, it receives a plurality of frequency signals and comprises a plurality of gate driver circuits according to claim 4 that are connected in series,
Wherein the output terminal of each gate driver circuit is coupled to the signal input part of next stage gate driver circuit.
8. semiconductor grid drive circuit according to claim 7, wherein each gate driver circuit also comprises second end that is coupled to said second switch and the mu balanced circuit between the said output terminal.
9. semiconductor grid drive circuit according to claim 8; Wherein said mu balanced circuit comprises the 3rd switch, the 4th switch and the 5th switch, and wherein said the 3rd switch has first end that couples Section Point, couple second end of first current potential and couple the control end of said output terminal; Said the 4th switch has first end that couples second current potential, couple second end of said Section Point and couple the control end of first end of said the 4th switch; Said the 5th switch has the control end that first end that couples said output terminal, second end that couples said first current potential and idol are received said Section Point, and said first current potential is lower than said second current potential.
10. semiconductor grid drive circuit according to claim 8; Wherein said mu balanced circuit comprises that the 6th switch, minion close and octavo is closed, and wherein said the 6th switch has first end that couples the 3rd node, couple second end of first current potential and couple the control end of said output terminal; Said minion is closed second end of the output terminal that has first end that couples said the 3rd node, couples the next stage driver element and is coupled the control end of second end that said minion closes; Said octavo is closed to be had first end that couples said output terminal, couples second end of said first current potential and the control end that couples said the 3rd node.
11. the driving method of a semiconductor grid drive circuit; Said semiconductor grid drive circuit comprises a plurality of driver elements that are connected in series; Each driver element is used to drive load and comprises signal input part, output terminal, first switch and second switch, and said driving method comprises:
The first frequency signal is coupled to first switch of driver element, connects said first switch when said first frequency signal during for noble potential and through said first switch input signal is coupled to a node with signal input part at said driver element; And
The second frequency signal is coupled to the second switch of said driver element; When the current potential of said node is connected said second switch during for noble potential,, said second frequency signal comes said load is charged and discharged to export signal so that being coupled to said output terminal through said second switch.
12. driving method according to claim 11 also comprises the following steps: said output signal is coupled to the signal input part of next stage driver element.
13. driving method according to claim 11 has phase differential between wherein said first frequency signal and the said second frequency signal.
14. driving method according to claim 11 has phase differential between wherein said input signal and the said output signal.
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| CN102646401B (en) * | 2011-12-30 | 2013-10-16 | 北京京东方光电科技有限公司 | Shift register, global outstanding assessment (GOA) panel and grid electrode driving method |
| CN103761944B (en) | 2013-12-25 | 2017-01-25 | 合肥京东方光电科技有限公司 | Gate drive circuit, display device and drive method |
| CN104157232B (en) * | 2014-08-01 | 2016-08-17 | 合肥京东方光电科技有限公司 | Gating drive circuit, gating driving method, array base palte and display device |
| CN106647072A (en) * | 2016-10-20 | 2017-05-10 | 深圳市华星光电技术有限公司 | Array substrate, liquid crystal displayer and display device |
| CN113794469B (en) * | 2021-09-03 | 2023-09-22 | 中国科学院电工研究所 | Frequency multiplication gate driving circuit and frequency multiplication control method thereof |
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