CN101727167A - power switching circuit - Google Patents

Abstract

The present invention discloses a power switching circuit, which is configured on a mainboard of a notebook computer, and the power switching circuit is characterized in that it includes a power-on detection circuit and a power-off unit. The power-on detection circuit is used to detect whether a power button of the notebook computer in a standby state is pressed, and output a power-on status signal accordingly. The power-off unit is coupled to the power-on detection circuit, and is used to determine whether to cut off all power rails on the mainboard according to the power-on status signal.

Description

power switching circuit

technical field

The present invention relates to an energy-saving technology, and in particular relates to a power switching circuit capable of reducing the power consumption of the mainboard of a notebook computer in a standby state.

Background technique

As the energy crisis is approaching, the awareness of environmental protection is gradually rising. In recent years, the US government has proposed energy-saving standards such as 80Plus and Energy Star (Energy Star) in order to regulate the energy consumption of electronic products. Among them, the latest version of the Energy Star 4.0 standard came into effect in July 2007, and its requirements for the standby power consumption of notebook computers (Notebooks) appear to be quite stringent.

The latest version of Energy Star 4.0 stipulates that when the motherboard of the notebook computer (motherboard) does not support the Wake On Lan (WOL) function, when the notebook computer is in hibernation (hibernation, S4) and shutdown (power off, S5) waiting In the standby state, its standby power consumption should be lower than 0.7W.

However, when the DC jack of the notebook computer is plugged into the voltage converter (adaptor), since the power management chip on the motherboard (such as the TPS51120 power management chip) will still receive the standby power (+VBATR) for continuous Generates +3V and +5V power rails for chips on the motherboard. As a result, the power consumed by these chips will likely cause the notebook computer to consume more than the 0.7W specified by Energy Star 4.0 when it is in hibernate (S4) and powered off (S5) states.

Contents of the invention

In view of this, the object of the present invention is to provide a power switching circuit, which can cause the notebook computer to be in sleep (S4) and shutdown (S5) states when the motherboard of the notebook computer does not support the wake-up on network (WOL) function. Standby power consumption is close to 0W to comply with Energy Star 4.0 regulations.

The invention provides a power switching circuit, which is configured on the main board of the notebook computer. The power switch circuit is characterized in that it includes a power-on detection circuit and a power cut-off unit. Wherein, the power-on detection circuit is used to detect whether the power button of the notebook computer in the standby state is pressed, and output a power-on state signal accordingly. The power cut-off unit is coupled to the power-on detection circuit for determining whether to cut off all power rails on the motherboard according to the power-on state signal.

In an embodiment of the present invention, the power-on detection circuit includes a first resistor, a second resistor, a first NMOS transistor, a first capacitor, and a Zener diode. Wherein, one end of the first resistor and the second resistor is coupled to a standby power supply. The gate of the first NMOS transistor is coupled to the power button and the other end of the first resistor, the drain of the first NMOS transistor is coupled to the other end of the second resistor, and the first The source of the NMOS transistor is coupled to the ground potential.

One end of the first capacitor is coupled to the drain of the first NMOS transistor, and the other end of the first capacitor is coupled to the ground potential. The anode terminal of the Zener diode is coupled to the ground potential, and the cathode terminal of the Zener diode is coupled to the drain of the first NMOS transistor, and outputs the power-on state signal.

In an embodiment of the present invention, the power cut-off unit includes a PMOS transistor, a third resistor, a fourth resistor, a second NMOS transistor, a fifth resistor, a second capacitor, a first diode, a second diode , and the third diode. Wherein, the source of the PMOS transistor is coupled to the standby power, and the drain of the PMOS transistor outputs the standby power when the PMOS transistor is turned on. One end of the third resistor is coupled to the source of the PMOS transistor, and the other end of the third resistor is coupled to the gate of the PMOS transistor.

One end of the fourth resistor is coupled to the gate of the PMOS transistor. The drain of the second NMOS transistor is coupled to the other end of the fourth resistor, and the source of the second NMOS transistor is coupled to the ground potential. One end of the fifth resistor is coupled to the gate of the second NMOS transistor, and the other end of the second NMOS transistor is coupled to the ground potential. One end of the second capacitor is coupled to the gate of the second NMOS transistor, and the other end of the second capacitor is coupled to the ground potential.

The anode terminal of the first diode is used to receive the wake-up signal, and the cathode terminal of the first diode is coupled to the gate of the second NMOS transistor. The anode terminal of the second diode is used to receive the power sustaining signal, and the cathode terminal of the second diode is coupled to the gate of the second NMOS transistor. The anode terminal of the third diode is used to receive the power-on state signal, and the cathode terminal of the third diode is coupled to the gate of the second NMOS transistor.

In an embodiment of the present invention, when the power button of the notebook computer in the standby state is not pressed, both the power supply maintenance signal and the power-on state signal are at a low voltage level.

In an embodiment of the present invention, when the power button of the notebook computer in the standby state is pressed, the power maintaining signal and the power-on state signal are at a high voltage level. As a result, the PMOS transistors are turned on, restoring all power rails on the motherboard.

In an embodiment of the present invention, when the motherboard supports the wake-on-lan function, the wake-on-lan signal is at a high voltage level, otherwise it is at a low voltage level.

In an embodiment of the present invention, the network wake-up signal is provided by the network control chip on the main board, and the power supply maintenance signal is provided by the keyboard control chip on the main board.

In an embodiment of the present invention, the standby state is a hibernation state or a power off state.

The present invention further provides a motherboard with the power switching circuit proposed in the present invention.

The present invention further provides a notebook computer having the above-mentioned motherboard proposed by the present invention.

The present invention mainly configures a power switching circuit directly on the main board of the notebook computer. This power switching circuit can cut off all power rails on the motherboard when the motherboard of the notebook computer does not support Wake-on-LAN (WOL), and when the notebook computer is in sleep (S4) and shutdown (S5) states, thereby causing the notebook computer to Standby power consumption is close to 0W when the computer is hibernated and powered off to comply with ENERGY STAR 4.0 regulations.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, several embodiments of the present invention will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a notebook computer according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a power-on detection circuit according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of a power cut-off unit according to an embodiment of the present invention.

Detailed ways

The technical effect that the present invention intends to achieve is mainly to allow the motherboard of the notebook computer not to support the wake-on-lane function (WOL), and its standby power consumption in the sleep (S4) and shutdown (S5) states can meet the energy requirements. Star 4.0 regulations. The following content will be described in detail with regard to the technical features of this case, so as to provide reference for those skilled in the art.

FIG. 1 is a schematic diagram of a notebook computer 100 according to an embodiment of the present invention. Referring to FIG. 1, the notebook computer 100 includes a motherboard 101 and a power button (power button) PB. Certainly, those skilled in the art should know that the notebook computer 100 also includes other components, such as a display screen, an optical drive, .

In this embodiment, the mainboard 101 includes a power switching circuit (directly configured on the mainboard 101) composed of a power-on detection circuit 103 and a power cut-off unit 105, a network control chip 107, a keyboard control chip 109, and a power management chip 111. (For example, TPS51120 power management chip). Wherein, the power-on detection circuit 103 is used to detect whether the power button PB of the notebook computer 100 in the standby state (such as the state of hibernation (S4) or power-off (S5)) is pressed, and output the power-on state signal PWRSW accordingly; The power cut-off unit 105 is coupled to the power-on detection circuit 103 for determining whether to cut off all power rails on the motherboard 101 according to the power-on status signal PWRSW.

To be more clear, FIG. 2 is a circuit diagram of the power-on detection circuit 103 according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 2 together. The power-on detection circuit 103 includes a first resistor R1, a second resistor R2, an NMOS transistor N1, a first capacitor C1, and a Zener diode (Zener Diode) ZD (for example, a Zener diode of about 3V ). Wherein, one end of the first resistor R1 and the second resistor R2 is coupled to the standby power supply +VBATR (approximately 18.5V), and the standby power supply +VBATR will be plugged into the DC jack (DCjack, not shown) of the notebook computer 100 at the voltage A converter (adaptor, not shown) is generated.

The gate of the first NMOS transistor N1 is coupled to the power button PB and the other end of the first resistor R1, the drain of the first NMOS transistor N1 is coupled to the other end of the second resistor R2, and the first NMOS The source of the transistor N1 is coupled to the ground potential. One end of the first capacitor C1 is coupled to the drain of the first NMOS transistor N1, and the other end of the first capacitor C1 is coupled to the ground potential. An anode of the Zener diode ZD is coupled to the ground potential, and a cathode of the Zener diode ZD is coupled to the drain of the first NMOS transistor N1, and outputs the power-on state signal PWRSW.

In this embodiment, when the power button PB of the notebook computer 100 in the sleep (S4) and shutdown (S5) states is not pressed, the power-on state signal PWRSW is at a low voltage level, but when it is in the sleep (S4) and shutdown (S5) states, the power button PB is not pressed. When the power button PB of the notebook computer 100 in the shutdown state ( S5 ) is pressed, the power-on state signal PWRSW is at a high voltage level.

In addition, FIG. 3 is a circuit diagram of the power cut-off unit 105 according to an embodiment of the present invention. Please refer to FIGS. 1-3 together. The power cut-off unit 105 includes a PMOS transistor P1, a third resistor R3, a fourth resistor R4, an NMOS transistor N2, a fifth resistor R5, a second capacitor C2, a first diode D1, a Two diodes D2, and a third diode D3. Wherein, the source of the PMOS transistor P1 is coupled to the standby power +VBATR, and the drain of the PMOS transistor P1 outputs the standby power +VBATR to the power management chip 111 when the PMOS transistor P1 is turned on.

One end of the third resistor R3 is coupled to the source of the PMOS transistor P1 , and the other end of the third resistor R3 is coupled to the gate of the PMOS transistor P1 . One end of the fourth resistor R4 is coupled to the gate of the PMOS transistor P1. The drain of the NMOS transistor N2 is coupled to the other end of the fourth resistor R4, and the source of the NMOS transistor N2 is coupled to the ground potential.

One end of the fifth resistor R5 is coupled to the gate of the NMOS transistor N2, and the other end of the NMOS transistor N2 is coupled to the ground potential. One end of the second capacitor C2 is coupled to the gate of the NMOS transistor N2, and the other end of the second capacitor C2 is coupled to the ground potential. The anode of the first diode D1 is used to receive the network wake-up signal NIC_GPIO provided by the network control chip 107 , and the cathode of the first diode D1 is coupled to the gate of the NMOS transistor N2 .

The anode of the second diode D2 is used to receive the power sustain signal KBC_PWRKEEP provided by the keyboard controller 109 , and the cathode of the second diode D2 is coupled to the gate of the NMOS transistor N2 . The anode terminal of the third diode D3 is used to receive the power-on state signal PWRSW, and the cathode terminal of the third diode D3 is coupled to the gate of the NMOS transistor N2.

In this embodiment, when the power button PB of the notebook computer 100 is not pressed when it is in sleep (S4) and shutdown (S5) states, the power supply maintenance signal KBC_PWRKEEP is at a low voltage level, but when it is in sleep (S4) and When the power button PB of the notebook computer 100 in the shutdown state ( S5 ) is pressed, the power sustaining signal KBC_PWRKEEP is at a high voltage level. In addition, when the motherboard 101 supports the WOL function, the WOL signal NIC_GPIO is at a high voltage level, otherwise it is at a low voltage level.

Based on the above, when the motherboard 101 does not support the WOL function, the WOL signal NIC_GPIO will be at a low voltage level. In this way, when the power button PB of the notebook computer 100 is not pressed in the hibernation (S4) and shutdown (S5) states, both the power-on state signal PWRSW and the power supply maintenance signal KBC_PWRKEEP are at a low voltage level, so the PMOS transistor P1 will be cut off.

Under this condition, since the standby power +VBATR will not be supplied to the power management chip 111, the power management chip 111 will not continue to generate +3V and +5V power rails for the chips of the motherboard 101 to use as in the prior art (also That is, all power rails on the motherboard 101 are cut off), so that the standby power consumption of the notebook computer 100 in the hibernation (S4) and shutdown (S5) states will approach 0W, so that it can meet the requirements of Energy Star 4.0.

However, when the power button PB of the notebook computer 100 in the hibernation (S4) and shutdown (S5) states is pressed, the power-on state signal PWRSW will change from a low voltage level to a high voltage level, so the NMOS transistor N2 will be turned on, so that the PMOS transistor P1 will also be turned on.

Under this condition, since the standby power +VBATR will be normally supplied to the power management chip 111, the power management chip 111 will continue to generate +3V and +5V power rails for the chips of the motherboard 101 to use as in the prior art (that is, restore all power rails on the mainboard 101). In this way, when the keyboard control chip 109 receives the +3V power rail, it will change the power supply maintenance signal KBC_PWRKEEP from a low voltage level to a high voltage level, so that when the power button PB returns to the unpressed state , the NMOS transistor N2 can be kept in the conduction state, so the notebook computer 100 can complete subsequent booting actions.

On the contrary, when the motherboard 101 supports the WOL function, the WOL signal NIC_GPIO will be at a high voltage level. In this way, even if the power button PB of the notebook computer 100 is not pressed in the hibernation ( S4 ) and shutdown ( S5 ) states, the NMOS transistor N2 is still turned on, so that the PMOS transistor P1 is also turned on.

Under this condition, since the standby power +VBATR will be normally supplied to the power management chip 111, the power management chip 111 will continue to generate +3V and +5V power rails for the chips of the motherboard 101 to use as in the prior art (that is, restore all power rails on the mainboard 101). In this way, the motherboard 101 can support the wake-on-lan (WOL) function.

To sum up, the present invention mainly configures a power switching circuit directly on the motherboard of the notebook computer. This power switching circuit can cut off all power rails on the motherboard when the motherboard of the notebook computer does not support Wake-on-LAN (WOL), and when the notebook computer is in sleep (S4) and shutdown (S5) states, thereby causing the notebook computer to The standby power consumption of the computer in hibernation and shutdown states is close to 0W, so as to meet the requirements of Energy Star 4.0, and at the same time, it can extend the battery power supply time of the notebook computer.

Although the present invention has been disclosed above with a number of embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some modifications and changes without departing from the spirit and scope of the present invention. modification, so the protection scope of the present invention should be defined by the claims.

Claims (12)

1. a power supply switch circuit is disposed on the mainboard of a notebook, it is characterized in that this power supply switch circuit comprises:

One start testing circuit, whether a power knob that is in this notebook under the holding state in order to detection is pressed, and exports an open state signal according to this; And

One power switching unit couples this start testing circuit, determines whether to cut off all power rails on this mainboard according to this open state signal.

2. power supply switch circuit as claimed in claim 1 is characterized in that, this start testing circuit comprises:

One first resistance, the one end couples a standby power;

One second resistance, the one end couples this standby power;

One first nmos pass transistor, its grid couples the other end of this power knob and this first resistance, and its drain electrode couples the other end of this second resistance, and its source electrode then is coupled to an earthing potential;

One first electric capacity, the one end couples the drain electrode of this first nmos pass transistor, and its other end then is coupled to this earthing potential; And

One Zener diode, its anode tap couples this earthing potential, and its cathode terminal then couples the drain electrode of this first nmos pass transistor, and exports this open state signal.

3. power supply switch circuit as claimed in claim 2 is characterized in that, this power switching unit comprises:

One PMOS transistor, its source electrode couples this standby power, and this standby power is then exported in its drain electrode when this PMOS transistor turns;

One the 3rd resistance, one end couple the transistorized source electrode of this PMOS, and its other end then is coupled to the transistorized grid of this PMOS;

One the 4th resistance, one end couple the transistorized grid of this PMOS;

One second nmos pass transistor, its drain electrode couples the other end of the 4th resistance, and its source electrode then is coupled to this earthing potential;

One the 5th resistance, the one end couples the grid of this second nmos pass transistor, and its other end then is coupled to this earthing potential;

One second electric capacity, the one end couples the grid of this second nmos pass transistor, and its other end then is coupled to this earthing potential;

One first diode, its anode tap is in order to receive a WOL (Wake On LAN) signal, and its cathode terminal then is coupled to the grid of this second nmos pass transistor;

One second diode, its anode tap is kept signal in order to receive a power supply, and its cathode terminal then is coupled to the grid of this second nmos pass transistor; And

One the 3rd diode, its anode tap is in order to receive this open state signal, and its cathode terminal then is coupled to the grid of this second nmos pass transistor.

4. power supply switch circuit as claimed in claim 3 is characterized in that, when this power knob of this notebook under being in this holding state was not pressed, this power supply keeps signal and this open state signal is all a low voltage level.

5. power supply switch circuit as claimed in claim 4 is characterized in that, when this power knob of this notebook under being in this holding state was pressed, this power supply keeps signal and this open state signal is a high-voltage level.

6. power supply switch circuit as claimed in claim 5 is characterized in that, when this power supply was kept signal and this open state signal and is all this high-voltage level, this PMOS transistor can conducting, uses all power rails of replying on this mainboard.

7. power supply switch circuit as claimed in claim 3 is characterized in that, when this mainboard was supported a calling function of network, this WOL (Wake On LAN) signal was a high-voltage level, otherwise was a low voltage level.

8. power supply switch circuit as claimed in claim 3 is characterized in that, this WOL (Wake On LAN) signal is provided by the network control chip on this mainboard.

9. power supply switch circuit as claimed in claim 3 is characterized in that, this power supply is kept signal and provided by the keyboard control chip on this mainboard.

10. power supply switch circuit as claimed in claim 1 is characterized in that, this holding state is a dormant state or an off-mode.

11. mainboard with power supply switch circuit as claimed in claim 1.

12. notebook with mainboard as claimed in claim 11.

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