CN101714401B - Subthreshold sensitive amplifying circuit for reinforcing capacity and density of memory cell array - Google Patents

Abstract

The invention relates to a subthreshold sensitive amplifying circuit for reinforcing the capacity and the density of a memory cell array, which is provided with five PMOS pipes P1-P5 and six NMOS pipes N1-N6, wherein the source terminal of the PMOS pipe P1 is connected with a power supply, and the drain terminal of the P1 is connected with the source terminals of P4 and P5; the source terminal of the PMOS pipe P2 is connected with the power supply, and the drain terminal of P2 is connected with the gate terminal of P4 and the drain terminal of the NMOS pipe N1 at a bit line BL; the source terminal of the PMOS pipe P3 is connected with the power supply, and the drain terminal of P3 is connected with the gate terminal of P5 and the drain terminal of the NMOS pipe N2 at a non-bit line NBL; the gate terminal of the NMOS pipe N3, the gate terminal of N4 and the gate terminal of P1 are connected with a sensitive amplifier for enabling signal pre; the source terminal of the NMOS pipe N3 and the source terminal of N4 are connected with the ground; the source terminal of the NMOS pipe N1 and the source terminal of N2 are connected with the ground; the source terminal of the NMOS pipe N5 and the source terminal of N6 are connected with the ground; the gate terminal of the PMOS pipe P2 and the drain terminal of P4 are connected with the drain terminal of the NMOS pipe N3, the gate terminal of N1, the drain terminal of N5 and the gate terminal of N6; and the gate terminal of the PMOS pipe P3 and the drain terminal of P5 are connected with the drain terminal of the NMOS pipe N4, the gate terminal of N2, the gate terminal of N5 and the drain terminal of N6.

Description

In order to strengthen the subthreshold value sensitive amplifying circuit of memory cell array capacity and density

Technical field

The present invention relates to the sensitive amplifying circuit of subthreshold value field (supply voltage is less than transistorized threshold voltage), particularly a kind of in order to strengthen the subthreshold value sensitive amplifying circuit of memory cell array capacity and density.It is mainly for the general weak situation of subthreshold value zone internal memory storage unit reading and writing ability, according to the actual information in the selected storage unit, dynamic compensation reading and writing ability, thereby strengthen the impact of choosing the storage unit firing current pairs of bit line amplitude of oscillation, so that fairly large memory cell array becomes possibility.

Background technology

Memory cell array is the important component part of Modern Digital System, also the power consumption bottleneck of system often.Have higher requirement to the reduction power consumption technology of memory cell array to improving constantly of various portable set demands in market.The subthreshold value design is the hot topic of current ultralow Consumption.Enter the subthreshold value zone of circuit by reducing supply voltage (Vdd)---Vdd is less than threshold voltage (Vth) so that system works is at the linear zone of circuit, so significantly reduce system dynamically, quiescent dissipation.The design of sub-threshold memory cell array has highlighted the low-power consumption superiority of subthreshold value design especially.But series of problems has also been introduced in this design in concrete implementation procedure: 1) during actual motion, storage unit reading and writing ability generally a little less than; 2) number of memory cells of same bit line series connection is limited, so that the capacity of memory cell array is limited, and area consumption is large; 3) the neutrality line amplitude of oscillation is less the read cycle, and the detection margin of sense amplifier is less; 4) performance is subject to the impact of process deviation etc.The key point of problem be because open in the subthreshold value zone, cut-off current is less than (Ion/Ioff)---unlatching in the normal design, cut-off current are roughly 10 than (Ion/Ioff) ⁷, and this value only is 10 in the subthreshold value design ³-10 ⁴As everyone knows, storage unit is one and is subjected to the larger logical block of area restriction, less transistor size so that his reading and writing driving force itself further worsen, the leakage current that is not selected logical block coupling pipe on the bit line is far longer than under the corresponding conditions it in the impact in superthreshold zone to the impact of memory cell array, and should impact can further worsen under the impact of process deviation.If do not leave enough redundances (the series connected memory cell number is greater than certain limit on the bit line), the leakage current of the not selected storage unit that the firing current of selected unit may be accumulated disturbs, so that the correct logic of subsequent conditioning circuit None-identified causes the read-write inefficacy (Fig. 1) of storage unit.Consider the bias voltage of process deviation and follow-up sense amplifier, number of memory cells can further be limited on the single bit line.The memory cell array design inclination in present subthreshold value zone is in two kinds of designs: 1) carefully calculate the proportionate relationship of transistor firing current and cut-off current in the various process corner, strictly control the number of the storage unit of connecting on the same bit line; 2) add the leakage compensated logic in storage unit inside.But memory cell array is large capacity logical block, to the design density higher requirement is arranged, above two kinds of methods all can not effectively solve the excessive problem of memory cell array chip area consumption.

Summary of the invention

The present invention seeks to the characteristic that has according to circuit in the subthreshold value zone, for the key issue that the subthreshold value memory circuit faces, provide a kind of in order to strengthen the subthreshold value sensitive amplifying circuit of memory cell array capacity and density.The number of memory cells that can connect on can be for increasing the sub-threshold memory cell array alignment when its small-signal on realizing the storage unit bit line is amplified to full amplitude of oscillation function, thus memory cell array capacity and density strengthened.It is mainly for the general weak situation of subthreshold value zone internal memory storage unit reading and writing ability, according to the actual information in the selected storage unit, dynamic compensation reading and writing ability, thereby strengthen the impact of choosing the storage unit firing current pairs of bit line amplitude of oscillation, so that fairly large memory cell array becomes possibility.

For achieving the above object, the present invention adopts following technical scheme:

A kind of in order to strengthen the subthreshold value sensitive amplifying circuit of memory cell array capacity and density, it is characterized in that: be provided with and comprise five PMOS pipe P1～P5 and six NMOS pipe N1～N6, totally 11 transistors, wherein, the source termination power of PMOS pipe P1, the drain terminal of PMOS pipe P1 is connected jointly with the source of PMOS pipe P4 and PMOS pipe P5; The source termination power of PMOS pipe P2, the drain terminal of PMOS pipe P2 jointly is connected in a bit with the drain terminal that grid end and the NMOS of PMOS pipe P4 manage N1 and this point is connected bit line BL; The source termination power of PMOS pipe P3, the drain terminal of PMOS pipe P3 jointly is connected in a bit with the drain terminal that grid end and the NMOS of PMOS pipe P5 manage N2 and this point is connected the non-NBL of bit line; The grid end of NMOS pipe N3 jointly is connected in a bit with the grid end that grid end and the PMOS of NMOS pipe N4 manage P1 and this point is connected sense amplifier enable signal pre; The source of the source of NMOS pipe N3 and NMOS pipe N4 all is connected with ground, the source of the source of NMOS pipe N1 and NMOS pipe N2 all is connected with ground, the source of the source of NMOS pipe N5 and NMOS pipe N6 all is connected with ground, and the grid end of the drain terminal of the grid end of PMOS pipe P2, PMOS pipe P4, the drain terminal of NMOS pipe N3, NMOS pipe N1, the drain terminal of NMOS pipe N5 and the grid end of NMOS pipe N6 connect jointly; The drain terminal of the grid end of the grid end of the drain terminal of the drain terminal of the grid end of PMOS pipe P3, PMOS pipe P5, NMOS pipe N4, NMOS pipe N2, NMOS pipe N5 and NMOS pipe N6 connects jointly.

Advantage of the present invention and remarkable result effect: the present invention is operated in the subthreshold value zone and can amplifies by the information in the selected storage unit of identification, feeds back on the bit line again.Reading of reality, in the write operation process, the reading of memory cell array, writing driving force is provided simultaneously by selected memory cell array and amplifying circuit.

(1) behind the preliminary filling EO, the word line of selected storage unit is opened, and the signal of storing on the selected storage unit can be delivered on the bit line.Meeting of the present invention is according to canned data in the dynamic recognition memory cell of voltage difference small on the bit line, and this signal is amplified to the full amplitude of oscillation (0 or Vdd).

(2) the present invention can feed back to Dynamic Recognition and the signal that is amplified to the full amplitude of oscillation on the bit line again, strengthen in the concrete reading and writing operating process effective firing current and do not choose the ratio of storage unit cut-off current, thereby strengthen the number of memory cells that same bit line is connected.

(3) the present invention can increase power consumption in the capacity of memory cell array and the method for density (circuit), area consumption minimum at present known.

(4) bit line does not have voltage difference between selected storage unit and the present invention, has further reduced leakage current and race and hazard phenomenon.

(5) be in draw on the storage unit in subthreshold value zone ability generally a little less than, circuit of the present invention draws driving on can automatically regulating accordingly according to the actual information of storing on the memory cell array, so that the bit line high logic level can correctly be identified in the subsequent logic unit, break through the read operation bottleneck.

(6) by the dynamic adjustment of sensitive amplifying circuit of the present invention, successfully solve the problem that subthreshold value zone circuit is opened, cut-off current is more weak than (Ion/Ioff), need not to add auxiliary circuit, need not extra power consumption.

(7) self dynamically adjusts, and timing control signal is simple, has avoided being in the mistake of the larger introducing of delay deviation of sub-threshold region circuit.

Description of drawings

Fig. 1 is the logic diagram of a row sub-threshold storage array;

Fig. 2 is circuit structure diagram of the present invention;

Fig. 3 is that not adopt the present invention be BL in the read operation process, NBL, the transient changing of Q and NQ;

Fig. 4 is that employing the present invention is BL in the read operation process, NBL, the transient changing of Q and NQ.

Embodiment

With reference to Fig. 2, the present invention is provided with five PMOS pipe P1～P5 and six NMOS pipe N1～N6, totally 11 transistors, wherein, and the source termination power of PMOS pipe P1, the drain terminal of PMOS pipe P1 is connected jointly with the source that PMOS pipe P4 and PMOS manage P5; The source termination power of PMOS pipe P2, the drain terminal of PMOS pipe P2 jointly is connected in a bit with the drain terminal that grid end and the NMOS of PMOS pipe P4 manage N1 and this point is connected bit line BL; The source termination power of PMOS pipe P3, the drain terminal of PMOS pipe P3 jointly is connected in a bit with the drain terminal that grid end and the NMOS of PMOS pipe P5 manage N2 and this point is connected the non-NBL of bit line; The grid end of NMOS pipe N3 jointly is connected in a bit with the grid end that grid end and the PMOS of NMOS pipe N4 manage P1 and this point is connected sense amplifier enable signal pre; The source of the source of NMOS pipe N3 and NMOS pipe N4 all is connected with ground, the source of the source of NMOS pipe N1 and NMOS pipe N2 all is connected with ground, the source of the source of NMOS pipe N5 and NMOS pipe N6 all is connected with ground, and the grid end of the drain terminal of the grid end of PMOS pipe P2, PMOS pipe P4, the drain terminal of NMOS pipe N3, NMOS pipe N1, the drain terminal of NMOS pipe N5 and the grid end of NMOS pipe N6 connect jointly; The drain terminal of the grid end of the grid end of the drain terminal of the drain terminal of the grid end of PMOS pipe P3, PMOS pipe P5, NMOS pipe N4, NMOS pipe N2, NMOS pipe N5 and NMOS pipe N6 connects jointly.

Suppose the inner Q=" 1 " of selected storage unit, NQ=" 0 ".During read operation, (the word line of this storage unit is " 1 " to choose the coupling pipe of storage unit to open, WL=1), the bit line of the Information Conduction complementation of storage unit storage inside is to upper, should be in theory completely supply voltage value Vdd on the bit line BL, and should be completely zero potential on the non-NBL of bit line.But since the storage unit of not choosing of the electric capacity on the bit line and accumulation (the word line of this storage unit is for " 1 ", the existence of leakage current WL=0), so that: the magnitude of voltage on the bit line BL is the magnitude of voltage (Δ V1) greater than 0, and the upper magnitude of voltage of the non-NBL of bit line be less than Vdd a magnitude of voltage (Vdd-Δ V2) (Fig. 3).In fact the driveability of P transistor npn npn is obviously not as N-type transistor (minimum value of P transistor npn npn leakage current approximately is the transistorized 22%under|Vds|=|Vgs|=200mV of N-type, 0.13um technique).So the probability of in the design of sub-threshold memory cell array, reading " 1 " error in operation is greater than the probability of reading " 0 " error in operation (Δ V2＞＞Δ V1).

Fig. 3 (a) reads " 1 " and reads the simulation result of " 0 " under 4 storage unit of every bit lines series connection.All transistors all are the minimum transistor width and are conventional connected mode (body of P transistor npn npn is connected to supply voltage Vdd, and the transistorized body of N-type is connected to ground gnd).This simulation result is to obtain at the worst condition of the read cycle of memory cell array (not selected storage unit is opposite with the storage information of selected storage unit).In Fig. 3 (a), the sense bit line BL of storage unit is pulled down to 108.9mV.Meanwhile owing to not choosing the impact of cell leakage current, the non-NBL of bit line by on move 6.216mV to.Fig. 3 (b) reads " 1 " and reads the simulation result of " 0 " under 8 storage unit of every bit lines series connection.Since pull open on the selected storage unit and open electric current and can't keep voltage on the bit line BL greater than the reversal voltage of storage unit, the storage unit counter-rotating, and reading to lose efficacy produces.Fig. 4 has shown the test waveform of employing sub-threshold storage array of the present invention under the test condition identical with Fig. 3 (b).Because the driving force that strengthens, Ion/Ioff increases, and can read correct logical message (196.4mV) from bit line BL.That is to say and do not adopt when of the present invention, the information of sub-threshold memory cell array readout error under the condition of 8 storage unit of every bit lines series connection, and after adopting the present invention, memory cell array under the same conditions can be read correct information.Test result shows in addition, and sub-threshold memory cell array still can work under the condition of 16 storage unit of every bit lines series connection behind employing the present invention.Namely adopt memory cell array of the present invention can support more storage unit, adopt the capacity of sub-threshold memory cell array of the present invention and density to be enhanced.

The present invention compares with conventional sense amplifier and need not extra control signal, cell density is less, because same bit line can support more storage unit, so the lifting of adopting memory cell array of the present invention can obtain larger capacity and obtain performance at global density.

Claims (1)

1. one kind in order to strengthen the subthreshold value sensitive amplifying circuit of memory cell array capacity and density, it is characterized in that: be provided with five PMOS pipe P1～P5 and six NMOS pipe N1～N6, totally 11 transistors, wherein, the source termination power of PMOS pipe P1, the drain terminal of PMOS pipe P1 is connected jointly with the source of PMOS pipe P4 and PMOS pipe P5; The source termination power of PMOS pipe P2, the drain terminal of PMOS pipe P2 jointly is connected in a bit with the drain terminal that grid end and the NMOS of PMOS pipe P4 manage N1 and this point is connected bit line BL; The source termination power of PMOS pipe P3, the drain terminal of PMOS pipe P3 jointly is connected in a bit with the drain terminal that grid end and the NMOS of PMOS pipe P5 manage N2 and this point is connected the non-NBL of bit line; The grid end of NMOS pipe N3 jointly is connected in a bit with the grid end that grid end and the PMOS of NMOS pipe N4 manage P1 and this puts the Enable Pin that is connected this amplifying circuit

The source of the source of NMOS pipe N3 and NMOS pipe N4 all is connected with ground, the source of the source of NMOS pipe N1 and NMOS pipe N2 all is connected with ground, the source of the source of NMOS pipe N5 and NMOS pipe N6 all is connected with ground, and the grid end of the drain terminal of the grid end of PMOS pipe P2, PMOS pipe P4, the drain terminal of NMOS pipe N3, NMOS pipe N1, the drain terminal of NMOS pipe N5 and the grid end of NMOS pipe N6 connect jointly; The drain terminal of the grid end of the grid end of the drain terminal of the drain terminal of the grid end of PMOS pipe P3, PMOS pipe P5, NMOS pipe N4, NMOS pipe N2, NMOS pipe N5 and NMOS pipe N6 connects jointly.

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