CN101677067B - Copper core layer multilayer packaging substrate manufacturing method - Google Patents
Copper core layer multilayer packaging substrate manufacturing method Download PDFInfo
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- CN101677067B CN101677067B CN200810304555XA CN200810304555A CN101677067B CN 101677067 B CN101677067 B CN 101677067B CN 200810304555X A CN200810304555X A CN 200810304555XA CN 200810304555 A CN200810304555 A CN 200810304555A CN 101677067 B CN101677067 B CN 101677067B
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Abstract
A copper core layer multilayer packaging substrate manufacturing method is a single surface and multilayer packaging substrate for starting manufacturing by taking the copper core substrate as a base. The structure comprises a thick copper plate with high rigidity, and one surface of the thick copper plate has a build-up circuit, while the other surface has a ball side pattern barrier. The mode for connecting its crystal providing side and ball side with various build-up circuits is that they are communicated by a plurality of electroplating blind holes and buried holes. Therefore, The inventive packaging substrate is characterized by including a high-density build-up circuits for providing the coiling required by connecting of electronic assembly, and simultaneously using a thick copper plate to provide enough rigidity to make the packaging process to be more easier. Therefore, the multilayer packaging substrate manufactured by the invention can form copper core layer multilayer packaging substrate supported by a copper core substrate, and can effectively improve plate bending problem of ultrathin nuclear layer substrate and simplify the making flow of conventional build-up circuit board, thereby achieving the object of improving the reliability when the packaging body is jointed to the substrate.
Description
Technical field:
The present invention relates to a kind of manufacture method of copper-core layer multi-layer encapsulation substrate, refer to that especially a kind of is the basis single face that begins to make, the manufacture method of layer multilayer packaging substrate with copper nuclear substrate.
Background technology:
In the making of general layer multilayer packaging substrate; Its production method system is usually begun by a core substrate; Through modes such as boring, plated metal, consent and two-sided circuit making, accomplish the inner layer core plate of a two-sided structure, increase a layer processing procedure via a circuit more afterwards and accomplish a layer multilayer packaging substrate.Shown in figure 22, it is to be one the generalized section of stratum nucleare base plate for packaging to be arranged.At first; Prepare a core substrate 60, wherein, this core substrate 60 is made up of the sandwich layer 601 of a tool predetermined thickness and 602 of line layers being formed at these sandwich layer 601 surfaces; And be formed with several in this sandwich layer 601 and electroplate via 603, can use the line layer 602 that connects these sandwich layer 601 surfaces.
Then as Figure 23～and shown in Figure 26, these core substrate 60 enforcement circuits are increased a layer processing procedure.At first, form one first dielectric layers 61, and these first dielectric layer, 61 surfaces are formed with several first openings 62, to expose this line layer 602 in this core substrate 60 surfaces; Afterwards; Form a crystal seed layer 63 with modes such as electroless-plating or plating in the surface that this first dielectric layer 61 exposes; And on this crystal seed layer 63, form patterning resistance layer 64, and have several second openings 65 in its patterning resistance layer 64, form the crystal seed layer 63 of patterned circuit with exposed portions serve; Then; Utilize the mode of electroplating in this second opening 65, to form one first patterned line layer 66 and several conductive blind holes 67; And make its first patterned line layer 66 be able to see through these several conductive blind holes 67 to do with the line layer 602 of this core substrate 60 and electrically conduct; And then remove this patterning resistance layer 64 and etching, form one first circuit layer reinforced structure 6a after waiting to accomplish.Likewise; This genealogy of law can be transported the second circuit layer reinforced structure 6b that forms one second dielectric layer 68 and one second patterned line layer 69 in a like fashion again in the outermost surface of this first circuit layer reinforced structure 6a, forms a layer multilayer packaging substrate progressively to increase a layer mode.Yet this kind manufacture method has that wiring density is low, the number of plies reaches shortcomings such as flow process complicacy more.
In addition, the method for thick copper metallic plate when core material of utilizing also arranged, can after accomplishing an inner layer core plate, increase layer processing procedure to accomplish a layer multilayer packaging substrate via a circuit again through modes such as etching and consents.Like Figure 27～shown in Figure 29, it is the generalized section that the stratum nucleare base plate for packaging is arranged for another.At first, prepare a core substrate 70, the individual layer copper core substrate 70 that this core substrate 70 utilizes etching and filling holes with resin 701 and modes such as boring and electroplating ventilating hole 702 to form by the metal level of a tool predetermined thickness; Afterwards, utilize above-mentioned circuit to increase a layer mode, form one first dielectric layer 71 and one first patterned line layer 72, constitute a tool first circuit layer reinforced structure 7a by this in these core substrate 70 surfaces.This method is also identical with said method; System can utilize a circuit to increase layer mode again and form one second dielectric layer 73 and one second patterned line layer 74 in the outermost surface of this first circuit layer reinforced structure 7a; Constitute a tool second circuit layer reinforced structure 7b by this, form a layer multilayer packaging substrate progressively to increase a layer mode.Yet this kind manufacture method not only its copper core substrate making is difficult for, and also identical with said method, has wiring density and hangs down shortcomings such as reaching the flow process complicacy.So, general can't meet user required when reality is used with the person.
Summary of the invention:
Technical problem to be solved by this invention is; Deficiency to prior art; A kind of copper-core layer multi-layer encapsulation substrate that can form tool copper nuclear base plate supports according to actual demand is provided; And can effectively reach and improve ultra-thin stratum nucleare substrate plate prying problem, and simplify traditional build-up circuit board and make flow process, and then reach the manufacture method of the copper-core layer multi-layer encapsulation substrate of the reliability (Board Level Reliability) when improving the packaging body bonded substrate.
For solving the problems of the technologies described above, the technical scheme that the present invention adopted is: a kind of manufacture method of copper-core layer multi-layer encapsulation substrate comprises the following step at least:
(A) bronze medal nuclear substrate is provided;
(B) respectively at forming one first resistance layer on this copper nuclear surface of first base, and in second of this copper nuclear substrate go up form one cover shape fully the second resistance layer, in wherein, this first resistance layer is gone up and is formed several first openings;
(C) form several first grooves in several first opening belows;
(D) remove this first resistance layer and this second resistance layer;
(E) in several first grooves, form one first electrical barrier layer;
(F) on this copper nuclear surface of first base and this first electrical barrier layer, form one first dielectric layer and a first metal layer;
(G) on this first metal layer and this first dielectric layer, form several second openings, and appear first of the copper nuclear substrate of part;
(H) form one second metal level in several second openings and on this first metal layer;
(I) respectively at forming one the 3rd resistance layer on this second metal level, and in second of this copper nuclear substrate go up form one cover shape fully the 4th resistance layer, in wherein, the 3rd resistance layer is gone up and is formed several the 3rd openings;
(J) remove second metal level and the first metal layer of the 3rd opening below, and form one first line layer;
(K) remove the 3rd resistance layer and the 4th resistance layer, so far, accomplish one and have the individual layer build-up circuit substrate that copper nuclear base plate supports and electric property connect, and select directly to carry out step (L) or step (M);
(L) on this individual layer build-up circuit substrate, carrying out putting brilliant side and ball side line layer makes; In wherein, form one first welding resisting layer on this first line layer surface, and on this first welding resisting layer, form several the 4th openings; To appear the part of this first line layer as electric connection pad; Then go up and form one the 5th resistance layer, and on the 5th resistance layer, form several the 5th openings, afterwards again respectively at forming one first barrier layer in several the 4th openings in second of this copper nuclear substrate; And in the 5th opening, form one second barrier layer, remove the 5th resistance layer at last; And
(M) on this individual layer build-up circuit substrate, carry out a circuit layer reinforced structure and make,, form one second dielectric layer on this first line layer surface in wherein; And on this second dielectric layer, form several the 6th openings,, then form one first crystal seed layer in this second dielectric layer and several the 6th open surfaces to appear first line layer of part; Again respectively at forming one the 6th resistance layer on this first crystal seed layer; And in second of this copper nuclear substrate go up form one cover shape fully the 7th resistance layer, and go up in the 6th resistance layer and to form several minion mouths, to appear first crystal seed layer of part; Form one the 3rd metal level on first crystal seed layer that in this minion mouth, has appeared afterwards; Remove the 6th resistance layer, the 7th resistance layer and this first crystal seed layer at last, on this second dielectric layer, to form one second line layer, so far; Accomplish one and have the double-deck build-up circuit substrate that copper is examined base plate supports and electric property connection; And continue this step (M) and increase the circuit layer reinforced structure, form the more base plate for packaging of multilayer of tool, also or directly put brilliant side and the making of ball side line layer to this step (L).
Compared with prior art; The beneficial effect that the present invention had is: the present invention is that the basis begins to make single face, layer multilayer packaging substrate with copper nuclear substrate; Its structure comprises the thick copper coin of the high rigid support of a tool; And a cording build-up circuit of this thick copper coin, another side are then had a ball side pattern barrier layer, and each build-up circuit and put brilliant side and ball side ways of connecting for electroplating blind holes, the conducting of buried via hole institute with several.The present invention simultaneously has the required coiling when linking to each other so that electronic building brick to be provided of high density build-up circuit, simultaneously, and provides enough rigidity to make the encapsulation procedure can be more simple and easy with thick copper coin.So just can form the copper-core layer multi-layer encapsulation substrate of tool copper nuclear base plate supports according to actual demand; And can effectively reach and improve ultra-thin stratum nucleare substrate plate prying problem, and simplify traditional build-up circuit board and make flow process, and then reach the reliability (Board Level Reliability) when improving the packaging body bonded substrate.
Description of drawings:
Fig. 1 is a making schematic flow sheet of the present invention.
Fig. 2 is layer multilayer packaging substrate () generalized section of one embodiment of the invention.
Fig. 3 is layer multilayer packaging substrate (two) generalized section of one embodiment of the invention.
Fig. 4 is layer multilayer packaging substrate (three) generalized section of one embodiment of the invention.
Fig. 5 is layer multilayer packaging substrate (four) generalized section of one embodiment of the invention.
Fig. 6 is layer multilayer packaging substrate (five) generalized section of one embodiment of the invention.
Fig. 7 is layer multilayer packaging substrate (six) generalized section of one embodiment of the invention.
Fig. 8 is layer multilayer packaging substrate (seven) generalized section of one embodiment of the invention.
Fig. 9 is layer multilayer packaging substrate (eight) generalized section of one embodiment of the invention.
Figure 10 is layer multilayer packaging substrate (nine) generalized section of one embodiment of the invention.
Figure 11 is layer multilayer packaging substrate (ten) generalized section of one embodiment of the invention.
Figure 12 is layer multilayer packaging substrate (11) generalized section of one embodiment of the invention.
Figure 13 is layer multilayer packaging substrate (12) generalized section of one embodiment of the invention.
Figure 14 is layer multilayer packaging substrate (13) generalized section of one embodiment of the invention.
Figure 15 is layer multilayer packaging substrate (14) generalized section of one embodiment of the invention.
Figure 16 is layer multilayer packaging substrate (15) generalized section of one embodiment of the invention.
Figure 17 is layer multilayer packaging substrate (16) generalized section of one embodiment of the invention.
Figure 18 is layer multilayer packaging substrate (17) generalized section of one embodiment of the invention.
Figure 19 is layer multilayer packaging substrate (18) generalized section of one embodiment of the invention.
Figure 20 is layer multilayer packaging substrate (19) generalized section of one embodiment of the invention.
Figure 21 is layer multilayer packaging substrate (20) generalized section of one embodiment of the invention.
Figure 22 system is with the generalized section that the stratum nucleare base plate for packaging is arranged.
Figure 23 system increases layer (one) generalized section with the enforcement circuit.
Figure 24 system increases layer (two) generalized section with the enforcement circuit.
Figure 25 system increases layer (three) generalized section with the enforcement circuit.
Figure 26 system increases layer (four) generalized section with the enforcement circuit.
Figure 27 is that another is with the generalized section that the stratum nucleare base plate for packaging is arranged.
Figure 28 is another first circuit layer reinforced structure generalized section of usefulness.
Figure 29 is another the second road layer reinforced structure generalized section of usefulness.
Label declaration:
(part of the present invention)
Step (A)～(M) 11～23 individual layer build-up circuit substrates 3
Copper nuclear substrate 30 first and second resistance layers 31,32
First opening, 33 first electrical barrier layers 34
First dielectric layer, 35 the first metal layers 36
Second opening, 37 second metal levels 38
39,40 layers of build-up circuit substrate 4 of third and fourth resistance layer
The 3rd opening 41 first line layers 42
Second dielectric layer 43 the 4th opening 44
First crystal seed layer 45 the 5th, six resistance layers 46,47
The 5th opening 48 the 3rd metal level 49
Second line layer, 50 first welding resisting layers 51
The 6th opening 52 the 7th resistance layer 53
Minion mouth 54 first and second barrier layers 55,56
(commonly using part)
First and second circuit layer reinforced structure 6a, 6b core substrate 60
Electroplate via 603 first dielectric layers 61
First opening, 62 these crystal seed layers 63
First patterned line layer, 66 conductive blind holes 67
Second dielectric layer, 68 second patterned line layer 69
Two circuit layer reinforced structure 7a, 7b core substrate 70
Filling holes with resin 701 electroplating ventilating holes 702
First dielectric layer, 71 first patterned line layer 72
Second dielectric layer, 73 second patterned line layer 74
Embodiment:
Seeing also shown in Figure 1ly, is to be making schematic flow sheet of the present invention.As shown in the figure: the present invention is a kind of manufacture method of copper-core layer multi-layer encapsulation substrate, and it comprises the following steps: at least
(A) copper nuclear substrate 11 is provided: bronze medal nuclear substrate is provided;
(B) form first and second resistance layer and first opening 12: respectively at forming one first resistance layer on this copper nuclear surface of first base; And in second of this copper nuclear substrate go up form one cover shape fully the second resistance layer, and on this first resistance layer, form several first openings with exposure and visualization way;
(C) form first groove 13: form several first grooves in several first opening belows with etching mode;
(D) remove first and second resistance layer 14: remove this first resistance layer and this second resistance layer to peel off mode;
(E) form the first electrical barrier layer 15: in several first grooves, form one first electrical barrier layer with direct pressing or mode of printing;
(F) form first dielectric layer and the first metal layer 16: direct pressing one first dielectric layer and a first metal layer on this copper nuclear surface of first base and this first electrical barrier layer; Also or earlier take to fit behind this first dielectric layer; Form this first metal layer again; Wherein, this first dielectric layer can carry out the formation of pressing or mode of printing simultaneously with this first electrical barrier layer;
(G) form second opening 17: the mode with laser drill forms several second openings on this first metal layer and this first dielectric layer; And the copper that appears part is examined first of substrate; Wherein, After several second openings can be done out earlier copper window (Conformal Mask), the mode via laser drill formed again, also or with the mode of direct laser drill (LASERDirect) formed;
(H) form second metal level 18: the mode with electroless-plating or plating forms one second metal level in several second openings and on this first metal layer;
(I) form third and fourth resistance layer and the 3rd opening 19: respectively at forming one the 3rd resistance layer on this second metal level; And in second of this copper nuclear substrate go up form one cover shape fully the 4th resistance layer, and on the 3rd resistance layer, form several the 3rd openings with exposure and visualization way;
(J) form first line layer 20: remove second metal level and the first metal layer of the 3rd opening below with etching mode, and form one first line layer;
(K) accomplish individual layer build-up circuit substrate 21: remove the 3rd resistance layer and the 4th resistance layer to peel off mode with copper nuclear base plate supports and electric property connection.So far, accomplish one and have the individual layer build-up circuit substrate of copper nuclear base plate supports and electric property connection, and can select directly to carry out step (L) or step (M);
(L) put brilliant side and ball side line layer and make 22: the making of on this individual layer build-up circuit substrate, carrying out putting brilliant side and ball side line layer; In wherein; First welding resisting layer of using in this first line layer surface-coated one deck tool insulation protection; And on this first welding resisting layer, forms several the 4th openings with exposure and visualization way, appearing the part of this first line layer, then go up and form one the 5th resistance layer in second of this copper nuclear substrate as electric connection pad; And on the 5th resistance layer, form several the 5th openings; Afterwards again respectively at forming one first barrier layer in several the 4th openings, and in the 5th opening, form one second barrier layer, remove the 5th resistance layer to peel off mode at last.So far, accomplish with the patterning but still fully electrically ball side line layer of short circuit of the brilliant side line layer of putting of a complete patternization, wherein, this first and second barrier layer can be in electronickelling gold, electroless nickel plating gold, electrosilvering or the electrotinning and selects one of which; And
(M) carry out the circuit layer reinforced structure and make 23: on this individual layer build-up circuit substrate, carry out the making of a circuit layer reinforced structure; In wherein; Form one second dielectric layer at this first line layer and this first dielectric layer surface; And on this second dielectric layer, form several the 6th openings with the laser drill mode, to appear first line layer of part, then the mode with electroless-plating or plating forms one first crystal seed layer in this second dielectric layer and several the 6th open surfaces; Again respectively at forming one the 6th resistance layer on this first crystal seed layer; And go up in second of this copper nuclear substrate and to form one and cover the 7th resistance layer of shape fully, and utilize exposure and visualization way to go up in the 6th resistance layer to form several minion mouths, to appear first crystal seed layer of part; Form one the 3rd metal level on first crystal seed layer that in this minion mouth, has appeared with the mode of electroless-plating or plating more afterwards; Remove the 6th resistance layer and the 7th resistance layer to peel off mode at last, and remove this first crystal seed layer, on this second dielectric layer, to form one second line layer with etched mode.So far, increase one deck circuit layer reinforced structure again again, accomplish one and have the double-deck build-up circuit substrate that copper is examined base plate supports and electric property connection.And can continue this step (M) increase circuit layer reinforced structure; Form the more base plate for packaging of multilayer of tool; Also or directly put brilliant side and ball side line layer is made to this step (L), wherein, after several the 6th openings can be done out earlier the copper window; Form via the laser drill mode again, also or with direct laser drill mode form.
In wherein, the dry film that above-mentioned these the first～seven resistance series of strata are done with applying, printing or rotary coating or the high sensing optical activity photoresistance of wet film; This first electrical barrier layer and this first and second dielectric layer can be anti-welding green lacquer, epoxy resins insulation film (AjinomotoBuild-up Film; ABF), benzocyclobutene (Benzocyclo-buthene; BCB), two Maleimides-triazine resin (Bismaleimide Triazine; BT), epoxy resin board (FR4, FR5), polyimides (Polyimide; PI), polytetrafluoroethylene (Poly (tetra-floroethylene), PTFE) or epoxy resin and glass fiber form one.
See also Fig. 2～shown in Figure 21, be respectively layer multilayer packaging substrate (19) generalized section, and layer multilayer packaging substrate (20) generalized section of one embodiment of the invention of layer multilayer packaging substrate (18) generalized section, one embodiment of the invention of layer multilayer packaging substrate (17) generalized section, one embodiment of the invention of layer multilayer packaging substrate (16) generalized section, one embodiment of the invention of layer multilayer packaging substrate (15) generalized section, one embodiment of the invention of layer multilayer packaging substrate (14) generalized section, one embodiment of the invention of layer multilayer packaging substrate (13) generalized section, one embodiment of the invention of layer multilayer packaging substrate (12) generalized section, one embodiment of the invention of layer multilayer packaging substrate (11) generalized section, one embodiment of the invention of layer multilayer packaging substrate (ten) generalized section, one embodiment of the invention of layer multilayer packaging substrate (nine) generalized section, one embodiment of the invention of layer multilayer packaging substrate (eight) generalized section, one embodiment of the invention of layer multilayer packaging substrate (seven) generalized section, one embodiment of the invention of layer multilayer packaging substrate (six) generalized section, one embodiment of the invention of layer multilayer packaging substrate (five) generalized section, one embodiment of the invention of layer multilayer packaging substrate (four) generalized section, one embodiment of the invention of layer multilayer packaging substrate (three) generalized section, one embodiment of the invention of layer multilayer packaging substrate (two) generalized section, one embodiment of the invention of layer multilayer packaging substrate () section generalized section, one embodiment of the invention of one embodiment of the invention.As shown in the figure: the present invention is in a preferred embodiment; One bronze medal nuclear substrate 30 is provided earlier; And first and second resistance layer 31,32 of the high photosensitive macromolecular material of fitting separately on first and second face respectively at this copper nuclear substrate 30; And on this first resistance layer 31, form several first openings 33 with the exposure and the mode of developing, appearing 30 first of copper nuclear substrates it under, second resistance on its second layers 32 is then for covering shape fully.Afterwards, make the groove 311 of half erosion again with etched mode, wherein, this copper nuclear substrate 30 is one not conform to the thick copper coin of dielectric layer material; This first and second resistance layer 31,32 is the dry film photoresist layer.
Then, remove this first and second resistance layer, have the copper nuclear substrate 30 of first of pin with formation.Print one first electrical barrier layer 34 afterwards in this groove 311; And on first of this copper nuclear substrate 30 pressing one first dielectric layer 35 and a first metal layer 36; Mode with laser drill forms several second openings 37 on this first metal layer 36 and this first dielectric layer 35 again; Mode with electroless-plating or plating forms one second metal level 38 in several second openings 37 and this first metal layer 36 surfaces afterwards; Wherein, this first and second metal level 36,38 is all copper, and these second metal level, 38 conducts are used with the electric connection of 30 first of this copper nuclear substrates.
Then, respectively at the 3rd resistance layer 39 of the high photosensitive macromolecular material of fitting on this second metal level 38, and in second the 4th resistance layer 40 of going up the high photosensitive macromolecular material of fitting of this copper nuclear substrate 30.And mode several the 3rd openings 41 of formation on the 3rd resistance layer 39 to make public and to develop, to appear second metal level 38 under it.Remove first and second metal level under the 3rd opening 41 with etching mode afterwards,, remove this third and fourth resistance layer at last to form one first line layer 42.So far, accomplish the individual layer build-up circuit substrate 3 that has patterned circuit and be connected with first of the pin of this copper nuclear substrate 30.
Then, in preferred embodiment of the present invention, be the making of in advance carrying out the circuit layer reinforced structure.At first the pressing unification is second dielectric layer 43 of epoxy resins insulation membrane material on this first line layer 42 and first dielectric layer 35; Afterwards; Mode with laser drill forms several the 4th openings 44 on this second dielectric layer 43; Appearing first line layer 42 under it, and on this second dielectric layer 43 and the 4th opening 44 surfaces the mode with electroless-plating or plating forms one first crystal seed layer 45.Hinder layer 46 respectively at the 5th of the high photosensitive macromolecular material of fitting on this first crystal seed layer 45 afterwards; And in second the 6th resistance layer 47 of going up the high photosensitive macromolecular material of fitting of this copper nuclear substrate 30; Then utilize exposure and visualization way on the 5th resistance layer 46, to form several the 5th openings 48; And then in several the 5th openings 48 electroless-plating or electroplate one the 3rd metal level 49; Remove the 5th, six resistance layers at last, and remove this first crystal seed layer with etching mode again, to form one second line layer 50.So far, increase the circuit layer reinforced structure of one deck again again, accomplish one and have the double-deck build-up circuit substrate 4 that copper nuclear base plate supports and electric property connect, in wherein, this first crystal seed layer and the 3rd metal level are all metallic copper.
Afterwards, put the making of brilliant side and ball side line layer.First welding resisting layer of at first using in these second line layer, 50 surface-coated one deck insulation protections 51, the mode with exposure and development forms several the 6th openings 52 on this first welding resisting layer 51 then, to appear the circuit layer reinforced structure as electric connection pad.Then; Second the 7th resistance layer 53 of going up the high photosensitive macromolecular material of fitting in this copper nuclear substrate 30; And,, and on several minion mouths 54, form one second barrier layer 56 again respectively at formation one first barrier layer 55 on several the 6th openings 52 with exposure and visualization way several minion mouths 54 of formation on the 7th resistance layer 53; At last, remove the 7th resistance layer.So far, accomplish the layer multilayer packaging substrate 5 that a tool copper stratum nucleare supports, wherein, this first and second barrier layer 55,56 is all nickel-gold layer.
From the above, the present invention system is the basis with copper nuclear substrate, the single face that begins to make, layer multilayer packaging substrate, and its structure comprises the thick copper coin of the high rigid support of a tool, and a mask build-up circuit of this thick copper coin, another side is then had a ball side pattern barrier layer.In wherein, each build-up circuit and put brilliant side and blind holes, the conducting of buried via hole institute are electroplated with several by ball side ways of connecting system.Therefore, the characteristic of base plate for packaging of the present invention ties up in having the required coiling when linking to each other so that electronic building brick to be provided of high density build-up circuit, simultaneously, and provides enough rigidity to make the encapsulation procedure can be more simple and easy with thick copper coin.Though each circuit is dead short circuit on electrically before encapsulation procedure is accomplished, ball side pattern barrier layer then capable of using after encapsulation procedure is accomplished removes thick copper coin partly with etched mode, and then can make electrical independence and form the column pin of tool protective effect.By this; Use the layer multilayer packaging substrate of the highdensity build-up circuit base plate for packaging of tool of the present invention method manufacturing; Can form the copper-core layer multi-layer encapsulation substrate of tool copper nuclear base plate supports according to actual demand; And can effectively reach and improve ultra-thin stratum nucleare substrate plate prying problem, and simplify traditional build-up circuit board and make flow process, and then reach the purpose of the reliability (Board Level Reliability) when improving the packaging body bonded substrate.
In sum; The present invention is a kind of manufacture method of copper-core layer multi-layer encapsulation substrate, can effectively improve the various shortcoming of usefulness, has the required coiling when linking to each other so that electronic building brick to be provided of high density build-up circuit; Provide enough rigidity to make the encapsulation procedure can be more simple and easy simultaneously, and with thick copper coin.By this; Use the layer multilayer packaging substrate of manufacturing of the present invention; Can form the copper-core layer multi-layer encapsulation substrate of tool copper nuclear base plate supports according to actual demand; And can effectively reach and improve ultra-thin stratum nucleare substrate plate prying problem, and simplify traditional build-up circuit board and make flow process, reaching the purpose of the reliability (Board LevelReliability) when improving the packaging body bonded substrate, so make generation of the present invention can more progressive, more practical, more meet user's institute must; Really met the important document of application for a patent for invention, the whence proposes patent application in accordance with the law.
Only the above is merely preferred embodiment of the present invention, when not limiting practical range of the present invention with this; So all simple equivalent of doing according to claims of the present invention and description change and modify, all should still belong in the scope that patent of the present invention contains.
Claims (13)
1. the manufacture method of a copper-core layer multi-layer encapsulation substrate is characterized in that comprising at least the following step:
(A) bronze medal nuclear substrate is provided;
(B) respectively at forming one first resistance layer on this copper nuclear surface of first base, and in second of this copper nuclear substrate go up form one cover shape fully the second resistance layer, in wherein, this first resistance layer is gone up and is formed several first openings;
(C) form several first grooves in several first opening belows;
(D) remove this first resistance layer and this second resistance layer;
(E) in several first grooves, form one first electrical barrier layer;
(F) on this copper nuclear surface of first base and this first electrical barrier layer, form one first dielectric layer and a first metal layer;
(G) on this first metal layer and this first dielectric layer, form several second openings, and appear first of the copper nuclear substrate of part; (H) form one second metal level in several second openings and on this first metal layer;
(I) respectively at forming one the 3rd resistance layer on this second metal level, and in second of this copper nuclear substrate go up form one cover shape fully the 4th resistance layer, in wherein, the 3rd resistance layer is gone up and is formed several the 3rd openings;
(J) remove second metal level and the first metal layer of the 3rd opening below, and form one first line layer;
(K) remove the 3rd resistance layer and the 4th resistance layer, so far, accomplish one and have the individual layer build-up circuit substrate that copper nuclear base plate supports and electric property connect, and select directly to carry out step (L) or step (M);
(L) on this individual layer build-up circuit substrate, carrying out putting brilliant side and ball side line layer makes; In wherein, form one first welding resisting layer on this first line layer surface, and on this first welding resisting layer, form several the 4th openings; To appear the part of this first line layer as electric connection pad; Then go up and form one the 5th resistance layer, and on the 5th resistance layer, form several the 5th openings, afterwards again respectively at forming one first barrier layer in several the 4th openings in second of this copper nuclear substrate; And in the 5th opening, form one second barrier layer, remove the 5th resistance layer at last; And
(M) on this individual layer build-up circuit substrate, carry out a circuit layer reinforced structure and make,, form one second dielectric layer on this first line layer surface in wherein; And on this second dielectric layer, form several the 6th openings,, then form one first crystal seed layer in this second dielectric layer and several the 6th open surfaces to appear first line layer of part; Again respectively at forming one the 6th resistance layer on this first crystal seed layer; And in second of this copper nuclear substrate go up form one cover shape fully the 7th resistance layer, and go up in the 6th resistance layer and to form several minion mouths, to appear first crystal seed layer of part; Form one the 3rd metal level on first crystal seed layer that in this minion mouth, has appeared afterwards; Remove the 6th resistance layer, the 7th resistance layer and this first crystal seed layer at last, on this second dielectric layer, to form one second line layer, so far; Accomplish one and have the double-deck build-up circuit substrate that copper is examined base plate supports and electric property connection; And continue this step (M) and increase the circuit layer reinforced structure, form the more base plate for packaging of multilayer of tool, also or directly put brilliant side and the making of ball side line layer to this step (L).
2. the manufacture method of copper-core layer multi-layer encapsulation substrate according to claim 1 is characterized in that, this copper nuclear substrate is one not contain the copper coin of dielectric layer material.
3. the manufacture method of copper-core layer multi-layer encapsulation substrate according to claim 1 is characterized in that, this first～seven resistance layer is the dry film of doing with applying, printing or rotary coating or the high sensing optical activity photoresistance of wet film.
4. the manufacture method of copper-core layer multi-layer encapsulation substrate according to claim 1 is characterized in that, several first and third, five and the minion mouth form with the exposure and the mode of developing.
5. the manufacture method of copper-core layer multi-layer encapsulation substrate according to claim 1 is characterized in that, this step (C) forms several first grooves, this step (J), and to remove the method that this first and second metal level and this step (M) remove this first crystal seed layer be etching.
6. the manufacture method of copper-core layer multi-layer encapsulation substrate according to claim 1 is characterized in that, the method that removes of this first～seven resistance layer is for peeling off.
7. the manufacture method of copper-core layer multi-layer encapsulation substrate according to claim 1 is characterized in that, this first electrical barrier layer forms with the mode of direct pressing or printing.
8. the manufacture method of copper-core layer multi-layer encapsulation substrate according to claim 1; It is characterized in that, this first electrical barrier layer and this first and second dielectric layer be anti-welding green lacquer, epoxy resins insulation film, benzocyclobutene, two Maleimide-triazine resin, epoxy resin board, polyimides, polytetrafluoroethylene, epoxy resin or glass fiber one of them.
9. the manufacture method of copper-core layer multi-layer encapsulation substrate according to claim 1 is characterized in that, the mode that this step (E) first electrical barrier layer and step (F) first dielectric layer carry out pressing or printing simultaneously forms.
10. the manufacture method of copper-core layer multi-layer encapsulation substrate according to claim 1 is characterized in that, this step (F) or behind this first dielectric layer of taking to fit, forms this first metal layer with this first dielectric layer of direct pressing and this first metal layer on it again.
11. the manufacture method of copper-core layer multi-layer encapsulation substrate according to claim 1 is characterized in that, several second, six openings are that the mode via laser drill forms again after doing out earlier the copper window, also or with the mode of direct laser drill form.
12. the manufacture method of copper-core layer multi-layer encapsulation substrate according to claim 1 is characterized in that, the generation type of this second and third metal level and this first crystal seed layer is electroless-plating or plating.
13. the manufacture method of copper-core layer multi-layer encapsulation substrate according to claim 1 is characterized in that, this first and second barrier layer is that electronickelling gold, electroless nickel plating are golden, one of in electrosilvering or the electrotinning.
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| CN200810304555XA CN101677067B (en) | 2008-09-19 | 2008-09-19 | Copper core layer multilayer packaging substrate manufacturing method |
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| CN200810304555XA CN101677067B (en) | 2008-09-19 | 2008-09-19 | Copper core layer multilayer packaging substrate manufacturing method |
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| CN102378502B (en) * | 2010-08-13 | 2013-11-27 | 欣兴电子股份有限公司 | Circuit board and manufacturing method thereof |
| CN103917049A (en) * | 2013-11-22 | 2014-07-09 | 大连太平洋电子有限公司 | Laser drilling plate machining method adopting secondary outer-layer core material for reducing copper |
| CN105304602A (en) * | 2014-07-18 | 2016-02-03 | 日月光半导体制造股份有限公司 | Semiconductor substrate, semiconductor package structure and manufacturing method thereof |
| CN110418508B (en) * | 2019-07-15 | 2021-08-31 | 宁波华远电子科技有限公司 | Manufacturing method of copper substrate circuit board |
| CN111432577B (en) * | 2020-03-03 | 2023-02-17 | 宁波华远电子科技有限公司 | Photosensitive polyimide addition and subtraction circuit process of ultrathin rigid-flex board |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1379616A (en) * | 2001-04-02 | 2002-11-13 | 日东电工株式会社 | Multi layer circuit board and its manufacturing method |
| CN1484482A (en) * | 2002-09-17 | 2004-03-24 | �ձ�������ҵ��ʽ���� | Multi-layer wire distributed substrate and mfg method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1379616A (en) * | 2001-04-02 | 2002-11-13 | 日东电工株式会社 | Multi layer circuit board and its manufacturing method |
| CN1484482A (en) * | 2002-09-17 | 2004-03-24 | �ձ�������ҵ��ʽ���� | Multi-layer wire distributed substrate and mfg method |
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