CN101635271B

CN101635271B - Fabricating method of shallow trench isolation structure

Info

Publication number: CN101635271B
Application number: CN2009100527979A
Authority: CN
Inventors: 肖海波
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2009-06-09
Filing date: 2009-06-09
Publication date: 2012-06-20
Anticipated expiration: 2029-06-09
Also published as: CN101635271A

Abstract

The invention provides a fabricating method of a shallow trench isolation structure. The fabricating method comprises the following steps: forming a shallow trench on a semiconductor substrate; growing lining oxide layers on side walls and bottom of the shallow trench; growing insulation medium in the shallow trench and on a semiconductor substrate; carrying out grinding treatment and wet etching treatment on the surface of the insulation medium; growing a protection oxide layer around the insulation medium in the shallow trench; carrying out annealing treatment; removing the protection oxide layer on the semiconductor substrate by a dry etching method; and precipitating a sacrificial oxide layer on the semiconductor substrate at two sides of the insulation medium in the shallow trench. The Fabricating method can help reduce etched insulation medium in trenches, thus reducing current leakage of fabricated devices.

Description

A kind of manufacture method of fleet plough groove isolation structure

Technical field

The invention belongs to a kind of semiconductor technology, relate in particular to a kind of manufacture method of fleet plough groove isolation structure.

Background technology

In integrated circuit flourish today, element downsizing and the integrated trend that is inevitable also are the important topics of all circles' develop actively.When component size is dwindled gradually, integrated level (Integration) improves gradually, and interelement isolation structure also must dwindle, so element separation technical difficulty degree also increases gradually.Element separation helps regional oxidizing process, and (Local Oxidation, the field oxide that LOCOS) forms (Field Oxide) because field oxide is subject to beak (Birds Beak) characteristic of its profile, dwindles its size and have any problem in fact.In view of this; Existing other element separation methods continue to be developed; Wherein (Shallow Trench Isolation STI) is widely used most, especially is applied in the ic manufacturing process of time half micron (Sub-half Micron) with shallow trench isolation.

The manufacturing that shallow trench isolation leaves generally uses silicon nitride as hard mask, on the semiconductor-based end, defines precipitous groove with anisotropy (anisotropy) etching method (dry etching); Again groove is filled up oxide afterwards; Form oxide plug, with as the element fleet plough groove isolation structure, the element below 0.13 micron is for example in the cmos device; Isolation between nmos pass transistor and the PMOS transistor is all adopted shallow trench isolation to leave (STI) technology and is formed; Fig. 1 is a prior art shallow trench isolation method flow chart, may further comprise the steps: step 11: on semiconductor-based bottom material, form said shallow trench, form shallow trench isolation and leave; The general silicon nitride that uses defines precipitous groove as hard mask on the semiconductor-based end; Step 12: in said shallow trench sidewall and bottom grow liners oxide layer; The purpose of grow liners oxide layer is for fear of corner effect (Corner Effect); If the corner of shallow trench is point too; In follow-up manufacture process, when for example utilizing ion inject to form source electrode with drain electrode, this one edge corner will stored charge; Cause abnormal threshold current (Subthreshold Current) in the transistor channels and cause neck knot effect (Kink Effect), make that transistor can't normal operation; Step 13: the dielectric of growing in said shallow trench and at semiconductor-based the end, said dielectric is a silica, generally is to utilize chemical gaseous phase deposition (CVD) in said shallow trench, to insert dielectric; Step 14: carry out annealing in process, annealing temperature is between 1000 ℃ to 1200 ℃; Step 15: grind on the surface to said dielectric, makes the shallow trench flattening surface, and remove the suprabasil dielectric of semiconductor, i.e. oxide layer and silicon nitride layer.After step 15; Can also increase step 16: on the said semiconductor-based bottom material of said dielectric both sides, precipitate sacrificial oxide layer, silicon dioxide for example, this is in follow-up ion implantation process, substrate surface to be battered down; Protected substrate surface; After ion injected, the sacrificial oxide layer that is battered down can be removed through the method for wet etching.When such method is removed the suprabasil dielectric oxide layer of semiconductor in step 15; Can use hydrofluoric acid; Generally remove fully in order to ensure the suprabasil insulating medium layer of semiconductor, the time of etching can be grown a bit a little, like this will be when removing oxide layer; Can etch into the silica in the shallow trench, and after the silica in the shallow trench partly is etched.Fig. 2 is the sketch map of prior art fleet plough groove isolation structure; Dielectric 130 in the groove part is etched; Especially formed bigger depression (divot) at shallow trench with the place that active area joins; The device of processing later on will produce metal silicide in these depression the insides, will be easy to generate the phenomenon of electric leakage.

Summary of the invention

In order to overcome the problem that exists in the prior art, the present invention provides a kind of method that can avoid the oxide in the shallow trench to be etched.

To achieve these goals, the present invention proposes the manufacture method of fleet plough groove isolation structure, comprising: on the semiconductor-based end, form said shallow trench; In said shallow trench sidewall and bottom grow liners oxide layer; The dielectric of growing in said shallow trench and at semiconductor-based the end; Grind on surface to said dielectric, makes the shallow trench flattening surface; Growth protecting oxide layer around the dielectric in said shallow trench; Carry out annealing in process; Use the dry etching method to remove the suprabasil protection oxide layer of semiconductor; Precipitate sacrificial oxide layer on the said semiconductor-based bottom material of the dielectric both sides in said shallow trench.

Optional, adopt the dry etching method on said semiconductor-based bottom material, to form said shallow trench.

Optional, the annealing region of said annealing in process is between 800 ℃ to 1000 ℃.

Optional, said dielectric is a silica.

Optional, said sacrificial oxidation layer material is a silicon dioxide.

The beneficial effect of the manufacture method of fleet plough groove isolation structure of the present invention mainly shows: the layer of protecting oxide layer of growing around the dielectric in shallow trench, carry out after the annealing in process, and remove the protection oxide layer of semiconductor-based ground with the dry etching method.The dry etching method can be controlled the direction of etching and the degree of etching effectively; Thereby form the protection wall in groove side surface; This layer protection wall is because covered the active area at the semiconductor-based end; Effectively guarantee the grooves recess problem that various wet etchings produce in the subsequent technique process, thereby avoided the semiconductor device by using shallow trench to do the situation that electric leakage takes place in isolation.

Description of drawings

Fig. 1 is a prior art shallow trench isolation method flow chart;

Fig. 2 is the sketch map of prior art fleet plough groove isolation structure;

Fig. 3 is the flow chart of the manufacture method of a kind of fleet plough groove isolation structure of the present invention;

Fig. 4 is a fleet plough groove isolation structure sketch map of the present invention.

Embodiment

Below in conjunction with accompanying drawing invention is done further to describe.

Please refer to Fig. 3 and Fig. 4, Fig. 3 is the flow chart of the manufacture method of a kind of fleet plough groove isolation structure of the present invention, and Fig. 4 is a fleet plough groove isolation structure sketch map of the present invention; Can see from Fig. 3; The present invention includes following steps: step 21: on material of the semiconductor-based ends 100, form said shallow trench, the bottom one deck of material of the said semiconductor-based ends 100 is a silicon, the oxide layer of on silicon, growing afterwards; Regrowth silicon nitride layer on oxide layer; The formation shallow trench isolation leaves, and generally uses silicon nitride as hard mask, the precipitous groove of definition on the semiconductor-based end; Step 22: in said shallow trench sidewall and bottom grow liners oxide layer 110; The purpose of grow liners oxide layer 110 is for fear of corner effect (Corner Effect); If the corner of shallow trench is point too; In follow-up manufacture process, when for example utilizing ion inject to form source electrode with drain electrode, this one edge corner will stored charge; Cause abnormal threshold current (Subthreshold Current) in the transistor channels and cause neck knot effect (Kink Effect), make that transistor can't normal operation; Step 23: growth dielectric 130 in said shallow trench and at semiconductor-based the end, said dielectric is a silica, generally is to utilize chemical gaseous phase deposition (CVD) in said shallow trench, to insert dielectric; Step 24: grind on the surface to said dielectric 130, makes the shallow trench flattening surface, is carrying out wet etching treatment afterwards, gets rid of the silicon nitride layer in the said dielectric 130 surface insulation media; Step 25: growth protecting oxide layer 120 around the dielectric in said shallow trench, this layer oxide layer are to form the protection wall in groove side surface after the subsequent step 27; Step 26: carry out annealing in process, annealing temperature is between 800 ℃ to 1000 ℃, and the purpose of annealing is to make the densification of protection oxide layer, simultaneously also in order to reduce the speed of wet etching in the subsequent technique; Step 27: use the dry etching method to remove the protection oxide layer of step 25 growth at the semiconductor-based end 100; The dry etching method can be controlled the direction of etching and the degree of etching effectively; Thereby form the protection wall in groove side surface; This layer protection wall has effectively guaranteed the grooves recess problem that various wet etchings produce in the subsequent technique process because covered the active area at the semiconductor-based end; Step 28: deposition sacrificial oxide layer (not shown) on the said semiconductor-based bottom material of dielectric 130 both sides in said shallow trench; Silicon dioxide for example; This is in follow-up ion implantation process, substrate surface to be battered down, and has protected substrate surface, after ion injects; The sacrificial oxide layer that is battered down can be removed through the method for wet etching.

Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.

Claims

1. the manufacture method of fleet plough groove isolation structure comprises:

S1: on the semiconductor-based end, form said shallow trench;

S2: in said shallow trench sidewall and bottom grow liners oxide layer;

S3: the dielectric of growing in said shallow trench and at semiconductor-based the end;

S4: the surface of said dielectric is ground and wet etching treatment;

S5: growth protecting oxide layer around said dielectric;

S6: carry out annealing in process;

S7: use the dry etching method to remove the suprabasil protection oxide layer of semiconductor;

S8: precipitate sacrificial oxide layer on the said semiconductor-based bottom material of the dielectric both sides in said shallow trench.

2. according to the manufacture method of the said fleet plough groove isolation structure of claim 1, it is characterized in that adopting among the said step S1 dry etching method on said semiconductor-based bottom material, to form said shallow trench.

3. according to the manufacture method of the said fleet plough groove isolation structure of claim 1, the annealing region that it is characterized in that said annealing in process is between 800 ℃ to 1000 ℃.

4. according to the manufacture method of the said fleet plough groove isolation structure of claim 1, it is characterized in that said dielectric is a silica.

5. according to the manufacture method of the said fleet plough groove isolation structure of claim 1, it is characterized in that said sacrificial oxidation layer material is a silicon dioxide.