CN101627438B - Nonvolatile storage device and nonvolatile data recording medium - Google Patents
Nonvolatile storage device and nonvolatile data recording medium Download PDFInfo
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Abstract
The invention provides a nonvolatile storage device and a nonvolatile data recording medium. The conventional ReRAM configuration has a problem that a retention time of the resistance value is short. To improve the retention characteristic, a method of two-step write is performed, and a low write speed exists. The nonvolatile storage device includes: a first write-in circuit which performs a first write-in process by applying a first electric pulse to a nonvolatile storage element so that a resistance value of the nonvolatile storage element changes from a first resistance value to a second resistance value, and by applying a second electric pulse having an inverse polarity as compared to the first electric pulse so that the resistance value changes from the second resistance value to the first resistance value; and a second write-in circuit which performs a second write-in process by applying a third electric pulse to the nonvolatile storage element so that the resistance value of the nonvolatile storage element changes from a third resistance value to a fourth resistance value, and by applying a fourth electric pulse having the same polarity as the third electric pulse so that the resistance value changes from the fourth resistance value to a fifth resistance value.
Description
Technical field
The present invention relates to use Nonvolatile memory devices and the nonvolatile data recording medium of the material storage data that resistance value reversibly changes by applying electric pulse.
Background technology
In recent years, be accompanied by the development of the digital technology of electronic equipment, in order to preserve the data of music, image, information etc., increase gradually for the requirement of big capacity and non-volatile memory storage.As a kind of method that is used for the such requirement of reply, because of the electric pulse resistance change that is applied in, and continue the resistance change layer of this state of maintenance and paid close attention to as the Nonvolatile memory devices of memory element (below, be called ReRAM).This is because it has relatively simple for structure and densification as memory element and easily, easily obtains features such as conformability with in the past semiconductor technology.In such ReRAM, even material and its driving method that the variation repeatability of stable resistance value will be produced well are required to establish, research and development are being carried out actively.
In patent documentation 1, putting down in writing: between first electrode and second electrode, perofskite type oxide is set, form variable resistor element, by between first electrode and second electrode, applying the potential pulse of certain polarity, make at first electrode and the second interelectrode resistance and change, further, with respect to because applying the increase of the accumulation pulse application time that potential pulse produces, the rate of change of resistance value changes by forward is negative.Figure 12 is illustrated in the resistance value of disclosed resistance variation material in the patent documentation 1 and the relation of the integration time of the potential pulse that applies.
In addition, in non-patent literature 1, disclose about using TiO
2Resistance variable element, switched to the method for Unipolar resistance switch unvaryingly by bipolar resistance switch.
Patent documentation 1: TOHKEMY 2006-19444 communique
Non-patent literature 1:Schroeder H.and Jeong, D.S., 2007, Resistiveswitching in a Pt/TiO2/Pt this film stack-a candidate for a non-volatileReRAM, Microelectronic Engineering, vol.84, pp.1982-1985
In the structure of described ReRAM in the past, there is the short problem (the highest about 100 hours) of retention time (retention performance) of resistance value.In order to improve this retention performance, after existence temporarily writes the data corresponding with " 0 ", " 1 " to variable resistor element, carry out be used to make write state complete append the method that writes, but exist if carrying out such two-stage writes, then the slack-off problem of writing speed.
Summary of the invention
The present invention is for the invention that solves described problem, its objective is: provide to make writing speed fast Nonvolatile memory devices and nonvolatile data recording medium that the holding time of data is long.
As described in non-patent literature, if switch to the Unipolar resistance switch, the elongated possibility of retention performance of data is arranged then.But, in the structure of non-patent literature 1, if switch to the Unipolar resistance switch, then can not get back to bipolar resistance switch again, can not carry out high speed motion again.
In order to reach this purpose, Nonvolatile memory devices of the present invention, with used quick action opposite polarity pulse write activity and used write activity and the usefulness of the pulse of the good same polarity of retention performance, by its change action, make high speed motion and keep becoming possibility for a long time.
" with writing of the pulse of the fireballing opposite polarity of usage operation " means, write (bipolar writing) for a kind of non-volatile memory device (ReRAM element), wherein, being used for will be the polarity of the electric pulse (low resistance pulse) that is applied in of low resistance state in the component variation of high resistance state, will be that the polarity of the electric pulse (high resistance pulse) that is applied in of high resistance state is different conditions (bipolar state) in the component variation of low resistance state with being used for.
In bipolar writing, with the low resistance pulse and the high resistance pulse that are applied in, be called bipolar low resistance pulse and bipolar high resistance pulse.To be called bipolar high resistance state and bipolar low resistance state at high resistance state and the low resistance state of the non-volatile memory device of bipolar state.
" with writing of the pulse of using the good same polarity of retention performance " means, and is the writing of non-volatile memory device (one pole writes) of equal state (one pole state) to the polarity of the polarity of low resistance pulse and high resistance pulse.
In one pole writes, with low resistance pulse and the high resistance pulse that is applied in, be called the pulse of one pole low resistance and the pulse of one pole high resistance.To be called one pole high resistance state and one pole low resistance state at high resistance state and the low resistance state of the non-volatile memory device of one pole state.
Present inventors, in order to reach described purpose, that carries out repeatedly discussing found that with all strength: to the non-volatile memory device in bipolar high resistance state, apply the 3rd electric pulse (in an embodiment, with the relation of bipolar high resistance pulse in, same polarity and voltage are bigger, the electric pulse that pulse width is longer), further apply with the 4th electric pulse of the 3rd electric pulse identical polar (in an embodiment, polarity is identical with the 3rd electric pulse, but absolute value of voltage and pulse width and bipolar high resistance pulse and bipolar low resistance pulsion phase electric pulse together), thus, element can be changed to the one pole high resistance state by bipolar high resistance state.By such structure, can be the one pole state by bipolar state variation with non-volatile memory device.The non-volatile memory device of one pole high resistance state is because the maintenance of resistance value good (can through keeping high resistance for more time) is conducive to long data and preserves.In addition, about the element of low resistance state, no matter be bipolar low resistance state or one pole low resistance state, the maintenance of resistance value is all good.
Further present inventors have found: for the non-volatile memory device of one pole high resistance state, apply five electric pulse different with the 3rd electric pulse polarity (in an embodiment, polarity is different with the 3rd electric pulse, but the electric pulse that the absolute value of voltage and the width of pulse are identical with the 3rd electric pulse), element can be changed to bipolar low resistance state by the one pole high resistance state.By such structure, can be bipolar state by the one pole state variation with non-volatile memory device.The non-volatile memory device of bipolar state, because it is it is short to write the pulse width of pulse, favourable for writing at a high speed.In addition, element is become by the one pole high resistance state after the bipolar low resistance state, and by applying bipolar high resistance pulse, element changes to bipolar high resistance state.
Can be bipolar state by the one pole state variation with non-volatile memory device (ReRAM element), unknown so far, be that present inventors find first.
Like this, as the mechanism that the state with non-volatile memory device switches arbitrarily, can consider following content between bipolar state and one pole state.
Namely, non-volatile memory device for bipolar state, resolve the result of resistance value, clear and definite: the variation of resistance states is the region generating as thin as a wafer of the electrode-electric resistive bed interface of the positive electrode side (negative electrode side when applying bipolar low resistance pulse) when applying bipolar high resistance pulse.The result who carries out the Raman scattering parsing knows: the resistance change layer side at this electrode interface is formed with γ-Fe
2O
3Layer.Such result, at Odagawa A.et al., 2007, Electroforming and resistance-switching mechanism in a magnetite thinfilm, Applied Physics Letters vol.91 is disclosed in 133503 grades.
By above result, the mechanism that the resistance states of the non-volatile memory cells under bipolar state changes by be speculated as electrode interface produce at Fe
3O
4And γ-Fe
2O
3Between redox reaction.If electron stream is applied electric pulse to the polarity (polarity of electric current from electrode stream to resistance change layer) of electrode, near the resistance change layer the electrode interface is oxidized, resistance value rise (high resistanceization).If apply the electric pulse of opposite polarity, then near the resistance change layer the electrode interface is reduced, resistance value decline (low resistanceization).
On the other hand, present inventors about non-volatile memory device, have discussed the temperature dependency of resistance value.Figure 13 is illustrated in the temperature dependency of resistance value of the resistance variable element of bipolar state and one pole state.What be used for experiment is to use platinum (Pt) as the material of upper electrode and lower electrode, use Fe
2O
3/ Fe
3O
4Resistance variable element (electrode area: 0.25 μ m as resistance variation material
2, the thickness of resistance change layer: 100nm, resistance change layer formation method: splash).As shown in figure 13, in the element of bipolar state, no matter be high resistance state or low resistance state, be accompanied by the rising of temperature, resistance value reduces.That is, shown similar semi-conductive characteristic.In the element of one pole state, under high resistance state, shown same semiconductor similar characteristics; Under low resistance state, be accompanied by the rising of temperature, resistance value increases.That is to say, understood: the element of one pole low resistance state, the characteristic of demonstration metalloid.
By above results presumption, the mechanism that changes at the resistance states of the non-volatile memory device of one pole state is, generates filament path (Off イ ラ メ Application ト パ ス) between electrode.This filament path by applying voltage, is cut off or continues, thus the switch of the value of having a resistance.
Then, if for the element of bipolar high resistance state, apply and the voltage of bipolar high resistance pulse same polarity (preferred, apply the bigger voltage of absolute value for more time, for example, apply the pulse of one pole low resistance), the then high γ-Fe of resistance value
2O
3Layer thickening, final, by soft breakdown, form the filament path.Thus, component variation is to the one pole low resistance state.Further, apply the voltage (for example, applying bipolar high resistance pulse or the pulse of one pole high resistance) of same polarity, thus, component variation is to the one pole high resistance state.This is " second writes " (one pole switching).
In addition, if the element to the one pole high resistance state, apply with the voltage of bipolar low resistance pulse same polarity (preferred, apply the bigger voltage of absolute value for more time, for example, apply and the absolute value of bipolar low resistance pulsion phase reversed polarity and voltage and the pulse that pulse width equates), γ-Fe then
2O
3Layer is reduced attenuation, Fe
3O
4Increase, change to bipolar low resistance state.This is " writing switching " (bipolar switching).
Namely, in order to solve described problem, Nonvolatile memory devices of the present invention, be have bipolar state and one pole state, by applying electric pulse the Nonvolatile memory devices of the non-volatile memory device of resistance variations, it possesses and carries out second second write circuit that writes and write commutation circuit.Wherein second be written as: to the non-volatile memory device of bipolar high resistance state, apply two electric pulses of same polarity successively, non-volatile memory device is changed to the one pole high resistance state; Writing commutation circuit is: to the non-volatile memory device of one pole high resistance state, apply the switch pulse that writes with described two electric pulse opposite polarities, non-volatile memory device is changed to bipolar low resistance state.
In such structure, in same Nonvolatile memory devices, carry out high speed motion by bipolar writing, and can write by one pole, keep high resistance state for a long time.So, can provide the writing speed of data is accelerated the Nonvolatile memory devices that the retention time of data is elongated and nonvolatile data recording medium.
That is, in order to solve described problem, Nonvolatile memory devices of the present invention has the Nonvolatile memory devices of the non-volatile memory device of resistance variations by applying electric pulse, it is characterized by:
Have and carry out first first write circuit that writes, carry out second second write circuit that writes, write commutation circuit, control device.
Wherein, first writes: by applying first electric pulse to described non-volatile memory device, the resistance value of described non-volatile memory device is second resistance value from first resistance change, by apply second electric pulse with the described first electric pulse opposite polarity to described non-volatile elements, the resistance value of described non-volatile memory device is first resistance value from described second resistance change;
Second writes: by applying the 3rd electric pulse to described non-volatile memory device, the resistance value of described non-volatile memory device is the 4th resistance value from the 3rd resistance change, by apply the 4th electric pulse with described the 3rd electric pulse same polarity to described non-volatile elements, the resistance value of described non-volatile memory device is the 5th resistance value from described the 4th resistance change;
Write commutation circuit: produce and to write switch pulse so that described non-volatile memory device by the 5th resistance value to first resistance change;
Control device: select any one control of described first write circuit, described second write circuit and said write commutation circuit,
By the circuit that uses described control device to select, described non-volatile memory device is carried out described first write or described second write.
The said write commutation circuit is carried out according to before the writing of described first write circuit, and applies after the 5th electric pulse that has with described the 4th electric pulse opposite polarity, carries out writing according to described first write circuit.
Such structure makes the high speed motion of Nonvolatile memory devices and keeps becoming possibility for a long time.
In described Nonvolatile memory devices, preferred first electric pulse and the 3rd electric pulse same polarity.
In addition, in described structure, described first electric pulse is the electric pulse that has same voltage with described the 4th electric pulse, by identical pulse width is set, can reduce the pulse kind, makes the simplification of cutting down circuit area, apparatus structure become possibility.
In described Nonvolatile memory devices, the absolute value of the voltage of preferred the 3rd electric pulse is bigger than the absolute value of the voltage of described the 4th electric pulse.In addition, the pulse width of the 3rd electric pulse is set at more than the pulse width of the 4th electric pulse, and the retention performance of non-volatile memory storage is elongated thus.
Described the 3rd resistance value is characterized by: it is identical with described second resistance value.
Described first resistance value is first low-resistance value, and described second resistance value is first high resistance higher than the resistance value of described first low-resistance value,
Described the 3rd resistance value is described first high resistance, and described the 4th resistance value is second low-resistance value lower than the resistance value of described first low-resistance value,
Described the 5th resistance value is second high resistance higher than the resistance value of described first high resistance.
In addition, Nonvolatile memory devices of the present invention, described control device possesses first control device and second control device, it is characterized by:
Described first control device carries out reading of described non-volatile memory element, and this non-volatile memory device carries out badly according to the writing of described first write circuit, when detecting described first resistance value, carry out according to the writing of described second write circuit,
Described second control device carries out reading of described non-volatile memory element, and this non-volatile memory device has carried out when detecting described the 3rd resistance value, carrying out writing according to described first write circuit according to the writing of described second write circuit.
In such structure, based on the value of reading, can easily judge writing mode.
In described Nonvolatile memory devices, the said write commutation circuit, if before the write activity that carries out according to first write circuit, apply after the 5th electric pulse that has with the 4th electric pulse opposite polarity, carry out the write activity according to first write circuit, then switching to first write activity by second write activity becomes possibility.
In such structure, as at a high speed and the nonvolatile data recording medium that keeps for a long time, can realize the resistance-varying type data carrier.
Described Nonvolatile memory devices is characterized by: comprising: the storage unit array, and it is made of the storage unit that possesses described non-volatile memory device, has a plurality of memory cell region that comprise a plurality of described storage unit; The sign non-volatile memory device, corresponding one of memory cell region, possess and temporarily write mark region, this temporarily writes mark region, have at the non-volatile memory device that belongs to described memory cell region and to write fashionable, corresponding sign based on first of first write circuit with having write described first write state on the non-volatile memory device; Have at the non-volatile memory device that belongs to described memory cell region and to write fashionable, corresponding sign based on second of second write circuit with having write described second write state on the non-volatile memory device.
Nonvolatile data recording medium, it is characterized by: comprise described Nonvolatile memory devices and the 4th control device, described the 4th control device, according to the value that temporarily writes mark region, judge each described memory cell region whether be comprise based on second write circuit write unclosed described non-volatile memory device based on described second write circuit write the object-storage unit zone, the non-volatile memory device that writes the object-storage unit zone that belongs to based on described second write circuit is carried out writing based on second write circuit.
In such structure, based on the value that temporarily writes mark region, can easily judge whether exist according to the unclosed storage unit of the write activity of second write circuit to each memory cell region.Therefore,, can easily judge whether need writing according to second write circuit for its memory cell region.
In described Nonvolatile memory devices, possess the transfer sequence control circuit that the control write circuit is switched, switch first write circuit and second write circuit.This transfer sequence control circuit when the control signal from the external device (ED) input shows that Nonvolatile memory devices is non-selected, controls to carry out writing according to second write circuit.
In such structure, when stopping from the input of the data of external device (ED), self-discipline ground carries out writing according to second write circuit.Therefore, the control by the external control device becomes easy, user's's (making the producer of the system that uses Nonvolatile memory devices etc.) convenience raising.
In addition, nonvolatile data recording medium of the present invention possesses Nonvolatile memory devices and the 5th control device, and the 5th control device is described external device (ED).
In such structure, when the data input from external device (ED) stopped, self-discipline ground carried out writing according to second write circuit.Therefore, become easy by the control of external control device, obtain and to carry out the data carrier that writes according to second write circuit with simple structure.
In described Nonvolatile memory devices, the transfer sequence control device also can constitute, and when power-off, writes commutation circuit in order to carry out controlling according to the write activity of second write circuit.
In such structure, in the moment of power supply disconnection (OFF), the storage unit for the record total data becomes done state according to writing of second write circuit, makes at power supply to disconnect in (OFF), and data also can positively be saved.
In described Nonvolatile memory devices, the transfer sequence control device also can constitute, and when power initiation, writes switching device shifter in order to carry out controlling according to writing of first write circuit.
In such structure, in the moment of power connection (ON), switch to and to carry out according to the writing of first write circuit of high speed motion, when moving usually, owing to do not carry out change action, so can not influence all performances of system substantially because of change action.
In described Nonvolatile memory devices, have under the situation of implementing according to second write circuit about writing, be used for forbidding writing the output function that second of data write the enforcement marking signal from the external device (ED) input.
In such structure, carry out according to writing of second write circuit fashionable because outside control device etc. can easily be differentiated its meaning, so can prevent maloperation.
In addition, the method of operating of Nonvolatile memory devices of the present invention is, have contain bipolar state and one pole state and by applying electric pulse the method for operating of the Nonvolatile memory devices of the non-volatile memory device of resistance variations, it has the switch step that writes of implementing second second write step that writes and implementing to write switching.Wherein, second write step, the non-volatile memory device in the bipolar high resistance state applies two identical electric pulses of polarity successively, and non-volatile memory device is changed to the one pole high resistance state; Write switching, the non-volatile memory device in the one pole high resistance state applies the switch pulse that writes with described two electric pulse opposite polarities, and non-volatile memory device is changed to the one pole low resistance state.
In such formation, in same Nonvolatile memory devices, carry out high speed motion by bipolar writing, and write by one pole, it is possible keeping high resistance state for a long time.Therefore, can provide to make writing speed fast Nonvolatile memory devices and nonvolatile data recording medium that data hold time is long.
With reference to accompanying drawing, from the detailed description of the embodiment of following use, can understand described purpose of the present invention, other purposes, feature and advantage.
Description of drawings
Fig. 1 is the block diagram of schematic configuration of the Nonvolatile memory devices of expression first embodiment of the present invention.
Fig. 2 is the block diagram of schematic configuration of the nonvolatile data recording medium system of expression first embodiment of the present invention.
Fig. 3 is the equivalent circuit figure that the summary of the storage unit array of expression first embodiment of the present invention constitutes.
Fig. 4 is the summary construction diagram that carries out the circuit that the data for the storage unit of first embodiment of the present invention write and read.
Fig. 5 is the chart of the variation of the resistance value of expression when applying electric pulse in the resistance variable element of representing in Fig. 3.
Fig. 6 (a) be the expression have only first write activity 85? in retention performance (maintenance) chart (retention), Fig. 6 (b) is after expression first write activity, implement after second write activity behind first write activity 85? in the chart of retention performance (maintenance).
Fig. 7 is the process flow diagram of summary of first write activity of expression first embodiment of the present invention.
Fig. 8 is the process flow diagram of summary of second write activity of expression first embodiment of the present invention.
Fig. 9 be expression first embodiment of the present invention by second process flow diagram that is written to the summary of first change action that writes.
Figure 10 is the block diagram of schematic configuration of the Nonvolatile memory devices of expression second embodiment of the present invention.
Figure 11 is the block diagram of schematic configuration of the Nonvolatile memory devices of expression the 3rd embodiment of the present invention.
Figure 12 is among the ReRAM that is illustrated in the past, the chart of the relation of the accumulated time of the resistance value of resistance variation material and the potential pulse that is applied in.
Figure 13 is the figure of temperature dependency of resistance value of the resistance variable element of expression bipolar state and one pole state.
Figure 14 is that expression is with the resistance variable element of first embodiment of the present invention, by bipolar state transformation to the one pole state, transform under the situation of bipolar state the figure of the relation of the resistance value of the voltage of pulse and the width of pulse and resistance variable element afterwards again.
Symbol description
100 Nonvolatile memory devices
102 control circuits
104 input data latch (manpower デ one タ ラ Star チ)
106 first write and use pulse generation circuit
107 are written to the first switching pulse generation circuit that writes by second
108 second write and use pulse generation circuit
110 write and use the pulse commutation circuit
111 writing stations
112 write circuits
114 row decoders
116 write-once mark region
118 storage unit arrays
120 sensor amplifiers
122 output data latch
130 bit lines
132 source electrode lines
134 word lines
136 select transistor
138 resistance variable elements
139 storage unit
140 voltage applying circuits
142 voltage applying circuits
144 nmos pass transistors
146 comparers
148 reference resistances
160 nonvolatile data recording medium systems
170 nonvolatile data recording mediums
180 control device
190 systems
192 volatile type memory storages
200 Nonvolatile memory devices
202 control circuits
224 second write sequence control circuits
300 Nonvolatile memory devices
302 control circuits
324 power sequencing circuits
Embodiment
Below, for embodiments of the present invention, describe with reference to accompanying drawing.In addition, have for the additional same symbol of same textural element, omit the situation of explanation.
(first embodiment)
(device constitutes)
Fig. 1 is the block diagram of schematic configuration of the Nonvolatile memory devices of expression first embodiment of the present invention.Below, with reference to Fig. 1, the structure of the Nonvolatile memory devices of present embodiment and the summary of action are described.
As shown in Figure 1, the Nonvolatile memory devices 100 (Nonvolatile memory devices) of present embodiment, possess: control circuit 102, input data latch 104, first write with pulse generation circuit 106, second write with pulse generation circuit 108, by second be written to first switching that writes with pulse generation circuit 107, write with pulse commutation circuit 110, write circuit 112, row decoder 114, write-once mark region 116, storage unit array 118, sensor amplifier 120, output data latch 122.
Input data latch 104, acceptance is from the internal control signal of control circuit 102 and the input signal that is transfused to via the sub-DIN of data input pin from control device 180 (back narration), latch data, with this input data signal, at the appointed time, as writing data-signal, to write circuit 112 outputs.
First writes with pulse generation circuit 106 (first writing station), from control circuit 102, accept internal control signal, represent at this internal control signal under the situation of first write mode, output first writes with pulse (potential pulse), under the situation beyond it, stop output and consume electric power to save.
Second writes with pulse generation circuit 108 (second writing station), from control circuit 102, accept internal control signal, represent at this internal control signal under the situation of second write mode, output second writes with pulse (potential pulse), under the situation beyond it, stop output and consume electric power to save.
Write to first switching that the writes pulse generation circuit 107 by second, from control circuit 102, accept internal control signal, represent at this internal control signal under the situation of second write mode, output writes to first by second and writes switching pulse (potential pulse), under the situation beyond it, stop output and consume electric power to save.
Write with pulse commutation circuit 110 (writing switching device shifter), the lead-out terminal of each pulse generation circuit is electrically connected, writes with pulse generation circuit 106, second and write with pulse generation circuit 108, write to the output of the first switching usefulness pulse generation circuit 107 that writes by second to accept first.Write with pulse commutation circuit 110, accept internal control signal from control circuit 102, represent at this internal control signal under the situation of first write mode, select first output that writes with pulse generation circuit 106, export to write circuit 112; Represent at this internal control signal under the situation of second write mode, select second output that writes with pulse generation circuit 108, export to write circuit 112; Represent to write under the situation of first switch mode that writes by second at this internal control signal, select to write to the output of first switching that writes with pulse generation circuit 107 by second, export to write circuit 112.
In the present embodiment, writing station 111 comprises: first write with pulse generation circuit 106, second write with pulse generation circuit 108, by second be written to first switching that writes with pulse generation circuit 107, write with pulse commutation circuit 110.
Temporarily write mark region 116, have the structure identical with memory cell array 118, with storage unit array 118 total word lines.In temporarily writing mark region 116, the section of a storage unit array 118 (memory cell region) possesses a storage unit (sign resistance variable element).Section in the present embodiment is the unit of the word line of blanket one or more storage unit array 118.That is, the unit of a word line of connection belongs to same section.
Output data latch 122, amplify 120 read data signals of accepting based on the internal control signal of accepting from control circuit 102 and from reading, latch data, at official hour, switch output ground, by the sub-DOUT of data output end, to control device 180 (back narration) or write circuit 112 output read data signals.That is, this internal control signal is represented under the situation of data readout mode, to the read data signal of the sub-DOUT output of data output end as outputting data signals; This internal control signal represent data first write mode, second write mode and by second write mode under the switch mode situation of first write mode, to write circuit 112 outputs as the read data signal that writes data-signal.
Write circuit 112 continues on each bit line of storage unit array 118.Write circuit 112 is accepted the internal control signal from control circuit 102, at official hour, writes to storage unit.Namely, show at this internal control signal under the situation of first write mode, write address information data-signal and this internal control signal based on being included in from what input data latch 104 was accepted, select corresponding bit lines, apply from writing with first of input the pulse commutation circuit 110 and write and use pulse, in the specified address of storage unit array 118, write data.Simultaneously, in the storage unit that temporarily write mark region 116 corresponding with the section that has carried out the address that data write, write " 0 ".
In addition, represent at this internal control signal under the situation of second write mode, judge based on the data-signal of from output data latch 122, accepting that writes, when data are " 0 " (low resistance, first resistance value), based on the address information that is contained in this internal control signal, select corresponding bit lines, apply from writing with what import the pulse commutation circuit 110 and second write and use pulse, carry out second write activity of data in the storage unit array 118.About being contained in the storage unit of this section, if second write end, then write " 1 " in the mark region 116 to temporarily write corresponding with this section.
In addition, represent to write under the first switch mode situation that writes by second at this internal control signal, judge based on the data-signal of from output data latch 122, accepting that writes, when data are " 1 " (high resistance, the 3rd resistance value), based on the address information that is contained in this internal control signal, select corresponding bit lines, apply from write with input the pulse commutation circuit 110 write the switching pulse that writes to first by second, data write to first by second in storage unit array 118 and write switching.About being contained in the storage unit of this section, if second write end, then write " 0 " in the mark region 116 in temporarily write corresponding with this section.Write circuit 112 is constituting to the mode that a plurality of storage unit apply potential pulse simultaneously.
Fig. 2 is the block diagram of the schematic configuration of the expression nonvolatile data recording medium system of first embodiment of the present invention and nonvolatile data recording medium.Below, with reference to Fig. 2, describe about the nonvolatile data recording medium 170 of present embodiment and the structure of nonvolatile data recording medium system 160 and the summary of action.
As shown in Figure 2, nonvolatile data recording 170 possesses Nonvolatile memory devices 100 and control device 180.In addition, nonvolatile data recording medium system 160 possesses nonvolatile data recording medium 170 and system 190 (for example, portable computer, mobile phone etc.), and system 190 possesses the volatile type memory storage 192 of portion (for example, DRAM etc.) within it.Input data signal and address signal that control device 180 is accepted from system 190, at the appointed time, pio chip is selected CS, external control signal CTL, address AD, is write pulse (ラ イ ト パ Le ス) WP, input data signal in the Nonvolatile memory devices 100.In addition, control device 180 is accepted outputting data signals from Nonvolatile memory devices 100, to system's 190 output outputting data signals.By sensor amplifier 120, output data latch 122, export the value that temporarily writes mark region 116 to control device 180, so that can detecting, control device 180 in storage unit array 118, has first data that write.System 190 uses volatile storage 192 as temporary transient storing mechanism.Namely, storage temporarily in volatile storage 192: the data that write to Nonvolatile memory devices 100, the data of from Nonvolatile memory devices 100, reading, use first write mode, to Nonvolatile memory devices 100 high speeds write the data of from volatile storage 192, reading.Afterwards, under the situation of non-selected resistance-varying type data carrier 170, control device 180 is in order to write the signal that the data correspondence comes and long preservation is carried out second and write with first from temporarily write the sign field.
Fig. 3 represents the equivalent circuit figure of schematic configuration of the storage unit array of first embodiment of the present invention.In the present embodiment, storage unit array 118 is 1T1R type (1 transistor, 1 resistance variable element types), possesses: the bit line 130 that has formed in parallel to each other with predetermined distance; Parallel with bit line 130, as to form with the interval of regulation source electrode line 132; Vertical with bit line 130 and source electrode line 132, as to form in parallel to each other with predetermined distance word line 134.Every bit lines 130 and source electrode line 132 are alternatively arranged side by side, between paired bit line 130 and source electrode line 132, be electrically connected with on the intersection point of each bit line 132 and word line 134 by in series one select transistor 136 and the storage unit 139 that resistance variable element 138 constitutes.Bit line 130 is electrically connected on the drain electrode of selecting transistor 136; The source electrode of selection transistor 136 is electrically connected on an end of resistance variable element 138, and the other end of resistance variable element 138 is electrically connected on source electrode line 132, selects the gate electrode of transistor 136 to be electrically connected on the word line 134.Row decoder 114 is connected on each word line 134, and based on the internal control signal of accepting from control circuit 102, the word line 134 that selection should be visited applies voltage (activation), will select transistor 136 to become conducting state.When data write and read, by the combination of bit line 130, source electrode line 132, word line 134, the specific resistance variable element 138 that becomes object applied voltage between bit line 130 and source electrode line 132, perhaps detected the electric current of circulation between.In storage unit 139, the resistance value of corresponding resistance variable element 138 ground storage data, low resistance (LR: about 2k Ω～5k Ω) state is paid " 0 " of binary data, (HR: is about 1M～60M) state paid binary data to high resistance?
Fig. 4 is in expression first embodiment of the present invention, carries out the summary construction diagram for the circuit that writes and read of storage unit.Not expression in Fig. 1, as shown in Figure 4, write circuit 112 possesses voltage applying circuit 140 and voltage applying circuit 142, sensor amplifier 120 possesses comparer 146 and benchmark opposing 148, between the voltage applying circuit 142 of the source electrode line 132 of storage cell array 118 and write circuit 112, be equipped with nmos pass transistor 144.In the present embodiment, write circuit 112 possesses with the same amount of voltage of the number of the storage unit that is applied in potential pulse simultaneously (corresponding to the number of the storage unit of an address: for example 16) and applies circuit 140 and voltage applying circuit 142.In the present embodiment, nmos pass transistor 144 is arranged at the periphery of memory cell array 118.Nmos pass transistor 144 can arrange one at many source electrode lines 132, also can arrange one on every source electrode line 132.
First writes with pulse generation circuit 106, second and writes with pulse generation circuit 108, writes to write to first by second and switches with pulse generation circuit 107, by writing with pulse commutation circuit 110, selectively is connected on the write circuit 112.From writing the pulse with 110 outputs of pulse commutation circuit, input to voltage applying circuit 140 and voltage applying circuit 142.
When the internal control signal that write circuit 112 is accepted is first write mode, voltage applying circuit 140, during the pulse that is transfused to is H, the data that correspondence should write, to the bit line of selecting 130 switch output HIGH voltages (+2V) and 0V; Voltage applying circuit 142, during the pulse that is transfused to is H, the data that correspondence should write, to the source electrode line 132 corresponding to the bit line of selecting 130 switch output 0V and high voltage (+2V).
When the internal control signal that write circuit 112 is accepted was second write mode, voltage applying circuit 140 was during the pulse that is transfused to is H, to the bit line 130 output 0V that select; Voltage applying circuit 142, during the pulse that is transfused to is H, the data that correspondence should write, to the source electrode line 132 corresponding to the bit line of selecting 130 switch output HIGH voltages (+2V) and high voltage (+5V).
The internal control signal that write circuit 112 is accepted be by second write to first write switch mode the time, voltage applying circuit 140, during the pulse that is transfused to is H, to bit line 130 output HIGH voltages of selecting (+5V); Voltage applying circuit 142 is during the pulse that is transfused to is H, to the source electrode line 132 output 0V corresponding to the bit line of selecting 130.
On the other hand, when the internal control signal that write circuit 112 is accepted was readout mode, voltage applying circuit 140 was adjusted to big impedance state (nonconducting state) with its output terminal; Voltage applying circuit 142 is to source electrode line 132 output 0V.
The output terminal of voltage applying circuit 140 is connected in an end of the bit line 130 of storage unit array 118.At the other end of bit line 130, the input terminal of the comparer 146 that the sensor amplifier 120 that continues has.On the input terminal of other of comparer 146, reference resistance 148 has continued.On the other hand, the output terminal of voltage applying circuit 142 is connected an end of source electrode line 132 by nmos pass transistor 144.And, on each intersection point between bit line 130 and the word line 134, between bit line 130 and source electrode line 132, be connected in series and selected transistor 136 and resistance variable element 138.Select the grid of transistor 136 to be connected on the bit line 134.In addition, the grid of nmos pass transistor 144 is connected on the row decoder 114 (with reference to Fig. 1).
[resistance variations of potential pulse and resistance variation material]
Resistance variable element 138 constitutes, and is provided with resistance change layer between the electrode material of Pt etc.Various materials are used to the resistance variation material (material of resistance change layer) of resistance variable element 138, but iron oxide potpourri (Fe
2O
3/ Fe
3O
4, ZnFe
2O
4/ Fe
3O
4) wait the migration metal oxide to be particularly suitable for using.
That is, the resistance change layer of preferred electro-resistance element 138 contains ferriferous oxide, is more preferably resistance change layer and contains iron oxide potpourri (Fe
2O
3/ Fe
3O
4, ZnFe
2O
4/ Fe
3O
4).Resistance change layer also can comprise ferriferous oxide.Resistance change layer also can comprise iron oxide potpourri (Fe
2O
3/ Fe
3O
4, ZnFe
2O
4/ Fe
3O
4) form.
Resistance variable element 138 possesses lower electrode and upper electrode.The electrode material of lower electrode and upper electrode has used various materials.The electrode material of lower electrode and upper electrode can be different.Lower electrode and the upper electrode of preferred resistance variable element 138 comprise platinum (Pt).
Concrete, the structure of resistance variable element 138 need be to realize that bipolar action and one pole move the element of two aspects.If this element, with reference to the record of this instructions, by the electric pulse that suitable adjusting applies, making to change between bipolar state and one pole state becomes possibility.
Fig. 5 is the figure of the variation of the resistance value of expression when applying electric pulse to the resistance variable element 138 shown in Fig. 3.
In first write mode, be " 0 " in the value of for example both having deposited, in first low resistance state, by (for example applying negative pulse, voltage :-2V, pulse width: 120ns), resistance value is changed to first high resistance state by first low resistance state, writes new value " 1 ".In addition, the value of both having deposited is " 1 ", and in first high resistance state, (for example, voltage :+2V, pulse width: 120ns), resistance value is changed to first low resistance state by first high resistance state, writes new value " 0 " by applying positive pulse.Does Fig. 6 (a) expression have only 85 after the enforcement of first write activity? retention performance.Known, the retention time is about 100 hours.
And the data of Fig. 6 (a) are about following content: the material of upper electrode and lower electrode uses platinum (Pt), and resistance variation material is used Fe
2O
3/ Fe
3O
4Resistance variable element (electrode area: 0.25 μ m
2, resistance change layer thickness: the formation method of 100nm, resistance change layer: splash)
In addition, positive voltage refers to, as benchmark, upper electrode is the voltage of positive potential with the lower electrode of resistance variable element 138; Negative voltage refers to lower electrode with resistance variable element 138 as benchmark, and upper electrode is the voltage of negative potential.
First low resistance state is bipolar low resistance state (first resistance value), and first high resistance state is bipolar high resistance state (second resistance value and the 3rd resistance value).Negative pulse is bipolar high resistance pulse (first electric pulse), and positive pulse is bipolar low resistance pulse (second electric pulse).
For example, shown in the left hand view of Fig. 5, at the material use platinum (Pt) of upper electrode and lower electrode, resistance variation material is used Fe
2O
3/ Fe
3O
4Resistance variable element (electrode area: 0.25 μ m
2, resistance change layer thickness: the formation method of 100nm, resistance change layer: splash), be under bipolar low resistance state (the about 2k Ω) situation, if apply negative pulse (voltage :-2V, pulse width: 120ns), then become bipolar high resistance state (about 20k Ω), be under the bipolar high resistance state situation, if apply positive pulse (voltage :+2V, pulse width: 120ns), then become bipolar low resistance (about 2k Ω).
On the other hand, in second write mode, be " 1 " in both values of depositing, in the time of first high resistance state, (for example, voltage :-5V, pulse width: 1ms), resistance value is changed to second low resistance state by first high resistance state by applying long negative pulse; In addition, by applying (the * * of negative pulse (for example, voltage :-2V, pulse width: 120ns), resistance value is changed to second high resistance state by second low resistance state, writes for keeping for a long time for example 10 years).After Fig. 6 (b) is illustrated in first write activity, implement 85 behind second write activity? retention performance (maintenance).According to second write activity, the retention time is more than 1000 hours.
In addition, the resistance variable element of the resistance variable element of Fig. 6 (b) and Fig. 6 (a) is same.
Second low resistance state is one pole low resistance state (the 4th resistance value), clicks high resistance state (the 5th resistance value) during second high resistance state.Long negative pulse is that one pole switches with long pulse (the 3rd electric pulse), and negative pulse is that one pole switches with short pulse (the 4th electric pulse).In addition, in the present embodiment, it is the pulse of one pole low resistance that one pole switches with long pulse, and it is the pulse of one pole high resistance that one pole switches with short pulse.
For example, shown in the figure of Fig. 5 central authorities, the material of upper electrode and lower electrode uses platinum (Pt), and resistance variation material is used Fe
2O
3/ Fe
3O
4Resistance variable element (electrode area: 0.25 μ m
2, resistance change layer thickness: the formation method of 100nm, resistance change layer: splash), under the situation of bipolar high resistance state, if apply long negative pulse (voltage :-5V, pulse width: 1ms), then become one pole low resistance state (about 200 Ω), further apply negative pulse (voltage :-2V, pulse width: 120ns), then become one pole high resistance state (about 200k Ω).In addition, under the situation in the one pole high resistance state, if apply long negative pulse (voltage :-5V, pulse width: 1ms), then become one pole low resistance state (about 200 Ω), under the situation in the one pole low resistance state, if apply negative pulse (voltage :-2V, pulse width: 120ns), then become one pole high resistance state (about 200k Ω).
Write in first switch mode that writes by second, both the value of depositing was to be used for " 1 " of maintenance for a long time, in the time of second high resistance state, by (for example applying long positive pulse, voltage :+5V, pulse width: 1ms), resistance value is changed to second low resistance state by second high resistance state; In addition, (for example, voltage :-2V, pulse width: 120ns), resistance value is changed to first high resistance state by second low resistance state, writes " 1 " that runs up according to first write mode by applying negative pulse.
Long positive pulse is to write switch pulse, and negative pulse is bipolar high resistance pulse.For the element in the one pole high resistance state, write switch pulse by applying, element changes to bipolar low resistance state (first low resistance state).
For example, shown in the figure on Fig. 5 right side, the material of upper electrode and lower electrode uses platinum (Pt), and resistance variation material is used Fe
2O
3/ Fe
3O
4Resistance variable element (electrode area: 0.25 μ m
2, resistance change layer thickness: the formation method of 100nm, resistance change layer: splash), under the situation of one pole high resistance state (about 200k Ω), if apply long positive pulse (voltage :+5V, pulse width: 1ms), then become bipolar low resistance state (about 600 Ω), further apply negative pulse (voltage :-2V, pulse width: 120ns), then become bipolar high resistance state (about 10k Ω).
Figure 14 represents resistance variable element, switches a position one pole state from bipolar state, switches under the situation of bipolar state the figure of the relation between the width of pulse voltage and pulse and the resistance value of resistance variable element afterwards again.
As shown in figure 14, if the resistance variable element in bipolar low resistance state applies negative pulse, then resistance variable element changes (for example first pulse) to bipolar high resistance state.If the resistance variable element in bipolar high resistance state applies positive pulse, then resistance variable element changes (for example second pulse) to bipolar low resistance state.This is " first writes ".
If the resistance variable element in bipolar high resistance state applies long negative pulse, then resistance variable element changes (the 8th pulse) by bipolar high resistance state to the one pole low resistance state.Further, if apply negative pulse to this resistance variable element, then change (the 9th pulse) to the one pole high resistance state.Be " second writes " by writing of the 8th pulse and the 9th pulse.
If the resistance variable element in the one pole high resistance state applies long negative pulse, then resistance variable element changes (for example the tenth pulse) to the one pole low resistance state.If the resistance variable element in the one pole low resistance state applies negative pulse, then resistance variable element changes (for example the 11 pulse) to the one pole high resistance state.This is " one pole writes ".
If the resistance variable element in the one pole high resistance state applies long positive pulse, then resistance variable element changes (the 18 pulse) to bipolar low resistance state.Further, if apply negative pulse to this resistance variable element, then change (nineteen pulse) to bipolar high resistance state.Be " writing the switching that writes to first from second " by writing of the 18 pulse and nineteen pulse.
If " writing the switching that writes to first from second " finishes, then resistance variable element by " first writes ", makes bipolar high resistance state and bipolar low resistance state alternatively change (the 20 later pulse).
In addition, " writing the switching that writes to first from second ", write direct the situation of " 0 " to the resistance variable element in one pole high resistance state (" 1 ") under, it is changed to bipolar high resistance state.
In the present embodiment, the one pole state is for preserving between high resistance state is long-term.Therefore, in the present embodiment, carry out " second writes ", do not carry out " one pole writes ".
Below, referring to figs. 1 through Fig. 4, the data of being undertaken by Nonvolatile memory devices 100 are read and write activity is described in detail.
At first, the action of reading for data describes.When data were read, according to selecting CS and address AD by the chip of control device 180 inputs, according to row decoder 114, specific word line 134 was activated, and the selection transistor 136 that continues on this word line becomes conducting state.Corresponding nmos pass transistor 144 also becomes conducting state by row decoder 114.Then, voltage applying circuit 140 is set in big impedance state (nonconducting state), and voltage applying circuit 142 is set at 0V.Control accordingly forms from comparer 146, by selecting transistor 136, resistance variable element 138, nmos pass transistor 144, the current path of arrival voltage applying circuit 142.Comparer 146 possesses voltage applying circuit, voltage such as applies to this current path and reference resistance 148 both sides.Comparer 146 is read the data (change in voltage type element 138 resistance values) of storage unit by relatively flowing the electric current in both.
Below, more specifically describe.As an example, the value of reference resistance 148 is set at 200k Ω.If the state low resistance state (value that is equivalent to " 0 ") of the resistance variable element 138 of the storage unit of selecting 139, then because the resistance value (=200k Ω) of resistance value (=2k the Ω)＜reference resistance in this path, it is bigger at the electric current of reference resistance 148 than stream that the electric current of stream in this path becomes, comparer 146 output high level.On the contrary, if the state high resistance state (value that is equivalent to " 1 ") of the storage unit of selecting, then because resistance value (=1M Ω first high resistance in this path, 60M Le second high resistance)＞resistance value (=200k Ω) of reference resistance, it is littler at the electric current of reference resistance 148 than stream that the electric current of stream in this path becomes, comparer 146 output low levels.Action thus, the state of selecteed storage unit, the output level of device 146 (read data signal) is read out as a comparison, by output data latch 122, taken out by the data terminal DOUT that exerts oneself as outputting data signals, via control device 180, be sent to system 190.
Then, describe about the data write activity as Nonvolatile memory devices 100 features.The write activity of Nonvolatile memory devices 100 separates write activity by pattern.Fig. 7 is the process flow diagram that is illustrated in the summary of first write activity in first embodiment of the present invention.Fig. 8 is the process flow diagram that is illustrated in the summary of second write activity in first embodiment of the present invention.Fig. 9 is illustrated in writing to the process flow diagram of the summary of first change action that writes by second in first embodiment of the present invention.
Data are write fashionable, according to internal control signal, by write circuit 112 and row decoder 114, select the storage unit 139 of regulation, write.That is, the two ends of this storage unit 139 (bit line 130 and source electrode line 132) is connected electrically on voltage applying circuit 140 and the voltage applying circuit 142 separately, to resistance variable element 138, applies the potential pulse of hope, carries out the switching of resistance value thus.
At first, with reference to Fig. 7, describe about first write activity.If arrive control device 180 from input data signal and the address signal of system's 190 inputs, the then 100 conveying instructions from control device 180 to Nonvolatile memory devices.On input data latch 104, storage (latching) is input to the data of the sub-DIN of data input pin, and the internal control signal of control circuit 102 outputs is set to first write mode, begins action (beginning).
At first, by control device 180 control control circuits 102, read with each section to the corresponding data that temporarily write sign field 116, be worth the judgement (step S102) whether the sign for " 0 " exists.In addition, read action about the data that temporarily write sign field 116 because with storage unit array 118 to read action identical, so omit explanation.In step S102, to differentiate under the situation for NO, whole storage unit is second write mode, therefore, carries out writing to first change action that writes (step S301～) by second.In step S102, be judged to be the situation of YES, be the state that possible carry out first write activity.
Then, to the word line 134 corresponding with the address shown in the address AD, (for example+5V), the word line 134 to other applies non-activation voltage (for example 0V) to apply activation voltage.By this action, the selection transistor 136 that should write the address of data becomes conducting state (step S103).In addition, this moment, corresponding nmos pass transistor 144 also became conducting state.
The data that should write, by binary number (position) formation of two values of getting " 1 " and " 0 ", an address is shared by the position of a plurality of (for example 16).So at first writing has the judgement (step S104) that does not have " 1 " in the data, if be judged to be YES, for the storage unit 139 that should write " 1 ", write circuit 112 is set to be used to applying first positive pulse (step S105).That is, for this storage unit, carry out the setting of write circuit 112, apply+2V to voltage applying circuit 140, apply 0V to voltage applying circuit 142 sides.
First positive pulse is bipolar low resistance pulse (second electric pulse).By applying first positive pulse, element changes to bipolar low resistance state from bipolar high resistance state.
Then, writing has the judgement (step S106) that does not have " 0 " in the data, if be judged to be YES, for the storage unit 139 that should write " 0 ", write circuit 112 is set to be used to applying first negative pulse (step S107).That is, about this storage unit, carry out the setting of write circuit 112, apply 0V to voltage applying circuit 140 sides, apply+2V to voltage applying circuit 142.In addition, in step S102, be judged to be under the situation of NO, write " 0 " to whole unit, therefore enter into step S105, for whole unit of this address, write circuit 112 is set to be used to applying negative pulse.
First negative pulse is bipolar high resistance pulse (first electric pulse).By applying first negative pulse, element changes to bipolar high resistance state from bipolar low resistance state.
Then, Xiang Yuying writes the corresponding storage unit 139 in address of data, applies first potential pulse (step S108) that writes with pulse generation circuit 106 outputs.And, in step S106, also be judged to be under the situation of NO steps performed S108.
In step 108, for the unit that should write " 1 ", from voltage applying circuit 140, via bit line 130 and selection transistor 136, the end to resistance variable element 138 applies+2V; Via nmos pass transistor 144 and source electrode line 132, with stipulated time (for example 120ns), apply 0V voltage to the other end of resistance variable element 138 from voltage applying circuit 142.By this voltage application, the resistance states of resistance variable element 138 from low resistance state (for example, about 2k Ω) to compare the little high resistance state of resistance value (for example, about 2M Le) as the high resistance state of target and change.
In addition, for the unit that should write " 0 ", from voltage applying circuit 140, via bit line 130 with select transistor 136, apply 0V to an end of resistance variable element 138, from voltage applying circuit 142, via nmos pass transistor 144 and source electrode line 132, to the other end of resistance variable element 138, (for example 120ns) at the appointed time applies+voltage of 2V.That is, positive pulse writes and applies the opposite polarity pulse.Apply by this voltage, the resistance states of resistance variable element 138 from high resistance state (for example, about 1M Ω) to compare the big low resistance state of resistance value (for example, about 2k Ω) as the low resistance state of target and change.
If step S108 finishes, then write " 0 " (step S109) to the sign that temporarily writes sign field 116 corresponding with containing the section that carried out first address that writes with resistance variable element.And, identical with write activity for the storage unit 139 of storage unit array 118 to the write activity that temporarily writes sign field 116, therefore omit explanation.
If finish to temporarily writing writing of sign, then finish (end) to writing of this address.Once first write the time that needs about 120ns.Nonvolatile memory devices 100 by carrying out the temporary transient write activity from step S101 to S109 repeatedly, carries out writing for first of a series of data of each address.
Then, with reference to Fig. 8, describe about second write activity.Finish to writing of each address, if the order that writes and read for nonvolatile data recording medium 170 that arrives from system 190 stops, then according to the control of control device 180, control circuit 102 is selected second write mode, begins second write activity (beginning).
At first, by control device 180 control control circuits 102, read the data that temporarily write sign field 116 corresponding with each section, be worth the judgement (step S202) whether the sign for " 0 " exists.In addition, read action about the data that temporarily write sign field 116 because with storage unit array 118 to read action identical, so omit explanation.In step S102, to differentiate under the situation for NO, second write activity of whole storage unit is finished, and therefore, need not carry out second write activity (end).On the other hand, in step S202, be judged to be the situation of YES, according to the control of control device 180, carry out a series of second write activity (step S203～).
At first, read out in corresponding to the total data (" 1 " or " 0 ") that goes up record for the section of the sign of " 0 " (below, second writes the object section), be stored in output data latch 122 (writing data storage device) and go up (step S203).
Then, write the variable N substitution 0 (step S204) in area to expression second section that writes the object section, taking-up unit in the data of storage writes the data (for example 16) of the amount of figure place, and 112 pass on (step S205) from output data latch 122 to write circuit.
If carry data to write circuit 112, then write regional corresponding word line 134 with N section of this section and apply activation voltage (for example+5V), the word line 134 to other applies non-activation voltage (for example 0V).By this action, the selection transistor 136 that data should be carried out second unit that writes becomes conducting state (step S206).In addition, this moment, corresponding NMSO transistor 144 also became conduction state.
Then, writing of carrying out carrying in write circuit 112 has the judgement (step S207) that does not have " 1 " in the data (section writes the data of storing in the unit of regional N), if be judged to be YES, then for answering second storage unit (unit of storage unit array 218) that writes " 1 ", write circuit 112 is set to second negative pulse and applies usefulness (step S208).That is, about this unit, carry out the setting of write circuit 112, apply voltage, apply-5V to voltage applying circuit 140, apply 0V to voltage applying circuit 142, (step 209).Then, for this unit, write circuit 112 is set at first negative pulse and applies usefulness (step S210).That is, about this storage unit, carry out the setting of write circuit 112, apply voltage, apply-2V to voltage applying circuit 140, apply 0V (step 211) to voltage applying circuit 142.
Second negative pulse is the long pulse (the 3rd electric pulse) that one pole switches usefulness.First negative pulse is that one pole switches with short pulse (the 4th electric pulse).By applying this two pulses successively, element is changed to the one pole high resistance state by bipolar high resistance.
If in step S207, be judged to be NO, then return step S205.
If step S210 finishes, then add 1 (step 212) at N, carry out the judgement (step S213) whether N surpasses Nmax, then do not return step 204 if surpass.By this action, write regional N=1,2 by section ..., carry out second successively till the Nmax and write.If N surpasses Nmax, then about this section, second writes and finishes, and therefore writes 1 to the mark region that temporarily writes corresponding to this section, sets (step S214) thus, returns step S201.In addition, to the write activity that temporarily writes sign field 116, the write activity that carries out with unit to storage unit array 218 is identical, therefore omits explanation.
By this action, Nonvolatile memory devices 100 by carrying out the action from step S201 to step 213 repeatedly, to subsidiary being masked as till 1 of whole sections, carrying out second successively and writes.
Then, with reference to Fig. 9, describe about being written to first change action that writes from second.Finish to writing of each address, if the order that writes and read with respect to nonvolatile data recording medium 170 that arrives from system 190 stops, then according to the control of control device 180, select control circuit 102 to select to write the switch mode that writes to first, beginning change action (beginning) from second.
At first, by control device 180 control control circuits 102, read with each section to the corresponding data that temporarily write sign field 116, be worth the judgement (step S302) whether the sign for " 1 " exists.In addition, read action about the data that temporarily write sign field 116 because with storage unit array 118 to read action identical, so omit explanation.In step S302, differentiate under the situation for NO, owing to be the first write activity pattern of whole storage unit, therefore, need not carry out change action (end).On the other hand, in step S302, be judged to be under the situation of YES, according to the control of control device 180, carry out a series of switching write activity (step S303～).
At first, the section (below, switch object section) that reads out in the sign that corresponds to " 1 " is gone up the total data (" 1 " or " 0 ") of record, is stored in output data latch 122 (writing data storage device) and goes up (step S303).
Then, switch the variable N substitution 0 (step S304) that the section that writes the object section writes the area to expression, taking-up unit in the data of storage writes the data (for example 16) of the amount of figure place, and 112 pass on (step S305) from output data latch 122 to write circuit.
If carry data to write circuit 112, then write regional corresponding word line 134 with N section of this section and be applied in activation voltage (for example+5V), the word line 134 to other applies non-activation voltage (for example 0V).By this action, the selection transistor 136 that data should be carried out second unit that writes becomes conducting state (step S306).In addition, this moment, corresponding NMSO transistor 144 also became conducting state.
Then, writing of carrying out carrying in write circuit 112 has the judgement (step S307) that does not have " 1 " in the data (section writes the data of storing in the unit of regional N), if be judged to be YES, then for the unit that should switch " 1 " (unit of storage unit array 218), write circuit 112 is set to and applies second positive pulse usefulness (step S308).That is, about this storage unit, carry out the setting of write circuit 112, apply voltage, apply+5V to voltage applying circuit 140 sides, apply 0V to voltage applying circuit 142, (step S309).Then, for this unit, write circuit 112 is set at first negative pulse and applies usefulness (step S310).That is, about this unit, carry out the setting of write circuit 112, apply voltage, apply-2V to voltage applying circuit 140, apply 0V (step 311) to voltage applying circuit 142.
Second positive pulse is to write switch pulse.First negative pulse is bipolar high resistance pulse (first electric pulse).By applying this two pulses successively, element is changed to bipolar high resistance state by the one pole high resistance state.
If in step S307, be judged to be NO, then return step S301.
If step S310 finishes, then add 1 (step 312) at N, carry out the judgement (step S313) whether N surpasses Nmax, then do not return step 304 if surpass.By this action, write regional N=1,2 at section ..., till the Nmax, carry out change action successively.If N surpasses Nmax, then about this section, change action is finished, and therefore writes 0 to the mark region that temporarily writes corresponding to this section, sets (step S314) thus, returns step S301.In addition, to the write activity that temporarily writes sign field 116, the write activity that carries out with unit to storage unit array 218 is identical, therefore omits explanation.
By this action, Nonvolatile memory devices 100 by carrying out the action from step S301 to step 313 repeatedly, to subsidiary being masked as till 1 of whole sections, carries out change action successively.
By above such action and structure, Nonvolatile memory devices 100 in the present embodiment, select CS, external control signal CTL, address AD, write pulse WP corresponding to the chip that is transfused to, reading of the storage unit 139 of wishing moved and write activity, thus, and by first write activity with short pulse (120ns), write activity at a high speed becomes possibility, in addition, on the spot by second write activity and to write, the keeping quality of data is improved.
(embodiment 2)
Figure 10 is the block diagram of schematic configuration of the Nonvolatile memory devices of expression second embodiment of the present invention.Below, with reference to Figure 10, describe about the formation of the non-volatile apparatus of present embodiment and the summary of action.In addition, the Nonvolatile memory devices of second embodiment, in the control circuit of the Nonvolatile memory devices of first embodiment, append the second write sequence control circuit 224, it is the circuit that output second writes the implementation sign FG from control circuit to control device, and other structures, action are identical with first embodiment.Therefore, about common textural element, with same symbol and title, omit explanation.
The second write sequence control circuit 224 is the circuit be used to the control of carrying out second write activity, in the first embodiment, realizes the control of second write activity that control device 180 carries out in the inside of Nonvolatile memory devices.
Whether second writes in the implementation sign FG is, based on being in second writes, (not shown: Shu Chu the binary signal control device 180 that is equivalent to first embodiment) to the control device of control circuit 202 outsides.Second to write in the implementation sign FG be under the situation of " 1 ", and expression Nonvolatile memory devices 200 is in second writes, and the acceptance of the data of coming from the outside is impossible.Sign FG is under the situation of " 0 " in second implementation, and expression Nonvolatile memory devices 200 is not in second writes, and the acceptance (first writes) of the data of coming from the outside is possible.
In the present embodiment, as shown in Figure 2, can constitute as the nonvolatile data recording medium that possesses control device.
The Nonvolatile memory devices 200 of present embodiment can access the effect identical with the Nonvolatile memory devices 100 of first embodiment, and need not control second write activity by the control device of outside, therefore, improves user convenience.In addition, write as second and to indicate FG in the implementation, in the time of output " 1 ", external control device, system do not carry out the instruction that writes of data, can prevent malfunction thus.
(the 3rd embodiment)
Figure 11 is the block diagram of schematic configuration of the Nonvolatile memory devices of expression the 3rd embodiment of the present invention.Below, with reference to Figure 11, describe about the structure of the Nonvolatile memory devices of present embodiment and the summary of action.In addition, the Nonvolatile memory devices of the 3rd embodiment is the device that the second write sequence control circuit of the Nonvolatile memory devices of second embodiment is replaced into the power sequencing circuit, and other structures, action are identical with second embodiment.Therefore, about common textural element, with same symbol and title, omit explanation.
Power supply sequent control circuit 324 is circuit that group is gone into control circuit 302, is in the power-off of Nonvolatile memory devices 300, makes powered-down (パ ワ one ダ ウ Application シ one ケ Application ス) sequentially-operating, carries out second circuit that writes.In addition, when being the power initiation of Nonvolatile memory devices 300, make the power connection sequentially-operating, carry out the circuit that is written to first change action that writes from second.
The driven by power that Nonvolatile memory devices 300 is supplied with by the outside.Therefore, the power-off of Nonvolatile memory devices 300 does not carry out automatically, and the outside control signal of coming begins and be based on.Concrete is to carry out power supply by following steps and disconnect.
At first, during the power-off of system (system 190 that is equivalent to Fig. 2), (control device 180 that is equivalent to Fig. 2) transmits the notification signal of power-off from system to control device.Control device then sends the power-off signal to Nonvolatile memory devices 300 if accept the notification signal of power-off.Power supply sequent control circuit 324 if accept the power-off signal, is then carried out the powered-down order, in its action, carries out second and writes.And, identical with second write activity of first embodiment at second write activity of powered-down order, therefore omit explanation.
If the switch connection (ON) of system (system 190 that is equivalent to Fig. 2), power initiation begins, and (control device 180 that is equivalent to Fig. 2) and Nonvolatile memory devices 300 beginning electric power are supplied with then from system to control device.Power supply sequent control circuit 324, the supply that detects electric power begins, and carries out the power-on order, carries out writing the switching that writes to first from second.In addition, in the power connection order, write the change action that writes to first by second, with first embodiment to append write activity identical, therefore omit explanation.
As above, in the present embodiment, carry out second during power-off together and write.Therefore, when power supply disconnected (OFF), about recording the storage unit of all data, second write and finishes, and disconnected at power supply that data also positively are saved in (OFF).On the other hand, when the power connection (ON), storage unit about the record total data, become first write mode, during power connection (ON) (when moving usually), do not carry out second write activity and write the change action that writes to first from second, it is processed that the writing of data all writes by first.Therefore, obviously writing speed accelerates.Namely, when moving usually, do not carry out second write activity and write the change action that writes to first by second, therefore second write activity and write by second that all performances do not have substantial influence for system to first change action that writes obtains good like this effect.
From described explanation as can be known, for those skilled in the art, many improvement of the present invention and other embodiments all can be known.Therefore, described explanation should only be explained as illustration, is shown as purpose and is provided to those skilled in the art will carry out best mode of the present invention.In the scope that does not break away from purport of the present invention, can change its detailed structure and/or function substantially.
Nonvolatile memory devices of the present invention can run up, and can realize the Nonvolatile memory devices that reliability is high, is useful in the various electronic device field of carrying Nonvolatile memory devices.
Claims (18)
1. Nonvolatile memory devices, it has, have bipolar state and one pole state and by applying of electric pulse the non-volatile memory device of resistance variations, it is characterized in that having:
The one pole commutation circuit, it carries out one pole and switches, and the action that one pole switches is that the non-volatile memory device in bipolar high resistance state applies two identical electric pulses of polarity successively, and non-volatile memory device is changed to the one pole high resistance state;
Write commutation circuit, it applies the switch pulse that writes with described two electric pulse opposite polarities to the non-volatile memory device in the one pole high resistance state, and non-volatile memory device is changed to bipolar low resistance state.
2. Nonvolatile memory devices, the non-volatile memory device that it has the resistance variations by applying of electric pulse is characterized by, and has:
First write circuit, it carries out first and writes, first action that writes is, by applying first electric pulse to described non-volatile memory device, the resistance value of described non-volatile memory device is second resistance value from first resistance change, by apply second electric pulse with the described first electric pulse opposite polarity to described non-volatile elements, the resistance value of described non-volatile memory device is described first resistance value from described second resistance change;
Second write circuit, it carries out second and writes, second action that writes is, by applying the 3rd electric pulse to described non-volatile memory device, the resistance value of described non-volatile memory device is the 4th resistance value from second resistance change, by apply the 4th electric pulse with described the 3rd electric pulse same polarity to described non-volatile elements, the resistance value of described non-volatile memory device is the 5th resistance value from described the 4th resistance change;
Write commutation circuit, its generation writes switch pulse so that described non-volatile memory device by the 5th resistance value to described first resistance change;
Control device, it selects any one control of described first write circuit, described second write circuit and said write commutation circuit,
By using the selected circuit of described control device, described non-volatile memory device is carried out described first write or described second write.
3. Nonvolatile memory devices as claimed in claim 2 is characterized by:
The said write commutation circuit is being carried out based on before the writing of described first write circuit, and applies after the 5th electric pulse that has with described the 4th electric pulse opposite polarity, carries out writing based on described first write circuit.
4. Nonvolatile memory devices as claimed in claim 2 is characterized by:
Described first electric pulse and described the 3rd electric pulse same polarity.
5. Nonvolatile memory devices as claimed in claim 2 is characterized by:
Described first electric pulse is the electric pulse identical with the voltage of described the 4th electric pulse.
6. as each described Nonvolatile memory devices of claim 2 to 5, it is characterized by:
Described first electric pulse has identical pulse width with the pulse of described the 4th electric pulse.
7. as each described Nonvolatile memory devices of claim 2 to 5, it is characterized by:
The absolute value of the voltage of described the 3rd electric pulse is bigger than the absolute value of the voltage of described the 4th electric pulse.
8. as each described Nonvolatile memory devices of claim 2 to 5, it is characterized by:
The pulse width of described the 3rd electric pulse is more than the pulse width of described the 4th electric pulse.
9. Nonvolatile memory devices as claimed in claim 2 is characterized by:
Described first resistance value is first low-resistance value, and described second resistance value is first high resistance bigger than the resistance value of described first low-resistance value,
Described the 4th resistance value is second low-resistance value littler than the resistance value of described first low-resistance value,
Described the 5th resistance value is second high resistance bigger than the resistance value of described first high resistance.
10. Nonvolatile memory devices as claimed in claim 2 is characterized by:
The said write commutation circuit is being carried out based on before the writing of first write circuit, and carries out the write activity based on first write circuit after applying the 5th electric pulse that has with the 4th electric pulse opposite polarity.
11. Nonvolatile memory devices as claimed in claim 2 is characterized by:
Also comprise:
The storage unit array, it is made of the storage unit that possesses described non-volatile memory device, has a plurality of memory cell region that comprise a plurality of described storage unit;
Sign use non-volatile memory device, one of memory cell region correspondence,
Possess and temporarily write mark region, this temporarily writes mark region, have at the non-volatile memory device that belongs to described memory cell region and to write fashionable, corresponding sign based on first of first write circuit with having write first write state on the non-volatile memory device; Have at the non-volatile memory device that belongs to described memory cell region and to write fashionable, corresponding sign based on second of second write circuit with having write second write state on the non-volatile memory device.
12. Nonvolatile memory devices as claimed in claim 2 is characterized by:
Possess the transfer sequence control circuit of control said write commutation circuit, switch described first write circuit and described second write circuit,
Described transfer sequence control circuit, when the control signal from the external device (ED) input showed that Nonvolatile memory devices is non-selected, control said write commutation circuit was carried out writing based on described second write circuit.
13. Nonvolatile memory devices as claimed in claim 2 is characterized by:
Have under the situation of implementing based on described second write circuit about writing, be used for forbidding writing the output function that second of data write the enforcement marking signal from the external device (ED) input.
14. a nonvolatile data recording medium is characterized by:
Comprise Nonvolatile memory devices as claimed in claim 11 and the 4th control device,
Described the 4th control device, according to the value that temporarily writes mark region, judge each described memory cell region whether be comprise based on second write circuit write unclosed described non-volatile memory device based on described second write circuit write the object-storage unit zone, the non-volatile memory device that writes the object-storage unit zone that belongs to based on described second write circuit is carried out writing based on second write circuit.
15. a nonvolatile data recording medium is characterized by:
Possess Nonvolatile memory devices, the 5th control device as claim 12 record,
Described the 5th control device is described external device (ED).
16. nonvolatile data recording medium as claimed in claim 15 is characterized by:
Described the 5th control device constitutes, in order to carry out controlling the said write commutation circuit based on described second the writing of write circuit when the power-off.
17. nonvolatile data recording medium as claimed in claim 15 is characterized by:
Described the 5th control device constitutes, in order to carry out controlling the said write commutation circuit based on described first the writing of write circuit when the power connection.
18. the driving method of a Nonvolatile memory devices, this Nonvolatile memory devices have comprise bipolar state and one pole state and by applying electric pulse the non-volatile memory device of resistance variations,
This driving method comprises:
The one pole switch step, the non-volatile memory device that carries out in the bipolar high resistance state applies two identical electric pulses of polarity successively, and non-volatile memory device is switched to the one pole that the one pole high resistance state changes;
Write switch step, carry out non-volatile memory device in the one pole high resistance state and apply the switch pulse that writes with described two electric pulse opposite polarities, make non-volatile memory device write switching to what bipolar low resistance state changed thus.
Applications Claiming Priority (3)
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| JP279876/2007 | 2007-10-29 | ||
| JP2007279876 | 2007-10-29 | ||
| PCT/JP2008/003055 WO2009057275A1 (en) | 2007-10-29 | 2008-10-28 | Nonvolatile storage device and nonvolatile data recording medium |
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| CN101627438A CN101627438A (en) | 2010-01-13 |
| CN101627438B true CN101627438B (en) | 2013-10-09 |
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| JP (1) | JP4464462B2 (en) |
| CN (1) | CN101627438B (en) |
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| WO2011013350A1 (en) * | 2009-07-29 | 2011-02-03 | パナソニック株式会社 | Memory device, host device, and memory system |
| JP5657876B2 (en) * | 2009-10-07 | 2015-01-21 | ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． | Semiconductor memory device |
| JP5032611B2 (en) * | 2010-02-19 | 2012-09-26 | 株式会社東芝 | Semiconductor integrated circuit |
| CN102422361B (en) * | 2010-03-30 | 2014-03-19 | 松下电器产业株式会社 | Non-volatile storage device and method for writing to non-volatile storage device |
| JP5508944B2 (en) | 2010-06-08 | 2014-06-04 | 株式会社東芝 | Semiconductor memory device |
| JP5560944B2 (en) * | 2010-06-18 | 2014-07-30 | ソニー株式会社 | Driving method of memory element |
| US8462580B2 (en) * | 2010-11-17 | 2013-06-11 | Sandisk 3D Llc | Memory system with reversible resistivity-switching using pulses of alternatrie polarity |
| JP5602175B2 (en) * | 2012-03-26 | 2014-10-08 | 株式会社東芝 | Nonvolatile semiconductor memory device and data writing method thereof |
| US9190149B2 (en) * | 2012-08-24 | 2015-11-17 | Infineon Technologies Ag | Method and system for switchable erase or write operations in nonvolatile memory |
| US9171616B2 (en) * | 2013-08-09 | 2015-10-27 | Macronix International Co., Ltd. | Memory with multiple levels of data retention |
| KR102061343B1 (en) * | 2013-11-06 | 2020-02-11 | 에스케이하이닉스 주식회사 | Semiconductor device |
| US9484094B2 (en) * | 2015-01-21 | 2016-11-01 | Ememory Technology Inc. | Control method of resistive random-access memory |
| WO2016194175A1 (en) * | 2015-06-03 | 2016-12-08 | 株式会社日立製作所 | Storage system |
| US9443587B1 (en) * | 2015-07-21 | 2016-09-13 | Winbond Electronics Corp. | Resistive memory apparatus and writing method thereof |
| JP2019071577A (en) * | 2017-10-11 | 2019-05-09 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor circuit and method of controlling the same |
| US10665313B1 (en) * | 2019-05-02 | 2020-05-26 | Sandisk Technologies Llc | Detecting short circuit between word line and source line in memory device and recovery method |
| US10726897B1 (en) * | 2019-05-14 | 2020-07-28 | International Business Machines Corporation | Trimming MRAM sense amp with offset cancellation |
| CN110708793B (en) * | 2019-09-26 | 2021-03-23 | 深圳市明微电子股份有限公司 | Cascade control method of cascade equipment, cascade equipment and illumination system |
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Also Published As
| Publication number | Publication date |
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| JP4464462B2 (en) | 2010-05-19 |
| US20100014343A1 (en) | 2010-01-21 |
| US8094482B2 (en) | 2012-01-10 |
| JPWO2009057275A1 (en) | 2011-03-10 |
| CN101627438A (en) | 2010-01-13 |
| WO2009057275A1 (en) | 2009-05-07 |
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