CN101562594B - Phase factor combined circuit based on stream line operation - Google Patents

Abstract

A phase factor combined circuit based on stream line operation relates to the field of integrated circuit design, and solves the problem of data jamming in operation by adopting an interleaved partitioning part transfer sequence method in time domain in the prior orthogonal frequency division multiplexing technology. The circuit completes the process of combination and storage of a group of four phase factors of data in first four clock signals when the circuit begins to work; the circuit completes the process of accumulating data produced by combining the phase factors in subsequent four clock signals, and simultaneously completes the process of combination and storage of the next group of four phase factors of data; and the action of the four clock signals is repeated, and the transmission and the accumulation of the data are completed. The phase factor combined circuit can complete the combination and accumulation of the phase factors of a group of data by only needing four clock signals, and are consistent with the IFFT conversion rates of the process so as not to cause the data jamming. The phase factor combined circuit based on the stream line operation is suitable for a PTS method in the prior OFDM system.

Description

Phase factor combined circuit based on pile line operation

Technical field

The present invention relates to the integrated circuit (IC) design field, be specifically related to a kind of integrated circuit of the communications field.

Background technology

Because OFDM (OFDM) technology has advantages such as band efficiency height, anti-multipath decline ability is strong, causes people's attention more and more.Yet the major defect of ofdm system is to have big peak-to-average power than (PAPR), causes nonlinear distortion easily, causes signal distortion, makes system performance degradation, therefore need manage its reduction.The PAPR method that reduces ofdm signal mainly comprises direct shearing method, shearing and filtering technique, compression-expansion technique, coding techniques, selection reflection method (SLM) and partial transmission sequence method (PTS) etc. repeatedly.Wherein the PTS method is a kind of undistorted phase optimization technology, can reduce the PAPR of ofdm signal effectively.But the PTS method need be carried out a plurality of inverse fourier transforms (IFFT) operation, has higher computation complexity.Yet based on the thought of cyclic shift, time domain interweaves and cuts apart the PTS method and only need IFFT one time.The method principle as shown in Figure 1, the PTS method mainly comprises three unit: 1 IFFT processing unit that N is ordered, 1 phase factor combining unit, 1 PAPR optimizes the unit, the process of described method is:

At first with frequency domain data X=[X ₀, X ₁..., X _N-1] become time domain data x={x by IFFT ₀, x ₁..., x _N-1], then to time domain data x carry out cyclic shift and with M phase factor vector $d^m=[d_0^m,d_1^m,...,d_{V-1}^m]$ In conjunction with obtaining M group alternative signal $x^m=[x_0^m,x_1^m,...,x_{N-1}^m],$ x ^mSignaling point can be expressed as

$x_n^m=\underset{i=0}{\overset{V-1}{\mathrm{\Σ}}}{d}_i^m\left\{x{\left((n-\mathrm{iN}/V)\right)}_N{R}_n\right\}$

Here N is the subcarrier number, and V is the number of element in the phase factor vector, { x ((n-iN/V)) _NR _nBe the sequence of iN/V position gained of sequence x ring shift right, and n=0 wherein, 1 .., N-1, i=0,1 ..., V-1, m=1,2 .., M.Calculate the PAPR of every group of alternative signal at last and select the minimum alternative signal x ' of PAPR to send to receiving terminal.

At subcarrier is N=128, and the situation of V=4 (when N, V get other values therewith in like manner), time domain interweave and cut apart PTS gained alternative signal and account for and can be expressed as

$x_n^m=\underset{i=0}{\overset{3}{\mathrm{\Σ}}}{d}_i^m\left\{x{\left((n-i\×32)\right)}_{128}{R}_n\right\}$

Wherein the signaling point that was respectively 0,32,64,96 o'clock of the value of n can be expressed as

$x_0^m=d_0^m{x}_0+d_1^m{x}_{96}+d_2^m{x}_{64}+d_3^m{x}_{32}$

$x_{32}^m=d_0^m{x}_{32}+d_1^m{x}_0+d_2^m{x}_{96}+d_3^m{x}_{64}$

$x_{64}^m=d_0^m{x}_{64}+d_1^m{x}_{32}+d_2^m{x}_0+d_3^m{x}_{96}$

$x_{96}^m=d_0^m{x}_{96}+d_1^m{x}_{64}+d_2^m{x}_{32}+d_3^m{x}_0$

The data point x of alternative signal ₀ ^m, x ₃₂ ^m, x ₆₄ ^m, x ₉₆ ^mJust by x ₀, x ₆₄, x ₃₂, x ₉₆These 4 data combine with phase factor and can obtain, and for the IFFT processor of pipeline organization, if the input data are order inputs, then dateout is that backward is arranged, and therefore the data of at first coming out are x ₀, x ₆₄, x ₃₂, x ₉₆..According to top equation, as four data x ₀, x ₆₄, x ₃₂, x ₉₆. in the time of acquisition, the operation of phase factor combination can be carried out immediately, and need not wait for that the IFFT processor finishes the IFFT that N orders and calculate, and does not also need the operation of cyclic shift, just utilizes the data inverse order relation that comes out to get final product.

The process of phase factor combination moves to right from multiply each other result's direction level of arrow in Fig. 2 of back gained of the data of IFFT unit and 4 phase factors as shown in Figure 2, needs 16 memory cell with its storage.After 4 clock cycle, 16 memory cell are filled up, and data path is changed into the form of Fig. 3, then four data in each path are done the operation that adds up, and can obtain the signaling point x of alternative signal through 4 clock cycle ₀ ^m, x ₃₂ ^m, x ₆₄ ^m, x ₉₆ ^mBy the time data accumulation finishes, and data path returns to the form of Fig. 2, the operation before repeating then.

Use said method operation, 4 signaling points that obtain alternative signal need 8 clock cycle, and then the speed of the speed of the combination of the phase factor data of coming than IFFT unit is slow, can cause data to stop up.

Summary of the invention

The present invention is for solving in existing OFDM (OFDM) technology, adopt time domain to interweave and cut apart there is data jamming in the PTS method in realizing the process that PAPR optimizes problem, a kind of phase factor combined circuit based on pile line operation is provided, it comprises clock unit, select the signal generation unit, four multipliers, 12 registers and accumulator group, wherein said 12 registers are divided into three grades, that is: first order registers group, second level registers group and third level registers group, each grade registers group has four registers, and four accumulators are arranged in the accumulator group;

Pending data multiply each other by four multipliers with four road phase factors respectively simultaneously, described four multipliers output signal to four registers of first order registers group respectively, four registers of described first order registers group output signal to four registers of second level registers group respectively, four registers of described second level registers group output signal to four registers of third level device storage respectively, and four registers of described third level registers group output signal to four accumulators of accumulator group respectively;

Clock unit clock signal Clock gives and selects the signal generation unit, three path select signals of described selection signal generation unit output, be respectively: first path select signal Sel_0, second path select signal Sel_1 and the 3rd path select signal Sel_2, wherein first path select signal Sel_0 is used to control the signaling path between first order registers group and the second level registers group; Second path select signal Sel_1 is used to control the signaling path between second level registers group and the third level registers group; The 3rd path select signal Sel_2 is used to control the signaling path between third level registers group and the accumulator group;

Pass between the input signal Clock of selection signal generation unit and three path select signals of output is:

When first path select signal Sel_0 is 0, be parallel path between first order registers group and the second level registers group; When first path select signal Sel_0 is 1, be crossedpath between first order registers group and the second level registers group; When second path select signal Sel_1 is 0, be parallel path between second level registers group and the third level registers group; When second path select signal Sel_1 is 1, be crossedpath between second level registers group and the third level registers group; When the 3rd path select signal Sel_2 is 0, be parallel path between third level registers group and the accumulator group; When the 3rd path select signal Sel_2 is 1, be crossedpath between third level registers group and the accumulator group;

N is an integer, and n＞0.

Beneficial effect: adopt phase factor combined circuit based on pile line operation, in process operation data, each clock signal obtains one group of data, legacy data in each grade registers group will move on in the next stage registers group according to the difference in path, obtain first signaling point and need 8 clock cycle, but when obtaining first signaling point, 12 register cells have filled up new data, that is: in the follow-up work process, only need 4 clock cycle just can obtain a collection of new signaling point, the speed in conjunction with the data of speed and IFFT unit output of phase factor is consistent, can not cause phenomenon of blocking in the data moving process.

Description of drawings

Fig. 1 is that time domain interweaves and cuts apart the schematic diagram of PTS, Fig. 2 is the parallel mobile schematic diagram of data in the cohesive process of phase factor, Fig. 3 is the schematic diagram that data cross moves in the cohesive process of phase factor, Fig. 4 is the structural representation of the phase factor combined circuit based on pile line operation of the present invention, Fig. 5 is the 1st, 2,3 and during 4n rising edge clock signal, when data transfer path schematic diagram, Fig. 6 are 4n+1 rising edge clock signal, the data transfer path schematic diagram, when Fig. 7 is 4n+2 rising edge clock signal, when data transfer path schematic diagram, Fig. 8 are 4n+3 rising edge clock signal, the data transfer path schematic diagram.

Embodiment

Embodiment one: present embodiment is described referring to Fig. 4.The described phase factor combined circuit of present embodiment based on pile line operation, it comprises clock unit 1, select signal generation unit 2, four multipliers, 12 registers and accumulator group ADD, wherein said 12 registers are divided into three grades, that is: first order registers group R1, second level registers group R2 and third level registers group R3, each grade registers group has four registers; Four accumulator ADD1, ADD2, ADD3, ADD4 are arranged among the accumulator group ADD;

Pending data multiply each other by four multipliers with four road phase factors respectively simultaneously, described four multipliers output signal to four register R11 of first order registers group R1 respectively, R12, R13, R14, four register R11 of described first order registers group R1, R12, R13, R14 outputs signal to four register R21 of second level registers group R2 respectively, R22, R23, R24, four register R21 of described second level registers group R2, R2, R23, R24 outputs signal to four register R31 of third level device storage R3 respectively, R32, R33, R34, four register R31 of described third level registers group R3, R32, R33, R34 outputs signal to four accumulator ADD1 of accumulator group ADD respectively, ADD2, ADD3, ADD4;

Clock unit 1 clock signal Clock gives and selects signal generation unit 2, three path select signals of described selection signal generation unit 2 outputs, be respectively: first path select signal Sel_0, second path select signal Sel_1 and the 3rd path select signal Sel_2, wherein first path select signal Sel_0 is used to control the signaling path between first order registers group R1 and the second level registers group R2; Second path select signal Sel_1 is used to control the signaling path between second level registers group R2 and the third level registers group R3; The 3rd path select signal Sel_2 is used to control the signaling path between third level registers group R3 and the accumulator;

Concern referring to table 1 between the input signal Clock of selection signal generation unit 2 and three path select signals of output:

Table 1

Be specially: when the 1st rising edge clock signal, the 2nd rising edge clock signal and the 3rd rising edge clock signal, three path select signals of output are 0;

When 4n rising edge clock signal, three path select signals of output are 1;

When 4n+1 rising edge clock signal, first path select signal Sel_0 of output is that 0, the second path select signal Sel_1 and the 3rd path select signal Sel_2 are 1,

In 4n+2 rising edge clock signal, it is 1 that first path select signal Sel_0 and second path select signal Sel_1 are 0, the three path select signal Sel_2;

In 4n+3 rising edge of clock signal, three first path select signal of path select signal Sel_0 of output, second path select signal Sel_1 and the 3rd path select signal Sel_2 are 0;

Described n is an integer, and n＞0;

When first path select signal Sel_0 is 0, be parallel path between first order registers group R1 and the second level registers group R2; When first path select signal Sel_0 is 1, be crossedpath between first order registers group R1 and the second level registers group R2; When second path select signal Sel_1 is 0, be parallel path between second level registers group R2 and the third level registers group R3; When second path select signal Sel_1 is 1, be crossedpath between second level registers group R2 and the third level registers group R3; When the 3rd path select signal Sel_2 is 0, be parallel path between third level registers group R3 and the accumulator group ADD; When the 3rd path select signal Sel_2 is 1, be crossedpath between third level registers group R3 and the accumulator group ADD.

Be meant for parallel path between first order registers group R1 described in the present embodiment and the second level registers group R2: i register R1i among the first order registers group R1 outputs signal to i register R2i among the registers group R2 of the second level.

Be meant for crossedpath between first order registers group R1 described in the present embodiment and the second level registers group R2: first register R11 among the first order registers group R1 outputs signal to the 3rd register R23 among the registers group R2 of the second level; Second register R12 among the first order registers group R1 outputs signal to the 4th register R24 among the registers group R2 of the second level; The 3rd register R13 among the first order registers group R1 outputs signal to first register R21 among the registers group R2 of the second level; The 4th register R14 among the first order registers group R1 outputs signal to second register R22 among the registers group R2 of the second level.

Be meant for parallel path between second level registers group R2 described in the present embodiment and the third level registers group R3: i register R2i among the registers group R2 of the second level outputs signal to i register R3i among the third level registers group R3.

Be meant for crossedpath between second level registers group R2 described in the present embodiment and the third level registers group R3: first register R21 among the registers group R2 of the second level outputs signal to the 4th register R34 among the third level registers group R3; Second register R22 among the registers group R2 of the second level outputs signal to first register R31 among the third level registers group R3; The 3rd register R23 among the registers group R2 of the second level outputs signal to second register R32 among the third level registers group R3; The 4th register R24 among the registers group R2 of the second level outputs signal to the 3rd register R33 among the third level registers group R3.

For being meant i register R3i among the third level registers group R3, parallel path outputs signal to i accumulator ADDi between third level registers group R3 described in the present embodiment and the accumulator group ADD.

Be meant for crossedpath between third level registers group R3 described in the present embodiment and the accumulator group ADD: first register R31 among the third level registers group R3 outputs signal to the 3rd accumulator ADD3; Second register R32 among the third level registers group R3 outputs signal to the 4th accumulator ADD4; The 3rd register R33 among the third level registers group R3 outputs signal to first accumulator ADD1; The 4th register R34 among the third level registers group R3 outputs signal to second accumulator ADD2.

When practical application, the signal input part based on the phase factor combined circuit of pile line operation of present embodiment is connected with the signal output part of IFFT circuit, and first group of data is in described IFFT circuit dateout sequence: x ₉₆, x ₃₂, x ₆₄, x ₀The time, the course of work of the described phase factor combined circuit based on pile line operation of present embodiment is:

When the 1st rising edge clock signal, the 2nd rising edge clock signal and the 3rd rising edge clock signal, select three path select signals of signal generation unit output: first path select signal Sel_0, second path select signal Sel_1 and the 3rd path select signal Sel_2 are 0, and the data transfer path of this moment is referring to shown in Figure 5;

When the 1st rising edge clock signal, pending data x ₀Simultaneously respectively with four phase factor d ₀ ^m, d ₁ ^m, d ₂ ^m, d ₃ ^mFour data of gained of multiplying each other successively are moved in four registers of first order registers group by parallel direction, that is: the data among R11, R12, R13 and the R14 are respectively x ₀d ₀ ^m, x ₀d ₁ ^m, x ₀d ₂ ^m, x ₀d ₃ ^m

When the 2nd rising edge clock signal, pending data x ₆₄Simultaneously respectively with four phase factor d ₀ ^m, d ₁ ^m, d ₂ ^m, d ₃ ^mFour data of gained of multiplying each other are moved into respectively in four registers of first order registers group by parallel direction, and promptly data are respectively x among R11, R12, R13, the R14 ₆₄d ₀ ^m, x ₆₄d ₁ ^m, x ₆₄d ₂ ^m, x ₆₄d ₃ ^m, the legacy data among four register R11, R12, R13 and the R14 in the first order registers group is moved into four registers among the registers group R2 of the second level respectively simultaneously, that is: the data among R21, R22, R23, the R24 are respectively x ₀d ₀ ^m, x ₀d ₁ ^m, x ₀d ₂ ^m, x ₀d ₃ ^m

When the 3rd rising edge clock signal, pending data x ₃₂Simultaneously respectively with four phase factor d ₀ ^m, d ₁ ^m, d ₂ ^m, d ₃ ^mFour data of gained of multiplying each other are moved into respectively in four registers of first order registers group R1 by parallel direction, that is: data are respectively x among R11, R12, R13, the R14 ₃₂d ₀ ^m, x ₃₂d ₁ ^m, x ₃₂d ₂ ^m, x ₃₂d ₃ ^mThe legacy data of four registers among the first order registers group R1 is moved into respectively in four registers of second level registers group R2 simultaneously, legacy data in four registers among the registers group R2 of the second level is moved into respectively in four registers of third level registers group R3, that is: the data among four register R21, R22, R23 and the R24 among the second level registers group R2 are respectively x ₆₄d ₀ ^m, x ₆₄d ₁ ^m, x ₆₄d ₂ ^m, x ₆₄d ₃ ^m, the data among four register R31, R32, R33 and the R34 among the third level registers group R3 are respectively x ₀d ₀ ^m, x ₀d ₁ ^m, x ₀d ₂ ^m, x ₀d ₃ ^m

When the 4th rising edge clock signal, the transmission path of data keeps the state of the 3rd rising edge clock signal constant, and data transmission procedure is: pending data x ₉₆Simultaneously respectively with four phase factor d ₀ ^m, d ₁ ^m, d ₂ ^m, d ₃ ^mFour data of gained of multiplying each other are moved into respectively in four registers of first order registers group R1 by parallel direction, and promptly data are respectively x among R11, R12, R13, the R14 ₉₆x ₀ ^m, x ₉₆d ₁ ^m, x ₉₆d ₂ ^m, x ₉₆d ₃ ^mThe legacy data of four registers among the first order registers group R1 is moved into respectively in four registers of second level registers group R2 simultaneously, legacy data in four registers among the registers group R2 of the second level is moved into respectively in four registers of third level registers group R3, data in four registers of third level registers group R3 are moved into respectively in four accumulators, that is: the data among four register R21, R22, R23 and the R24 among the second level registers group R2 are x ₃₂d ₀ ^m, x ₃₂d ₁ ^m, x ₃₂d ₂ ^m, x ₃₂d ₃ ^m, the data among four register R31, R32, R33 and the R34 among the third level registers group R3 are respectively x ₆₄d ₀ ^m, x ₆₄d ₁ ^m, x ₆₄d ₂ ^m, x ₆₄d ₃ ^m, the data in four accumulators are respectively x ₀d ₀ ^m, x ₀d ₁ ^m, x ₀d ₂ ^m, x ₀d ₃ ^m

At this moment, select three path select signals of signal generation unit output to be: first path select signal Sel_0, second path select signal Sel_1 and the 3rd path select signal Sel_2 are 1;

After the 4th rising edge clock signal, the transmission path of data changes according to the variation of path select signal, that is: the path between first order registers group R1 and the second level registers group R2 becomes crossedpath, path between second level registers group R2 and the third level registers group R3 becomes crossedpath, path between third level registers group R3 and the accumulator group ADD is a crossedpath, and data transfer path is referring to shown in Figure 6;

When the 5th rising edge clock signal, the transmission path of data is according to the transmission of the path after the 4th rising edge clock signal, data transmission procedure is that data transmission procedure is: the data in four registers of former first order registers group R1 are moved into respectively in four registers among the registers group R2 of the second level according to crossedpath, the data of four registers in the registers group of the described second level move in four registers of third level registers group R3 respectively according to crossedpath, data in four registers of described third level registers group R3 are moved into respectively in four accumulators according to crossedpath and add up, data move to be finished, deposit the 5th group of new data in four registers among the first order registers group R1 in, four register R21 among the registers group R2 of the second level, R22, data among R23 and the R24 are respectively: x ₉₆d ₂ ^m, x ₉₆d ₃ ^m, x ₉₆d ₀ ^m, x ₉₆d ₁ ^m, data are respectively x among four register R31, R32, R33 and the R34 among the third level registers group R3 ₃₂d ₁ ^m, x ₃₂d ₂ ^m, x ₃₂d ₃ ^m, x ₃₂d ₀ ^m, the data among four accumulator ADD1, ADD2, ADD3 and the ADD4 are respectively: x ₆₄d ₂ ^m+ x ₀d ₀ ^m, x ₆₄d ₃ ^m+ x ₀d ₁ ^m, x ₆₄d ₀ ^m+ x ₀d ₂ ^m, x ₆₄d ₁ ^m+ x ₀d ₃ ^m

At this moment, select three path signals of signal generation unit output to be: first path select signal Sel_0 is that 0, the second path select signal Sel_1 and the 3rd path select signal Sel_2 are 1;

After the 5th rising edge clock signal, the transmission path of data changes according to the variation of path select signal, that is: the path between first order registers group R1 and the second level registers group R2 reverts to parallel path, and other path remains unchanged, and still is crossedpath; Data transfer path is referring to shown in Figure 7;

When the 6th rising edge clock signal, the transmission path of data is according to the transmission of the path after the 5th rising edge clock signal, data transmission procedure is: the data in four registers of former second level registers group R2 are moved into respectively in four registers among the third level registers group R3 according to crossedpath, data in four registers of described third level registers group R3 are moved into respectively in four accumulators according to crossedpath and add up, data move the back: deposit the 6th group of new data in four registers among the first order registers group R1 in, data in four registers among the registers group R2 of the second level are the data among the former first order registers group R1, four register R31 among the third level registers group R3, R32, data among R33 and the R34 are respectively: x ₉₆d ₃ ^m, x ₉₆d ₀ ^m, x ₉₆d ₁ ^m, x ₉₆d ₂ ^m, the data among four accumulator ADD1, ADD2, ADD3 and the ADD4 are respectively: x ₃₂d ₃ ^m+ x ₆₄d ₂ ^m+ x ₀d ₀ ^m, x ₃₂d ₀ ^m+ x ₆₄d ₃ ^m+ x ₀d ₁ ^m, x ₃₂d ₁ ^m+ x ₆₄d ₀ ^m+ x ₀d ₂ ^m, x ₃₂d ₂ ^m+ x ₆₄d ₁ ^m+ x ₀d ₃ ^m

At this moment, select three path signals of signal generation unit output to be: it is 1 that first path select signal Sel_0 and second path select signal Sel_1 are 0, the three path select signal Sel_2;

After the 6th rising edge clock signal, data transfer path changes according to the variation of path select signal, that is: the path between second level registers group R2 and the third level registers group R3 becomes parallel path, and other path is constant, and the transmission path of the data of this moment is referring to shown in Figure 8;

When the 7th rising edge clock signal, the transmission path of data is according to the transmission of the path after the 6th rising edge clock signal, data transmission procedure is that data transmission procedure is: deposit the 7th group of new data in four registers among the first order registers group R1 in, data in four registers among the registers group R2 of the second level are the data of former first order registers group R1, data in four registers among the third level registers group R3 are the data in four registers of former second level registers group R2, four accumulator ADD1, ADD2, data among ADD3 and the ADD4 are respectively: x ₉₆d ₁ ^m+ x ₃₂d ₃ ^m+ x ₆₄d ₂ ^m+ x ₀d ₀ ^m, x ₉₆d ₂ ^m+ x ₃₂d ₀ ^m+ x ₆₄d ₃ ^m+ x ₀d ₁ ^m, x ₉₆d ₃ ^m+ x ₃₂d ₁ ^m+ x ₆₄d ₀ ^m+ x ₀d ₂ ^m, x ₉₆d ₀ ^m+ x ₃₂d ₂ ^m+ x ₆₄d ₁ ^m+ x ₀d ₃ ^m, obtain first signaling point x ₀, x ₃₂, x ₆₄, x ₉₆

At this moment, select three first path select signal of path signal Sel_0, second path select signal Sel_1 and the 3rd path select signal Sel_2 of the output of signal generation unit to be 0;

After the 7th rising edge clock signal, the transmission path of data changes according to path select signal, that is: the path between third level registers group R3 and the accumulator group ADD becomes parallel path, and the data transfer path of this moment returns to the state of Fig. 4;

Since the 8th rising edge clock signal, the transmission path of data repeats the change procedure of transmission path of the data of the 4th, 5,6,7 clock cycle, obtain other signaling point, that is: obtain a collection of new signaling point after 4 clock cycle, in the data transmission procedure, phase factor is identical with the data speed of IFFT circuit output in conjunction with speed, has solved the problem of data jamming.

In the present embodiment, when the path is parallel path between every two-stage register, realize storage, when the path between every two-stage register is crossedpath, realize data accumulation.

In the present embodiment, when n rising edge clock signal, select the path select signal of signal generation unit output, described path select signal realizes that to the control variation of the transmission path of data promptly the path just changes behind n rising edge clock signal.

Embodiment two: the difference of the described phase factor combined circuit based on pile line operation of this embodiment and embodiment one is, i accumulator ADDi is made up of adder and accumulator registers R4i, third level registers group R3 outputs signal to the adder in the accumulator, exports to described accumulator registers R4i again after the output signal addition of described adder with input signal and accumulator registers.

In the present embodiment between the registers group at different levels and the data path between third level registers group and the accumulator change step by step according to the needs of system or change simultaneously, to form pile line operation, made full use of the space of register, saved system resource.

Claims (2)

1. based on the phase factor combined circuit of pile line operation, it is characterized in that it comprises clock unit (1), selects signal generation unit (2), four multipliers, 12 registers and accumulator group ADD, wherein said 12 registers are divided into three grades, that is: first order registers group R1, second level registers group R2 and third level registers group R3, each grade registers group has four registers; Four accumulator ADD1, ADD2, ADD3, ADD4 are arranged among the accumulator group ADD;

Pending data multiply each other by four multipliers with four road phase factors respectively simultaneously, described four multipliers output signal to four register R11 of first order registers group R1 respectively, R12, R13, R14, four register R11 of described first order registers group R1, R12, R13, R14 outputs signal to four register R21 of second level registers group R2 respectively, R22, R23, R24, four register R21 of described second level registers group R2, R22, R23, R24 outputs signal to four register R31 of third level device storage R3 respectively, R32, R33, R34, four register R31 of described third level registers group R3, R32, R33, R34 outputs signal to four accumulator ADD1 of accumulator group ADD respectively, ADD2, ADD3, ADD4;

Clock unit (1) clock signal Clock gives and selects signal generation unit (2), three path select signals of described selection signal generation unit (2) output, be respectively: first path select signal Sel_0, second path select signal Sel_1 and the 3rd path select signal Sel_2, wherein first path select signal Sel_0 is used to control the signaling path between first order registers group R1 and the second level registers group R2; Second path select signal Sel_1 is used to control the signaling path between second level registers group R2 and the third level registers group R3; The 3rd path select signal Sel_2 is used to control the signaling path between third level registers group R3 and the accumulator group ADD;

Pass between the input signal Clock of selection signal generation unit (2) and three path select signals of output is:

When first path select signal Sel_0 is 0, be parallel path between first order registers group R1 and the second level registers group R2; When first path select signal Sel_0 is 1, be crossedpath between first order registers group R1 and the second level registers group R2; When second path select signal Sel_1 is 0, be parallel path between second level registers group R2 and the third level registers group R3; When second path select signal Sel_1 is 1, be crossedpath between second level registers group R2 and the third level registers group R3; When the 3rd path select signal Sel_2 is 0, be parallel path between third level registers group R3 and the accumulator group ADD; When the 3rd path select signal Sel_2 is 1, be crossedpath between third level registers group R3 and the accumulator group ADD;

N is an integer, and n＞0;

Be meant for parallel path between first order registers group R1 and the second level registers group R2: i register R1i among the first order registers group R1 outputs signal to i register R2i among the registers group R2 of the second level, i=1,2,3,4;

Be meant for crossedpath between first order registers group R1 and the second level registers group R2: first register R11 among the first order registers group R1 outputs signal to the 3rd register R23 among the registers group R2 of the second level; Second register R12 among the first order registers group R1 outputs signal to the 4th register R24 among the registers group R2 of the second level; The 3rd register R13 among the first order registers group R1 outputs signal to first register R21 among the registers group R2 of the second level; The 4th register R14 among the first order registers group R1 outputs signal to second register R22 among the registers group R2 of the second level;

Be meant for parallel path between second level registers group R2 and the third level registers group R3: i register R2i among the registers group R2 of the second level outputs signal to i register R3i among the third level registers group R3;

Be meant for crossedpath between second level registers group R2 and the third level registers group R3: first register R21 among the registers group R2 of the second level outputs signal to the 4th register R34 among the third level registers group R3; Second register R22 among the registers group R2 of the second level outputs signal to first register R31 among the third level registers group R3; The 3rd register R23 among the registers group R2 of the second level outputs signal to second register R32 among the third level registers group R3; The 4th register R24 among the registers group R2 of the second level outputs signal to the 3rd register R33 among the third level registers group R3;

For being meant i register R3i among the third level registers group R3, parallel path outputs signal to i accumulator ADDi between third level registers group R3 and the accumulator group ADD;

Be meant for crossedpath between third level registers group R3 and the accumulator group ADD: first register R31 among the third level registers group R3 outputs signal to the 3rd accumulator ADD3; Second register R32 among the third level registers group R3 outputs signal to the 4th accumulator ADD4; The 3rd register R33 among the third level registers group R3 outputs signal to first accumulator ADD1; The 4th register R34 among the third level registers group R3 outputs signal to second accumulator ADD2.

2. the phase factor combined circuit based on pile line operation according to claim 1, it is characterized in that i accumulator ADDi is made up of adder and accumulator registers R4i, third level registers group R3 outputs signal to the adder in the accumulator, exports to accumulator registers R4i again after the output signal addition of described adder with input signal and accumulator registers R4i.

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