CN101540315B - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN101540315B CN101540315B CN2008100830079A CN200810083007A CN101540315B CN 101540315 B CN101540315 B CN 101540315B CN 2008100830079 A CN2008100830079 A CN 2008100830079A CN 200810083007 A CN200810083007 A CN 200810083007A CN 101540315 B CN101540315 B CN 101540315B
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Abstract
The invention relates to a semiconductor device and a forming method thereof. The semiconductor device comprises a substrate on which an active region is defined, a shallow trench isolator positioned on the substrate and directly surrounding the active region, a grid electrode, a source electrode and a drain electrode which are positioned on the active region, and a hard mask positioned above thejuncture of the shallow trench isolator and the active region.
Description
Technical field
The present invention is about a kind of semiconductor device and forming method thereof, particularly about have shielded shallow trench isolation from semiconductor device and forming method thereof.
Background technology
In order to increase the carrier mobility of grid groove in the semiconductor device, technology generally uses the mode of adjusting the grid groove adaptability to changes to increase or reduce the adaptability to changes of grid groove, the carrier mobility of finally promoting grid groove now.For example, in the PMOS element, can form one group of groove, wait the silicon substrate that replaces part in wherein inserting the SiGe material again in the regions and source of grid groove both sides.So utilize the big effect of Ge atomic ratio Si atomic volume to cause strained silicon (strained-Si), in grid groove, producing extra compression stress, and can promote the carrier mobility of grid groove.
In Fig. 1 example Prior Art, use the SiGe layer to increase the schematic diagram of grid groove adaptability to changes technology.As shown in Figure 1, have P-type mos 101 and N type metal oxide semiconductor 102 on the silicon substrate 110 simultaneously.At first, the cap layer 103 that forms a patterning on silicon substrate 110 covers N type metal oxide semiconductor 102, and under the protection of cap layer 103, the regions and source of P-type mos 101 is carried out technologies such as etching, cleaning.
Afterwards, as shown in Figure 2, the SiGe layer 111 that forms with extension replaces the silicon substrate 110 of part in the regions and source of P-type mos 101 again.At this moment, can be because steps such as aforementioned etching or cleaning cause damage 131 by the shallow trench isolation that oxide constituted from 130 edge.Secondly, when backfill SiGe layer 111, because the SiGe material can be grown up along the intrinsic lattice direction of silicon substrate 110, and can't fill up fully, so can form slit 132 between 130 at the active region 120 and the shallow trench isolation of P-type mos 101.In addition, as shown in Figure 3, when removing cap layer 103, can damage shallow trench isolation once more again from 130.Damage 131 is added in the slit 132 that produces, make that not only increasing the space that the purpose of grid groove compression stress defined by slit 131 with SiGe layer 111 seriously offsets, and at follow-up metal silicide (the self-aligned silicide that aims at voluntarily, during salicide) step, metal silicide also may be along the slit 131 direction in silicon substrate 110, extend, cause other unmanageable harmful effects.
In addition, because being adjacent to the shallow trench isolation of active region 120 is not covered by cap layer 103 from 130, therefore in steps such as aforesaid etching or cleaning, also can cause the loss of its end face, make follow-up after removal covers cap layer 103 on the active region 120, each shallow trench isolation is not contour with respect to substrate surface from 130 end face, that is the shallow trench isolation that is adjacent to active region 120 can be lower than the shallow trench isolation that is adjacent to active region 121 from 130 end face from 130 end face, increases the degree of difficulty of subsequent technique.
So need a kind of semiconductor device and technology of novelty, solve this problem, make in the etching regions and source, when cleaning, removing technologies such as cap layer, can not sow discord and gap, keep the adaptability to changes and the carrier mobility of promoting grid groove of grid groove by this at active region and shallow trench isolation.
Summary of the invention
The present invention is in the semiconductor device that provides a kind of novelty.This semiconductor device has the mask that protection active region and shallow trench isolation are sowed discord the intersection of fragility, so in the etching regions and source, when cleaning, removing step such as cap layer, can avoid generating the slit.This mask can thoroughly solve the difficult problem that can meet with in the Prior Art.Both can keep the purpose of using epitaxial loayer to change grid groove stress on the one hand, guarantee also on the other hand that metal silicide correctly formed as can as expecting.
The present invention at first provides a kind of semiconductor device, includes substrate, the shallow trench isolation hard mask from, active region, grid, source electrode, drain electrode and protection usefulness.The definition of going up of substrate has this active region, shallow trench isolation is offed normal on substrate and directly is surrounded by source region, the canopy utmost point is positioned on the active region, source electrode is arranged in the active region of grid one side, drain electrode is arranged in the active region of grid opposite side, hard mask then be positioned at shallow trench isolation from the top of active region intersection, source electrode and drain electrode are formed by epitaxial loayer, this epitaxial loayer replaces the appropriate section of described substrate.
The present invention provides a kind of formation method for semiconductor again, and substrate at first is provided, the shallow trench isolation that definition has active region and directly surrounds this active region on this substrate from.Next forms grid, and it is positioned on the active region.Then form hard mask, make this hard mask be positioned at shallow trench isolation from the top of active region intersection.Form source electrode and drain electrode with epitaxial loayer, make this source/drain lay respectively at a side of grid, this epitaxial loayer replaces the appropriate section of substrate.Formed semiconductor can comprise two kinds or above semiconductor device respectively, and hard mask can be the extension of adjacent gate, or is electrically connected with the grid of self.
Description of drawings
Fig. 1-3 example formerly in the skill, uses the SiGe layer to increase the schematic diagram of grid groove adaptability to changes technology.
Fig. 4-9 discloses the method that the present invention forms semiconductor device in addition.
One preferred embodiment of the hard mask shape of Figure 10-11 illustration the present invention.
The multiple variation of hard mask in Figure 12 illustration semiconductor device of the present invention.
The cutaway view of Figure 13 illustration semiconductor device of the present invention.
The main element symbol description
101P type metal oxide semiconductor 102N type metal oxide semiconductor
103 cap layers, 110 silicon substrates
131 damages of 132 slits
200 semiconductor 201P type metal oxide semiconductors
202N type metal oxide semiconductor 203 cap layers
210 substrate 211SiGe layers
220/222 active region, 221 trench regions
230 shallow trench isolations are from 240 grids
242 clearance walls, 250 source electrodes
260 drain electrodes, 270 hard masks
271 dummy grids, 272 clearance walls
300 semiconductor devices, 310 substrates
320 active regions, 321 second active regions
330 first shallow trench isolations from 331 second shallow trench isolations from
340P type metal oxide semiconductor grid 342 first clearance walls
345N type metal oxide semiconductor grid 350 source electrodes
360 drain electrodes of 351 source electrodes
361 drain electrodes, 370/371 hard mask
500P type metal oxide semiconductor 550N type metal oxide semiconductor
510/560 active region, 520/570 grid
531/532/581/582 hard mask
Embodiment
The invention reside in semiconductor device and technology that a kind of novelty is provided, when solving the etching regions and source, clean and removing step such as cap layer, can sow discord the problem in fragile intersection formation slit along active region and shallow trench isolation.So, both can keep the purpose of using epitaxial loayer to change grid groove stress on the one hand, and can guarantee also that on the other hand metal silicide correctly formed as can as expecting.
Please refer to Fig. 4-10, Fig. 4-10 forms a preferred embodiment of semiconductor device method for the present invention.It discloses on active region 220 respectively at substrate 210, the active region 222 simultaneously or successively forms two kinds or above semiconductor device, for example P-type mos 201 and N type metal oxide semiconductor 202, and this two metal-oxide semiconductor (MOS) at least one be strain silicon metal oxide semiconductor (strained-Si MOS).Be that example explains now with the P-type mos 201 that forms N type metal oxide semiconductor 202 and tool strained silicon structure, but the present invention is not as limit, all equalizations of doing according to claim of the present invention change and modify, for example CMOS of the P type of strained silicon structure, N type metal oxide semiconductor etc. also all should belong to covering scope of the present invention.
As shown in Figure 4, the present invention forms the method for semiconductor device 200, and substrate 210 at first is provided.Definition has active region 220, active region 222 on the substrate 210, and the shallow trench isolation that directly is surrounded by source region 220,222 is from 230.Wherein, substrate 210 is generally the semiconductor material, for example monocrystalline silicon, the silicon-coated insulated semiconductor-based ends such as (SOI) etc.Shallow trench isolation comprises insulating material usually from 230, and Si oxide is for example known by known this skill person and intelligence the knowledgeable usually from 230 method and form shallow trench isolation, does not add to give unnecessary details at this.
Continue, as shown in Figure 5, deposit in regular turn, related process such as patterning, to form required grid 240 structures of P-type mos 201 and N type metal oxide semiconductor 202 respectively on active region 220, active region 222, it can include gate dielectric, grid conducting layer, clearance wall 242.Depending on the circumstances or the needs of the situation, clearance wall 242 can be a kind of provisional clearance wall (disposablespacer).In other words, if when clearance wall 242 is provisional clearance walls, clearance wall 242 can (selective epitaxial growth promptly be removed after SEG) technology is finished at selective epitaxial growth.
It should be noted that; this preferred embodiment meeting while forms the P-type mos 201 of tool strained silicon structure in desire active region 220 forms dummy grid (dummy gate) 271 with shallow trench isolation above 230 intersections, as the hard mask of protection usefulness.That is when making the required grid lead optical mask pattern of P-type mos 201 and N type metal oxide semiconductor 202, just cook up placement position in the lump as the dummy grid 271 of hard mask.In addition, the present invention more can utilize the rule of special mathematical computations to decide the position of hard mask dummy grid 271 again, therefore, dummy grid 271 includes the structure of gate dielectric, grid conducting layer, clearance wall 272 etc. similarly, and can be positioned at active region 220 and the top of shallow trench isolation from 230 intersections accurately.
Next, as shown in Figure 6, carry out suitable ion implantation technology, drain 260 in order to the source electrode 250/ that forms P-type mos 201, and lay respectively at a side of the grid 240 of P-type mos 201.The position that note that source electrode 250 and drain electrode 260 is any appointment, decides on electrical operation, in addition, before forming clearance wall 242, also can carry out another ion implantation technology earlier, in order to form the lightly doped drain (LDD) of P-type mos 201.
Then, can continue in silicon substrate 210, to set up stressor layers.For example, the cap layer 203 that forms patterning earlier on silicon substrate 210 covers N type metal oxide semiconductor 202, as shown in Figure 7.Come again, as shown in Figure 8, under the protection of cap layer 203, technologies such as etching, cleaning are carried out in source electrode 250/ drain electrode 260 zones of P-type mos 201.And again with selective epitaxial growth (selective epitaxial growth, SEG) technology, form the silicon substrate 210 of part in source electrode 250/ drain electrode 260 zones that required SiGe layer 211 replaces P-type mos 201, with the compression stress of increase P-type mos 201 grid grooves, and then the carrier mobility in the raising grid groove.
In this preferred embodiment; owing to can be subjected to protection from 230 edge as the dummy grid 271 of hard mask with the shallow trench isolation of active region 220 adjacency; therefore; when technologies such as the etching in source electrode 250/ drain electrode 260 zones of carrying out P-type mos 201, cleaning, just can not be subjected to step such as aforementioned etching or cleaning by the shallow trench isolation that oxide constituted from 230 edge and cause damage.In addition, as shown in Figure 9, when removing cap layer 203, dummy grid 271 of the present invention can make that still shallow trench isolation avoids damaging once more from 230.So shallow trench isolation can not produce the slit from 230 with the intersection of substrate 210, shallow trench isolation is from 230 also not damageds.So can effectively keep the compression stress that SiGe layer 211 produces in grid groove, also can guarantee when aiming at the step of metal silicide (Salicide) voluntarily, can correctly form the metal silicide of being desired follow-up.In addition; owing to be subjected to not being subjected to the etching or the injury of cleaning from 230 end face as the protection of the dummy grid 271 of hard mask with the shallow trench isolation of active region 220 adjacency; therefore; each shallow trench isolation on the substrate 210 is from 230 end face; that is; there is the shallow trench isolation that is adjacent to active region 220 that is subjected to as dummy grid 271 protection of hard mask contour with the shallow trench isolation that is adjacent to active region 220 that is covered by cap layer 203, and still keeps contour with respect to substrate 210 surfaces from 230 end face from 230 end face.
It should be noted that in preferred embodiment of the present invention shape and layout (layout) pattern of regarding the dummy grid 271 of hard mask can have multiple mode.Please refer among Figure 10 illustrated, rectangular as the dummy grid 271 of hard mask, strip for example, and extend with the intersection of active region 220 from 230 along shallow trench isolation.The trench region 221 of inserting strain gauge material promptly is arranged in active region 220.For example, when if the width that grid 240 and dummy grid are 271 is 0.14 micron (μ m), trench region 221 itself can have the width of 0.11 μ m, making that the border of trench region 221 is 0.03 μ m from the dummy grid 271 as hard mask, is adjacent contact with shallow trench isolation from 230 in this situation lower groove zone 221.
On the other hand, please refer to the illustrated hard mask of Figure 11.Be polygon as the dummy grid 271 of hard mask among Figure 12, ㄇ font for example not only extends with the intersection of active region 220 from 230 along shallow trench isolation, also cover simultaneously shallow trench isolation from 230 with at least one corner part of active region 220.
In addition, cooperate actual process and various semiconductor layout designs, hard mask of the present invention can also have multiple variation.For example, please refer to Figure 12, each other P-type mos 500 includes source region 510/560 and grid 520/570 with N type metal oxide semiconductor 550.Its each other hard mask 531/532/581/582 can be the extension of adjacent gate, or is electrically connected with adjacent gate.For example, the hard mask 531/532 of P-type mos 500 is from the extension of other contiguous but different grids.At this moment, the adjacent gate distortion strengthens its width, and is covered the intersection of the shallow trench isolation of P-type mos 500 from (figure does not show) and active region 510.If hard mask is the extension of adjacent gate, then the layout patterns of each grid should meet design rule, for example, meets the rule of optical nearing correction (Optical Proximity Correction).
On the other hand, and for example shown in Figure 12, the hard mask of semiconductor element can also be the extension of self grid, or is electrically connected with self grid.For example, the hard mask 581 of N type metal oxide semiconductor 550 is from the contiguous but extension of different grids, and hard mask 582 then is the extension from self grid.At this moment, contiguous/self grid distortion strengthens its width, and the shallow trench isolation that is covered N type metal oxide semiconductor 550 from (figure does not show) intersection with active region 560.The width of hard mask can be different than at least one the width in self grid and the adjacent gate.Similarly; owing to be not subjected to the etching or the injury of cleaning from the protection that is subjected to cap layer or hard mask with the shallow trench isolation of each active region adjacency; therefore; any two adjacent shallow trench isolations from; that is; have the shallow trench isolation that is subjected to hard mask protection of the present invention from the shallow trench isolation that is not subjected to hard mask protection but is covered by cap layer from end face contour, and still keep contour with respect to substrate surface.
In sum; this preferred embodiment is when forming required wire pattern; while forms dummy grid at active region and the shallow trench isolation that desire forms the metal-oxide semiconductor (MOS) of tool strained silicon structure above intersection; hard mask as protection usefulness; therefore not only can effectively protect with the shallow trench isolation of active region adjacency from seam crossing be not subjected to the etching or the injury of cleaning; each shallow trench isolation that more can significantly reduce on the substrate is subjected to the etching or the impairment of cleaning from end face, and still keeps contour with respect to substrate surface.
In addition, semiconductor device of the present invention and technology, also can be used in any semiconductor device with grid groove stress, for example use with the N type metal oxide semiconductor of tool stretching stress extensions such as the P-type mos that forms tool compression stress extension such as SiGe, SiC or comprise the P type of strained silicon structure, the CMOS of N type metal oxide semiconductor etc., also all should belong to covering scope of the present invention, and hard mask also can not be the extension of grid, and material, technology also can be different.
Please refer to Figure 13, the cutaway view of another preferred embodiment of Figure 13 illustration semiconductor device of the present invention.Semiconductor device 300 of the present invention comprises substrate 310, definition has first active region, 320/ second active region 321 on the substrate 310, in order to hold each element of semiconductor device 300 of the present invention respectively, sharp as P-type mos 301 and N type metal oxide semiconductor 302.Simultaneously, first shallow trench isolation is positioned on the substrate 310 from 330, and first active region 320 is directly surrounded, and second shallow trench isolation is positioned on the substrate 310 from 331, and second active region 321 is directly surrounded.Wherein, substrate 310 is generally the semiconductor material, for example monocrystalline silicon, the silicon-on-insulator semiconductor-based ends such as (SOI), and first shallow trench isolation comprises insulating material usually from 330,331, for example Si oxide etc.
First active region 320 is P-type mos 301 whereabouts of the present invention, and it includes grid 340, source electrode 350 and drain electrode 360.Grid 340 is positioned on first active region 320, and it includes gate dielectric (not shown), grid conducting layer (not shown), first clearance wall 342 again.On the one hand, source electrode 350 is arranged in first active region 320, and a side of adjacent gate 340.On the other hand, draining 360 is arranged in first active region 320, and the opposite side of adjacent gate 340.The position that note that source electrode 350 and drain electrode 360 is any appointment.N type metal oxide semiconductor 302 in second active region 321 then includes grid 345, source electrode 351 and drain electrode 361.Depending on the circumstances or the needs of the situation, first clearance wall 342 can be a kind of provisional clearance wall (disposable spacer).Change speech, if when first clearance wall 342 is provisional clearance walls, first clearance wall 342 can promptly be removed after selective epitaxial growth process is finished.
It should be noted that, because in this preferred embodiment, P-type mos 301 is the metal-oxide semiconductor (MOS) that a desire forms the tool strained silicon structure, therefore above substrate 310 intersections of first shallow trench isolation in 330 and first active region 320, also be provided with hard mask 370,371 in addition, be used for covering the juncture area of first shallow trench isolation from 320 of 330 and first active regions.Hard mask 370,371 can comprise to silicon base and cap layer etch process and cleaning step have repellence material, the material of silicon oxide compound, nitrogen silicon compound, photoresist etc. for example.Moreover this preferred embodiment can also use the rule of special mathematical computations (ultra mathematical calculation) to decide the position of hard mask 370,371.In addition, the hard mask 370,371 of this preferred embodiment can be formed at before the step of preparation cap layer, afterwards or simultaneously, and the shape and layout (layout) pattern of hard mask 370,371 can have multiple mode, shown in Figure 10-12.All the other preparation extensions and autotype aligning metal silicide step are identical with previous embodiment, do not add to give unnecessary details at this.
Because the present invention forms hard mask at active region and the shallow trench isolation that desire forms the metal-oxide semiconductor (MOS) of tool strained silicon structure above intersection; therefore not only can effectively protect with the shallow trench isolation of active region adjacency from seam crossing be not subjected to the etching or the injury of cleaning; each shallow trench isolation that more can significantly reduce on the substrate is subjected to the etching or the impairment of cleaning from end face, and make each shallow trench isolation from end face still keep contour with respect to substrate surface.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (20)
1. semiconductor device comprises:
Substrate, definition has first active region on it;
First shallow trench isolation from, be positioned on this substrate and directly surround this first active region;
First grid is positioned on this first active region;
First source electrode, be arranged in this first grid a side this first active region and form by epitaxial loayer, this epitaxial loayer replaces the appropriate section of described substrate;
First drain electrode, be arranged in this first grid opposite side this first active region and form by epitaxial loayer, this epitaxial loayer replaces the appropriate section of described substrate; And
Hard mask, be positioned at this first shallow trench isolation from the top of this first active region intersection.
2. semiconductor device as claimed in claim 1, wherein this hard mask be rectangle and along this first shallow trench isolation from extending with the intersection of this first active region.
3. semiconductor device as claimed in claim 1, wherein this hard mask be the ㄇ font and cover this first shallow trench isolation from at least one corner of this first active region.
4. semiconductor device as claimed in claim 1, further comprise second active region, around second shallow trench isolation of this second active region from and be located at second metal-oxide semiconductor (MOS) that comprises second grid in this second active region, wherein this first shallow trench isolation from, this first grid, this first source electrode and this first drain electrode forms PMOS together and this second metal-oxide semiconductor (MOS) is NMOS.
5. semiconductor device as claimed in claim 1, wherein this hard mask is electrically connected with this first grid.
6. semiconductor device as claimed in claim 4, wherein this hard mask is electrically connected with this second grid.
7. semiconductor device as claimed in claim 4, wherein this first shallow trench isolation from this second shallow trench isolation from contour with respect to this substrate surface.
8. semiconductor device as claimed in claim 1, wherein the position of this hard mask meets the rule of special mathematical computations.
9. semiconductor device as claimed in claim 1, wherein this hard mask comprises dummy grid and clearance wall.
10. semiconductor device as claimed in claim 4, wherein the width of this hard mask is different with in this second grid at least one than this first grid.
11. one kind forms method for semiconductor, comprises:
Substrate is provided, first shallow trench isolation that this substrate defines first active region and directly surrounds this first active region from;
Form first grid, it is positioned on this first active region;
Form hard mask, its be positioned at this first shallow trench isolation from the top of this first active region intersection; And
Form first source electrode and first drain electrode with epitaxial loayer, lay respectively at a side of this first grid, this epitaxial loayer replaces the appropriate section of described substrate.
12. as the method for claim 11, wherein this hard mask is a rectangle, and extends from the intersection with this first active region along this first shallow trench isolation.
13. as the method for claim 11, wherein this hard mask is the ㄇ font, and cover this first shallow trench isolation from at least one corner of this first active region.
14. the method as claim 11 further comprises:
Form second active region, around second shallow trench isolation of this second active region from and be arranged in second metal-oxide semiconductor (MOS) that this second active region comprises second grid, make this first shallow trench isolation from, this first grid, this first source electrode and this first drain electrode forms PMOS together and this second metal-oxide semiconductor (MOS) forms NMOS.
15. as the method for claim 11, wherein this hard mask is electrically connected with this first grid.
16. as the method for claim 14, wherein this hard mask is electrically connected with this second grid.
17. as the method for claim 14, wherein this first shallow trench isolation from this second shallow trench isolation from contour with respect to this substrate surface.
18. the method as claim 11 further comprises:
Use special mathematical computations to determine the position of this hard mask.
19. as the method for claim 11, wherein this hard mask comprises dummy grid and clearance wall.
20. as the method for claim 14, wherein the width of this hard mask is different with in this second grid at least one than this first grid.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100830079A CN101540315B (en) | 2008-03-17 | 2008-03-17 | Semiconductor device and forming method thereof |
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| CN2008100830079A CN101540315B (en) | 2008-03-17 | 2008-03-17 | Semiconductor device and forming method thereof |
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| CN101540315A CN101540315A (en) | 2009-09-23 |
| CN101540315B true CN101540315B (en) | 2010-12-08 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102299074B (en) * | 2010-06-22 | 2013-04-17 | 中国科学院微电子研究所 | Semiconductor device and forming method thereof |
| CN102315152A (en) * | 2010-07-01 | 2012-01-11 | 中国科学院微电子研究所 | Isolation region, semiconductor device and forming method thereof |
| CN102456739A (en) * | 2010-10-28 | 2012-05-16 | 中国科学院微电子研究所 | Semiconductor structure and forming method thereof |
| CN102412251B (en) * | 2011-03-30 | 2013-10-02 | 上海华力微电子有限公司 | Semiconductor device and method for improving carrier mobility of transistor |
| CN103681500B (en) * | 2012-09-12 | 2016-04-27 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor device |
| CN103681264B (en) * | 2012-09-26 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor device and the forming method of MOS transistor |
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