CN101547018A

CN101547018A - Method and device for realizing filtering extraction of multiaerial system

Info

Publication number: CN101547018A
Application number: CN200810103001A
Authority: CN
Inventors: 熊军; 赵天良; 高华; 柴旭荣; 周志国; 程履帮
Original assignee: Datang Mobile Communications Equipment Co Ltd
Current assignee: China Academy of Telecommunications Technology CATT; Datang Mobile Communications Equipment Co Ltd
Priority date: 2008-03-28
Filing date: 2008-03-28
Publication date: 2009-09-30
Anticipated expiration: 2028-03-28
Also published as: CN101547018B

Abstract

The invention provides a method for realizing the filtering extraction of a multiaerial system, which comprises the following steps: interweaving data signals of a K-path antenna into an M phase in a time division multiplexing mode according to a ratio K of a processing clock rate in an FPGA to a clock rate after digital down-conversion processing; dividing a filter factor into the M phase according to an extraction multiple M of the system, and respectively filtering the M-phase data signals by utilizing the M-phase filter factor; and merging and outputting the data signals after M-phase filtering. The invention also provides a device for realizing the filtering extraction of the multiaerial system. The filtering extraction of the data signals in the multiaerial system can be realized by utilizing the method and the device; and meanwhile, the utilization ratio of multiplicative resources can be increased by combining the symmetrical characteristic of a filter in the filtering process.

Description

Method and device for realizing decimation filtering of multi-antenna system

Technical Field

The invention relates to the technical field of mobile communication, in particular to a method and a device for realizing decimation filtering of a multi-antenna system.

Background

In the existing mobile communication system, the conventional DDC (digital down conversion) processing method is to filter (convolve) the received data first, and then extract the filtered signal; but since the filtering is done before decimation, a lot of multiplication resources are occupied. For this purpose, the decimation filtering in the prior art uses polyphase processing, i.e. digital filters E_K(z) after decimator M, filtering is performed after the rate is reduced, thus effectively reducing the number of multiplications; the decimation process of the polyphase filter is shown as the following formula:

the specific development is illustrated as follows:

wherein the first row of the two-dimensional matrix is marked H₀(Z^M) The second line is marked as Z^-1H₁(Z^M) And so on, the last row is Z^-(M-1)H_M-1(Z^M)；

So H (Z) can be labeled as:

H(Z)＝H₀(Z^M)+Z^-1H₁(Z^M)+Z^-2H₂(Z^M)+......+Z^-(M-1)H_(M-1)(Z^M) (1-4)

the transfer function of the filter can be expressed as:

wherein,

that is to say that the first and second electrodes,

wherein h (z) represents the transfer function of the polyphase filter; n represents the length of the filter coefficients; i denotes an index of each phase filter coefficient; k represents the index of the multiphase, and the value is from 0 to M-1; m represents the number of phases which are divided together; h (n) represents the value of the nth filter coefficient; e_k(z^M) Is the transfer function of the subphase filter; the decimation structure of a specific polyphase filter is shown in fig. 1;

although the above-mentioned prior art proposes the structure and processing method of polyphase filtering decimation, generally, polyphase filtering processing is only performed on single-antenna data, and how to perform decimation filtering processing more reasonably on data of a multi-antenna system is not well implemented.

Disclosure of Invention

In view of this, the present invention provides a method and an apparatus for implementing decimation filtering in a multi-antenna system, which can implement decimation filtering on data in the multi-antenna system and reduce multiplication resources.

In order to solve the above problems, the technical scheme provided by the invention is as follows:

a method of implementing decimation filtering, comprising:

the data signals are input to different paths through control to complete extraction speed reduction processing;

respectively carrying out filtering processing on the data signals subjected to speed reduction on different paths;

and merging the filtered data signals on different paths into a path of data signal for output.

The process of extracting and reducing the speed by controlling the data signals to be input to different paths is concretely as follows:

the data signal is sequentially input from the mth path to the 1 st path, and only one of M consecutive data is input on each path and goes through M cycles.

An apparatus for performing decimation filtering, comprising: the device comprises a decimation processing unit, a filtering processing unit and a combination processing unit; wherein,

the extraction processing unit is used for: the data signals are input to different paths through control to complete extraction speed reduction processing;

the filtering processing unit is used for: respectively carrying out filtering processing on the data signals subjected to speed reduction on different paths;

the merging processing unit is used for: and merging the filtered data signals on different paths into a path of data signal for output.

A method of implementing decimation filtering in a multi-antenna system, comprising:

according to the ratio K of the processing clock rate in the FPGA to the clock rate after digital down-conversion processing, interleaving the data signals of the K paths of antennas into M phases in a time division multiplexing mode; the M is the extraction multiple of the system;

dividing the filter coefficient into M phases according to the decimation multiple M, and filtering the M-phase data signals by using the M-phase filter coefficient;

and combining and outputting the M-phase filtered data signals.

The interleaving of the data signal specifically includes:

caching data at the same position on each antenna in the K paths of antennas;

and merging and outputting the buffered data for subsequent filtering processing.

The filtering the M-phase data signals by using the M-phase filter coefficients specifically includes:

when the sub-phase filter coefficient has symmetry, the sub-phase filter coefficient with symmetry is directly used for filtering the sub-phase data signal;

when the sub-phase filter coefficients do not have symmetry, new sub-phase filter coefficients are generated by using the sub-phase filter coefficients without symmetry, new sub-phase data signals are generated by using the sub-phase data signals, and then the new sub-phase data signals are filtered by using the new sub-phase filter coefficients.

Wherein the generating of the new sub-phase filter coefficient and the generating of the new sub-phase data signal specifically include:

obtaining new sub-phase filter coefficients by respectively adding and subtracting data at the same positions of the sub-phase filter coefficients without symmetry;

new sub-phase data signals are obtained by adding and subtracting the odd-phase data and the even-phase data of each sub-phase data signal, respectively.

Wherein the performing filtering further comprises:

before filtering the data signal of a certain antenna in each sub-phase, caching the data signals of other antennas, and simultaneously filtering all the antennas in a time division multiplexing mode.

Wherein the performing filtering further comprises:

and processing and propagating each sub-phase data signal according to a preset direction, and completing a plurality of multiplication and addition operations at one sampling moment.

An apparatus for implementing decimation filtering in a multi-antenna system, comprising: the device comprises an interleaving unit, a filtering unit and an output unit; wherein,

the interleaving unit is used for: according to the ratio K of the processing clock rate in the FPGA to the clock rate after digital down-conversion processing, adopting a time division multiplexing mode to interweave data signals of K paths of antennas into M phases, wherein M is the extraction multiple of the system;

the filtering unit is used for: dividing the filter coefficient into M phases according to the decimation multiple M, and filtering the M-phase data signals processed by the interleaving unit by using the M-phase filter coefficient;

the output unit is used for: and merging and outputting the data signals after the filtering processing of the filtering unit.

Wherein the interleaving unit further comprises: a sending unit and a first cache unit; wherein,

the sending unit is used for: sending data at the same position on each antenna in the K paths of antennas to each first cache unit;

the first cache unit is configured to: and the buffer sending unit sends the data on each antenna, and respectively combines and outputs the data to the filtering unit.

Wherein the filtering unit further includes: the phase splitting unit, the judging unit and the sub-phase filtering unit; wherein,

the phase separation unit is used for: dividing the filter coefficient into M phases according to the decimation multiple M;

the judgment unit is used for: judging whether each sub-phase filter coefficient has symmetry or not, and sending the result to the sub-phase filter unit;

the sub-phase filtering unit is used for: receiving the judgment result of the judgment unit, and when the sub-phase filter coefficient has symmetry, directly using the symmetric sub-phase filter coefficient to filter the sub-phase data signal; and when the sub-phase filter coefficients do not have symmetry, generating new sub-phase filter coefficients by using the sub-phase filter coefficients without symmetry, simultaneously generating new sub-phase data signals by using each sub-phase data signal, and then filtering the new sub-phase data signals by using the new sub-phase filter coefficients.

Wherein the sub-phase filtering unit is further configured to: new sub-phase filter coefficients are obtained by adding and subtracting data at the same positions as the sub-phase filter coefficients each having no symmetry, respectively, and new sub-phase data signals are obtained by adding and subtracting odd-phase data and even-phase data of each sub-phase data signal, respectively.

Wherein the filtering unit further includes: and the second buffer is used for buffering the data signals of other antennas before filtering by each sub-phase filtering unit.

Wherein the sub-phase filtering unit is further configured to: and processing and propagating each sub-phase data signal according to a preset direction, and completing a plurality of multiplication and addition operations at one sampling moment.

It can be seen that, by adopting the method and the device of the invention, the data signals of the multi-antenna system are interleaved into a plurality of phase data signals, the filter coefficients are divided into a plurality of corresponding phase filter coefficients by utilizing the extraction multiple, and then the plurality of data are filtered by utilizing the plurality of phase filter coefficients in a time division multiplexing mode, so as to realize the filtering extraction of the data signals of the multi-antenna system; meanwhile, the utilization rate of multiplication resources is improved by combining the symmetry characteristic of the filter in the filtering process.

Drawings

FIG. 1 is a schematic diagram of a decimation structure of a prior art polyphase filter;

FIG. 2 is a schematic flow chart of the method of example 1 of the present invention;

FIG. 3 is a schematic block diagram of an apparatus according to embodiment 2 of the present invention;

FIG. 4 is a schematic diagram showing the internal structure of the apparatus according to example 2 of the present invention when the decimation factor is 3;

FIG. 5 is a schematic flow chart of the method of example 3 of the present invention;

FIG. 6 is a diagram illustrating the odd-order filter coefficients are divided into two phases in the method according to embodiment 3 of the present invention;

FIG. 7 is a schematic diagram of the two-phase filtering process when the filter coefficients are odd-order in the method according to embodiment 3 of the present invention;

FIG. 8 is a diagram illustrating the even-order filter coefficients are divided into two phases in the method according to embodiment 3 of the present invention;

FIG. 9 is a schematic diagram of the two-phase filtering process when the filter coefficients are of even order in the method according to embodiment 3 of the present invention;

FIG. 10 is a schematic view of a three-phase filtering process in the method of embodiment 3 of the present invention;

FIG. 11 is a schematic block diagram of an apparatus according to embodiment 4 of the present invention.

Detailed Description

The basic idea of the invention is to apply the polyphase filtering process to the multi-antenna system, so as to realize the filtering extraction of the data signal of the multi-antenna system; meanwhile, the utilization rate of multiplication resources is improved by combining the symmetry characteristic of the filter in the filtering process.

In order that those skilled in the art will better understand the present invention, the method of the present invention will be described in detail below with reference to the accompanying drawings and specific examples.

Embodiment 1 of the present invention provides a method for implementing decimation filtering, as shown in fig. 2, where the method includes:

step 201: the data signals are input to different paths through control to complete extraction speed reduction processing;

step 202: respectively carrying out filtering processing on the data signals subjected to speed reduction on different paths;

step 203: and merging the filtered data signals on different paths into a path of data signal for output.

Specifically, the extraction of the data signal and the reduction of the rate are accomplished by controlling successive data signal input samples to different ones of the M paths: wherein, the deceleration can also be understood as a delay of a period; since the extraction and the delay are related operations, the size of the extraction factor can be changed by adjusting different input paths, which means that only the input path needs to be changed for adjusting the extraction factor; for example: in the down-conversion processing scheme of M filtering paths, firstly, input data signals are sequentially input from the Mth path to the 1 st path, for each path, only one continuous input data is obtained for every M paths, and M clock cycles are experienced in the process, so that M times of extraction and M cycles of delay can be completed; then, carrying out filtering processing on the speed-reduced signals on the M paths; and finally, combining the data signals on the paths, namely combining the signals convolved (filtered) by the M paths into one path and sending out the path.

In addition, embodiment 2 of the present invention further provides an apparatus for implementing decimation filtering, as shown in fig. 3, the apparatus includes: a decimation processing unit 301, a filtering processing unit 302, and a combining processing unit 303; wherein,

the extraction processing unit 301 is used for completing extraction speed reduction processing by controlling data signals to be input to different paths; the filtering processing unit 302 is configured to perform filtering processing on the data signals after speed reduction on different paths respectively; the merging processing unit 303 is configured to merge the data signals filtered on different paths into one path of data signal and output the path of data signal;

the decimation processing unit 301 in the device of the present embodiment performs decimation and delay on the input signalDelayed processing, while in embodiments of the present invention it may be considered a commutating switch; since decimation and delay are related operations, the size of the decimation factor can be changed by adjusting the change-over switch (decimation processing unit), which means that only the change-over switch is needed to adjust the decimation factor; meanwhile, the number of the filter processing units 302 may be plural; illustrated in detail by way of example in FIG. 4, wherein f_sRepresenting the input signal rate, f_sThe output rate of the signal is represented by/3, the rate having been reduced to one third of the input signal rate: in the down-conversion processing scheme of 3 filtering processing units, the reversing switch inputs input data from the 3 rd path to the 1 st path in sequence, for each path, only one data signal is obtained from every 3 continuous input data signals, and 3 clock cycles are passed in the period, so that 3-time extraction and 3-cycle delay can be completed.

Embodiment 3 of the present invention further provides a method for implementing decimation filtering in a multi-antenna system, as shown in fig. 5, where the method includes:

step 501: according to the ratio K of the processing clock rate in an FPGA (field programmable gate array) to the clock rate after DDC (digital down conversion) processing, adopting a TDM (time division multiplexing) mode to interweave the data signals of K paths of antennas into M phases; the M is the extraction multiple of the system;

the multiplexing method adopted in the embodiment of the invention is related to the processing clock rate in the FPGA and the rate after DDC processing, and the internal clock processing rate of the FPGA is usually greater than the rate of DDC processing, namely:

K = \frac{f_{clk}}{f_{ddc}}, K > 1;

therefore, the filtering and extracting function can be completed on the data of the multiple antennas in a TDM mode for the extracting and filtering processing of the multiple antenna system, so that the multiple antennas can share multiplication resourcesThe addition resource and the delayer effectively save the system resource. For example, if the clock rate after DDC processing is 30.72MHz and the processing clock rate inside the FPGA is 122.88MHz, the processing of K being 122.88/30.72 being 4 antennas can be completed; if the decimation multiple M of the system is 2, interleaving the data signals of 4 antennas into 2 phases for subsequent filtering, which is specifically illustrated as follows:

assuming that the input data rate of 4 antennas is 61.44MHz and the decimation multiple of the system is 2, dividing the data signals of the 4 antennas into 2 phases; firstly, sending data of 4 antennas to a multi-phase buffer, sending the first data of a first antenna to the first position in the buffer 1, sending the first data of a 2 nd antenna to the 2 nd position in the buffer 1, and so on until the first data of the 4 th antenna is sent to the 4 th position in the buffer 1; simultaneously sending the 2 nd data of the 2 nd antenna to the first position in the buffer 2, sending the 2 nd data of the 2 nd antenna to the 2 nd position in the buffer 2, and so on until the 2 nd data of the 4 th antenna is sent to the 4 th position in the buffer 2; thus, the interleaving is completed, and although the rate of sending the signals to the buffer by each antenna is 30.72MHz, the rate of outputting the signals by each buffer is the rate after 4 antennas are interleaved, that is, 122.88 MHz.

Step 502: dividing the filter coefficient into M phases according to the decimation multiple M, and filtering the M-phase data signals by using the M-phase filter coefficient;

in the embodiment of the present invention, each sub-phase filtering may adopt a filtering method in the prior art, and is not described again; however, the embodiment of the present invention provides another idea, that is, the symmetry of the sub-phase filter coefficient is considered during the filtering process:

if the sub-phase filter coefficients have symmetry, directly using the sub-phase filter coefficients having symmetry; for example, for the odd-order filter coefficients, if the odd-order filter coefficients are divided into two phases, each phase of filter coefficients presents symmetry, and in the filtering process, data to be filtered are added firstly and then multiplied by the filter coefficients, so that a multiplier used in the filtering process can save half, and multiplication resources of a system are saved;

if the sub-phase filter coefficients do not have symmetry, the sub-phase filter coefficients without symmetry are combined two by two, namely: if the mth phase does not have symmetry, the M-M phase filter coefficients do not have symmetry, the mth phase filter coefficients and the M-M phase filter coefficients can be combined, and the combination rule is that data at the same positions of the mth phase filter coefficients and the M-M phase filter coefficients are firstly added and subtracted to obtain new filter coefficients; and simultaneously adding and subtracting the input data of the odd term and the even term to obtain new input data.

In addition, the embodiment of the invention also provides that some buffer functions are added in the filtering process of each phase to buffer signals of other antennas so as to achieve the effect of multi-phase filtering on the filtering of a plurality of antennas; for example: in the embodiment step 501, for the processing of 4 antennas, 3 buffer areas are added before each filtering to buffer the data of other 3 antennas, and at this time, the filtering processing of multiple antennas is completed in a time-sharing manner in a TDM manner;

meanwhile, the embodiment of the invention also provides that a pulse structure is adopted to finish convolution operation in the filtering process of each phase, namely, data are transmitted and processed in the left-to-right direction, a plurality of multiplications and a plurality of additions are finished in one beat, and one data is output at the same time; for example, a systolic FIR filter: the ripple FIR filter structure is the optimal structure in the parallel filter structure, that is, the input data is fed into the data register, the later sampling data in the register corresponding to each FPGA processing clock is output to the multiplier to be multiplied by the corresponding coefficient, the filter coefficients are arranged from left to right, the first coefficient is at the leftmost side, the last coefficient is at the rightmost side, and the product results of the signal data and the filter coefficients are added together by the adder chain to form the filtering result at the sampling moment.

The following takes two-phase filtering as an example to introduce the efficient processing principle and method of odd-order filter coefficients and even-order filter coefficients in two phases respectively:

first, the mathematical expression of the double decimation filter coefficient is as follows:

where H (z) denotes the transfer function of the polyphase filter; n denotes the length of the filter coefficient; i denotes the index of the filter coefficient for each phase; k denotes the index of the polyphase; e_k(z²) The transfer function of the k-th phase filtering is shown;

(1) if for h (z) is an odd order filter, then either of the two-phase filter coefficients (first and second phases) is a symmetric filter coefficient, as shown in fig. 6 as h (0), h (1.. both are filter coefficients; therefore, the data signals of the multiple antennas can be directly filtered by using the symmetry:

the first corresponding filter coefficient starts from phase 0, isolates one filter coefficient to extract one until the last filter coefficient is extracted:

A＝H₀(z²)＝h(0)，h(2)，..h(n)，...h(2)，h(0) (2-4)

the second corresponding filter coefficient starts from phase 1, isolates one filter coefficient to extract one, and till the last filter coefficient is extracted:

B＝H₁(z²)＝h(1)，h(3)，..h(n-1)，h(n-1)...h(3)，h(1) (2-5)

after each phase is multiplied by its corresponding data, the multiplied data at that same time is then superimposed to complete the filtering of the time-of-day signal.

Because the coefficient is an odd number, the number of the filter coefficients after being divided into two phases is not equal, and the First phase needs to have one more coefficient than the second phase, the sub-phase filter of the second phase needs to delay one clock cycle through a register before entering a First Input First Output (FIFO) so as to achieve the function of synchronously processing and filtering the coefficients of the two-phase filter; for example, the filter coefficients corresponding to 4 antenna data in a certain time slot are shown in the following table, wherein the filter coefficients of 12 orders out of 13 orders are symmetric:

as can be seen from the above table, due to the symmetry of the coefficients of the polyphase filter, the data of the same antenna are multiplied by the coefficients of the filter after being added, so that the operation amount of multiplication is reduced; and since the second phase delay is 4 clock cycles (since there are 4 antennas, it is necessary to delay 4 clock cycles), the signals can be output in the correct order, as shown in fig. 7.

(2) If it is an even order filter for h (z), then neither phase (first phase or second phase) of the two-phase filter coefficients is a symmetric filter coefficient, as shown in fig. 8; wherein,

H₀(z²)＝h(0)，h(2)，..h(n)，...h(3)，h(1) (2-6)

H₁(z²)＝h(1)，h(3)，..h(n)，...h(2)，h(0) (2-7)

because the filter coefficients are even orders, the lengths of the two-phase filter coefficients are equal, and data at the same positions of the first-phase filter coefficient and the second-phase filter coefficient are firstly added and subtracted to obtain new filter coefficients A (Z) and B (Z); the data input at the same time, the odd term data and the even term data are added and subtracted to obtain new input data IX0(Z), IX1(Z), and then the filtering extraction process is performed, as shown in fig. 9: in particular, the method comprises the following steps of,

after the even order splits into two phases, each phase of the filter coefficients has no symmetry, but the coefficients at the same location of the two-phase filters have symmetry if superimposed:

A(z)＝[H₀(z²)+H₁(z²)]/2＝h(0)+h(1)，h(2)+h(3)，…，2h(n)，…，h(3)+h(2)，h(1)+h(0) (2-8)

adding the first phase filter coefficient and the second phase filter coefficient, and performing the correction on the two corresponding filter coefficients to achieve the aim that the filter coefficients show symmetry, wherein A (z) is generated as the corrected first phase filter coefficient; however, in this case, the first-phase filter coefficient is multiplied by the input first-phase data, i.e., A (Z) X₀(z) the multiplication of the second phase filter coefficients with the first phase data is not needed for the filtering process, and another symmetric filter coefficients need to be generated as follows:

B(z)＝[H₀(z²)-H₁(z²)]/2＝h(0)-h(1)，h(2)-h(3)，…，0，…，h(3)-h(2)，h(1)-h(0) (2-9)

subtracting the first phase filter coefficient from the second phase filter coefficient, and performing the correction on the two corresponding filter coefficients to achieve the purpose that the filter coefficients present symmetry, wherein the generated B (z) is used as the corrected second phase filter coefficient, and the symmetry of the B (z) is characterized by opposite signs;

the two-phase filter coefficients are symmetrical at the moment; theoretically, in the decimation filtering process, the first phase data needs to be convolved with the filter coefficient of the first phase, the second phase data needs to be convolved with the filter coefficient of the second phase, and therefore, the two-phase input data also needs to be additionally processed (namely, because the filter coefficient is modified, the input data needs to be correspondingly modified), and the two-phase input data IX is regenerated₀(z) and IX₁(z): wherein,

dividing the data into two phases, firstly superposing the data of the first phase and the data of the second phase, and inputting the superposed data as the corrected data of the first phase to a first-phase filter coefficient;

IX₀(z)＝X₀(z²)+X₁(z²) (2-10)

dividing the data into two phases, firstly subtracting the data of the first phase from the data of the second phase, and inputting the data of the second phase into a second phase filter coefficient as modified second phase data;

IX₁(z)＝X₀(z²)-X₁(z²) (2-11)

the regenerated filter coefficients are then convolved with the regenerated input data to complete the filter decimation process:

it should be noted that, in the embodiment of the present invention, only two-phase processing is taken as an example, but not limited thereto; the extraction of more complex multiples can also be obtained in two ways, for example: when the three times of extraction are performed, one phase of the filter coefficients is necessarily symmetrical, the other two phases are not symmetrical, and the two phases of the filter coefficients without symmetry can be symmetrical by a processing method of dividing the filter coefficients with even orders into two phases, so that the three-phase filter coefficients are symmetrical, and the specific processing is shown in fig. 10 and is not repeated.

Step 503: and combining and outputting the M-phase filtered data signals.

After each phase of filtering processing is finished, data output by each phase of filtering processing are superposed to obtain a final filtering result signal, and the final filtering result signal is represented by the following formula:

odd-order filter coefficients:

Y(z)＝X₀(z²)H₀(z²)+X₁(z²)H₁(z²) (2-14)

even-order filter coefficients:

= X_{0} (z^{2}) H_{0} (z^{2}) + X_{1} (z^{2}) H_{1} (z^{2})

it will be understood by those skilled in the art that all or part of the steps in the method for implementing the above embodiments may be implemented by hardware associated with program instructions, and the program is stored in a specific storage medium.

It can be seen that the method of the present invention realizes the filtering extraction of the data signals of the multi-antenna system; meanwhile, the utilization rate of multiplication resources is improved by combining the symmetry characteristic of the filter in the filtering process.

Based on the above idea, embodiment 4 of the present invention further provides an apparatus for implementing decimation filtering in a multi-antenna system, as shown in fig. 11, including: an interleaving unit 1101, a filtering unit 1102, and an output unit 1103; wherein,

the interleaving unit 1101 is configured to: according to the ratio K of the processing clock rate in the FPGA to the clock rate after digital down-conversion processing, adopting a time division multiplexing mode to interweave data signals of K paths of antennas into M phases, wherein M is the extraction multiple of the system;

the filtering unit 1102 is configured to: dividing the filter coefficient into M phases according to the decimation multiple M, and filtering the M-phase data signals processed by the interleaving unit 1101 by using the M-phase filter coefficient;

the output unit is used for: and combining and outputting the data signals filtered by the filtering unit 1102.

the sending unit is used for: sending data at the same position on each antenna in the K paths of antennas to each first cache unit; the first cache unit is configured to: and the buffer sending unit sends the data on each antenna, and respectively combines and outputs the data to the filtering unit.

In addition, the filtering unit further includes: the phase splitting unit, the judging unit and the sub-phase filtering unit; wherein the phase separation unit is used for: dividing the filter coefficient into M phases according to the decimation multiple M; the judgment unit is used for: judging whether each sub-phase filter coefficient has symmetry or not, and sending the result to the sub-phase filter unit; the sub-phase filtering unit is used for: receiving the judgment result of the judgment unit, and when the sub-phase filter coefficient has symmetry, directly using the symmetric sub-phase filter coefficient to filter the sub-phase data signal; and when the sub-phase filter coefficients do not have symmetry, generating new sub-phase filter coefficients by using the sub-phase filter coefficients without symmetry, simultaneously generating new sub-phase data signals by using each sub-phase data signal, and then filtering the new sub-phase data signals by using the new sub-phase filter coefficients.

Wherein the sub-phase filtering unit may be further configured to: new sub-phase filter coefficients are obtained by adding and subtracting data at the same positions as the sub-phase filter coefficients each having no symmetry, respectively, and new sub-phase data signals are obtained by adding and subtracting odd-phase data and even-phase data of each sub-phase data signal, respectively.

It should be noted that the filtering unit further includes: and the second buffer is used for buffering the data signals of other antennas before filtering by each sub-phase filtering unit.

Furthermore, the sub-phase filtering unit is further configured to: and processing and propagating each sub-phase data signal according to a preset direction, and completing a plurality of multiplication and addition operations at one sampling moment.

Meanwhile, it can be easily understood by those skilled in the art that the apparatus for implementing uplink scheduling information transmission in the above embodiments may be integrated or installed on a terminal currently and generally adopted, and such integration or installation shall be included in the protection scope of the present invention, and will not be described herein again.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. A method of performing decimation filtering, comprising:

2. The method of claim 1, wherein the performing the decimation speed reduction by controlling the data signal input to the different paths comprises:

3. An apparatus for performing decimation filtering, comprising: the device comprises a decimation processing unit, a filtering processing unit and a combination processing unit; wherein,

4. A method for implementing decimation filtering in a multi-antenna system, comprising:

and combining and outputting the M-phase filtered data signals.

5. The method according to claim 4, characterized in that the interleaving of the data signal comprises in particular:

caching data at the same position on each antenna in the K paths of antennas;

6. The method according to claim 4, wherein the filtering the M-phase data signals respectively by using the M-phase filter coefficients specifically comprises:

7. The method of claim 6, wherein the generating new sub-phase filter coefficients and generating new sub-phase data signals specifically comprise:

8. The method of any one of claims 6 or 7, wherein the performing a filtering process further comprises:

9. The method of any one of claims 6 or 7, wherein the performing a filtering process further comprises:

10. An apparatus for implementing decimation filtering in a multi-antenna system, comprising: the device comprises an interleaving unit, a filtering unit and an output unit; wherein,

11. The apparatus of claim 10, wherein the interleaving unit further comprises: a sending unit and a first cache unit; wherein,

12. The apparatus of claim 10, wherein the filtering unit further comprises: the phase splitting unit, the judging unit and the sub-phase filtering unit; wherein,

13. The apparatus of claim 12, wherein:

the sub-phase filtering unit is further configured to: new sub-phase filter coefficients are obtained by adding and subtracting data at the same positions as the sub-phase filter coefficients each having no symmetry, respectively, and new sub-phase data signals are obtained by adding and subtracting odd-phase data and even-phase data of each sub-phase data signal, respectively.

14. The apparatus of claim 12 or 13, wherein the filtering unit further comprises: and the second buffer is used for buffering the data signals of other antennas before filtering by each sub-phase filtering unit.

15. The apparatus according to claim 12 or 13, wherein:

the sub-phase filtering unit is further configured to: and processing and propagating each sub-phase data signal according to a preset direction, and completing a plurality of multiplication and addition operations at one sampling moment.