CN101527547B - Method and related device for controlling power output stage of power amplifier - Google Patents

Abstract

A control circuit for a power amplifier, comprising: an over-sampling unit for over-sampling a digital input signal to generate an over-sampled signal; a control module for generating a first control signal and a second control signal according to the over-sampling signal; a pulse width modulation circuit for generating a first pulse width modulation signal according to the first control signal; and a pulse width adjusting unit for adjusting the pulse width of the first pulse width modulation signal according to the second control signal to generate a second pulse width modulation signal to control a power output stage of the power amplifier.

Description

Method and related device for controlling power output stage of power amplifier

technical field

The present invention relates to the technology of audio processing, especially the method and related device for controlling the power output stage of the power amplifier.

Background technique

Digital power amplifiers, or class-D power amplifiers, are widely used in many audio processing devices due to their high efficiency. The digital audio power amplifier uses a pulse width modulation circuit (PWM circuit) to generate a pulse width modulation signal according to the digital input signal to control the operation of the power output stage (power stage).

The performance of a digital audio power amplifier is related to the resolution (that is, the number of bits) of the pulse width modulation circuit (PWM circuit). Generally speaking, the higher the resolution of the PWM circuit, the better the performance of the digital audio power amplifier. However, the known PWM circuit must operate at a higher frequency to achieve the purpose of improving the resolution. From a process point of view, increasing the operating frequency of components will increase the difficulty and cost of manufacturing. Considering the cost, the efficiency of the digital audio power amplifier will be limited by the process and it is difficult to effectively improve it.

Contents of the invention

In view of this, one of the objectives of the present invention is to provide a method for controlling a power output stage of an audio power amplifier and a related device, so as to solve the above-mentioned problems.

This specification provides an embodiment of a control circuit of a power amplifier, which includes: an oversampling unit, used to oversample a digital input signal to generate an oversampled signal; a control module, used to The oversampling signal generates a first control signal and a second control signal; a pulse width modulation circuit is used to generate a first pulse width modulation signal according to the first control signal; and a pulse width adjustment unit is used for The pulse width of the first PWM signal is adjusted according to the second control signal to generate a second PWM signal to control a power output stage of the power amplifier.

This specification provides a method for controlling the power output stage of a power amplifier, which includes: oversampling a digital input signal to generate an oversampling signal; generating a first control signal and a second control signal according to the oversampling signal control signal; generate a first pulse width modulation signal according to the first control signal; and adjust the pulse width of the first pulse width modulation signal according to the second control signal to generate a second pulse width modulation signal controls the power output stage.

Description of drawings

FIG. 1 is a simplified block diagram of a preferred embodiment of the audio power amplifier of the present invention.

FIG. 2 is a flowchart of an embodiment of the method for controlling the power output stage shown in FIG. 1 according to the present invention.

FIG. 3 is a simplified block diagram of a first embodiment of the control module in FIG. 1 .

FIG. 4 is a simplified block diagram of the first embodiment of the pulse width adjustment unit in FIG. 1 .

FIG. 5 is a simplified block diagram of a second embodiment of the control module in FIG. 1 .

FIG. 6 is a simplified block diagram of a second embodiment of the pulse width adjustment unit in FIG. 1 .

FIG. 7 is a simplified block diagram of a third embodiment of the pulse width adjustment unit in FIG. 1 .

FIG. 8 is a simplified block diagram of a third embodiment of the control module in FIG. 1 .

[Description of main component symbols]

100 audio power amplifier

102 control circuit

110 oversampling units

120 control module

130 pulse width modulation circuit

140 pulse width adjustment unit

150 clock generation modules

160 power output stage

200 flow chart

210, 220, 230, 240, 250 steps

310, 510, 520, 810, 820 delta-sigma modulator

320, 830 decision units

410, 610, 710 phase shifter

420, 620, 720, 736 multiplexers

430, 732 or gate

630, 734 AND gates

730 combinatorial logic

Detailed ways

Please refer to FIG. 1 , which is a block diagram of an audio power amplifier 100 according to an embodiment of the present invention. As shown in the figure, the audio power amplifier 100 includes a control circuit (controller) 102 and a power output stage (power stage) 160, wherein the power output stage 160 is usually a switch mode power output stage. In this embodiment, the control circuit 102 includes an oversampling unit (oversampler) 110, a control module 120, a pulse width modulation circuit (PWM circuit) 130, a pulse width adjustment unit (pulse width adjuster) 140 and a clock A module 150 is generated. The clock generation module 150 is used to generate a first working clock CLK_1 required by the oversampling unit 110 and the control module 120, and a second working clock CLK_2 required by the pulse width modulation circuit 130, wherein the first working clock CLK_1 The frequency is F1, and the frequency of the second working clock CLK_2 is F2, and F2 is greater than F1. In practice, the clock generation module 150 can use a phase-locked loop to generate the second working clock CLK_2, and use a frequency dividing device to divide the second working clock CLK_2 to generate the first working clock with a lower frequency. Clock CLK_1. In the following, the operation and implementation of the control circuit 102 will be further described with reference to FIG. 2 .

FIG. 2 is a flow chart 200 of an embodiment of the method for controlling the power output stage 160 of the present invention, and the steps included in it are described as follows:

In step 210, the oversampling unit 110 receives an N1-bit digital audio signal Di with a frequency of F0, and performs oversampling on the digital audio signal Di according to the first working clock CLK_1 to generate a frequency of An N1-bit oversampled signal Ds of F1, wherein F1 is greater than F0.

In step 220, the control module 120 generates an N2-bit first control signal Ctl_1 with a frequency of F1 and an N3-bit second control signal Ctl_2 with a frequency of F1 according to the oversampled signal Ds, wherein N1> N2≥N3≥1.

Please refer to FIG. 3 , which is a simplified block diagram of the first embodiment of the control module 120 of the present invention. As shown in FIG. 3 , the control module 120 of this embodiment includes an N4-bit sigma delta modulator (sigma delta modulator) 310 and a decision unit 320 , where N4=N2+N3 and N4<N1. The delta-sigma modulator 310 is used for performing a delta-sigma modulation on the oversampled signal Ds to generate an N4-bit modulation signal M0. In operation, the delta-sigma modulator 310 not only reduces the number of bits of the digital audio signal, but also has the function of noise shaping.

Next, the decision unit 320 generates the first control signal Ctl_1 and the second control signal Ctl_2 according to the modulation signal M0 output by the delta-sigma modulator 310 . In practice, the decision unit 320 can generate the first control signal Ctl_1 according to a plurality of most significant bits of the modulation signal M0, and generate the first control signal Ctl_1 according to at least one low bit (least significant bit) of the modulation signal M0 to generate the second control signal Ctl_2. For example, in one embodiment, the decision unit 320 outputs the N2 high bits of the modulation signal M0 as the first control signal Ctl_1, and outputs the N3 low bits of the modulation signal M0 as the second control Signal Ctl_2. In this example, the decision unit 320 can be realized by a demultiplexer.

Next, in step 230, the pulse width modulation circuit 130 generates a 1-bit first pulse width modulation signal PWM1 with a frequency of F2 according to the first control signal Ctl_1, wherein F2=2 ^N2 ×F1.

In step 240, the pulse width adjustment unit 140 adjusts the pulse width of the first pulse width modulation signal PWM1 according to the instruction of the second control signal Ctl_2 generated by the control module 120 to generate a second pulse width modulation. Signal PWM2. Hereinafter, the implementation and operation of the pulse width adjustment unit 140 will be further described with reference to FIG. 4 .

FIG. 4 is a simplified block diagram of the first embodiment of the pulse width adjustment unit 140 of the present invention. The pulse width adjusting unit 140 of this embodiment includes a phase shifter (phase shifter) 410 , a multiplexer 420 and an OR gate (OR gate) 430 . The phase shifter 410 is used to generate a plurality of delay signals according to the first pulse width modulation signal PWM1. In this example, the phase shifter 410 uses a delay chain composed of n delay stages to delay the first PWM signal PWM1 to generate n delayed signals P1˜Pn, where n= ^2N3-1 . In one embodiment, the delay amount of each delay stage of the phase shifter 410 is 1/(F2×2 ^N3 ), so the phase difference between two adjacent delayed signals among the plurality of delayed signals P1˜Pn is 1 /(F2× ^2N3 ). Please note that this is only an embodiment, and does not limit the actual setting method of the delay amount of each delay stage in the phase shifter 410 .

The multiplexer 420 selects one of the plurality of delayed signals P1-Pn as an output according to the value of the second control signal Ctl_2. For example, in one embodiment, when the value of the second control signal Ctl_2 is 0, the multiplexer 420 will output a logic "0"signal; when the value of the second control signal Ctl_2 is 1, the multiplexer 420 420 will select the delay signal P1 as output; when the value of the second control signal Ctl_2 is 2, the multiplexer 420 will select the delay signal P2 as output; and when the value of the second control signal Ctl_2 is 2 ^N3 -1 , the multiplexer 420 will select the delayed signal Pn as the output, and so on. Next, the OR gate 430 in the pulse width adjustment unit 140 performs a logical OR operation on the first pulse width modulation signal PWM1 and the output of the multiplexer 420 to generate the second pulse width modulation signal PWM2 .

It can be seen from the foregoing that when the value of the second control signal Ctl_2 is 0, the second pulse width modulation signal PWM2 output by the OR gate 430 is substantially the same as the first pulse width modulation signal PWM1. But when the value of the second control signal Ctl_2 is not 0, due to the high logic of the first pulse width modulation signal PWM1 and a delay signal Pi (i=1~n) selected by the multiplexer 420 The level periods do not completely overlap, so the pulse width of the second pulse width modulation signal PWM2 output by the OR gate 430 is greater than the pulse width of the first pulse width modulation signal PWM1. In other words, the pulse width adjustment unit 140 of this embodiment determines whether to increase the output pulse width of the pulse width modulation circuit 130 according to the second control signal Ctl_2 output by the control module 120 to form the second pulse width modulation signal. PWM2.

Next in step 250 , the audio power amplifier 100 uses the second pulse width modulation signal PWM2 generated by the control circuit 102 to drive the power output stage 160 . The operation of using a pulse width modulation signal to control a power output stage is a well-known technology, and no further description is given here.

In the control circuit 102 of the audio power amplifier 100, if the modulation signal M0 of N4 bits generated by the delta-sigma modulator 310 of the control module 120 is directly used as the input signal of the pulse width modulation circuit 130, the pulse width modulation The operating frequency of the inverter circuit 130 must be increased to 2 ^N4 ×F1. This will greatly increase the manufacturing difficulty and cost of the pulse width modulation circuit 130 . It can be seen that the control module 120 uses the decision unit 320 to decompose the modulation signal M0 output by the delta-sigma modulator 310 into the first control signal Ctl_1 and the second control signal Ctl_2 with relatively low bit numbers, which can effectively reduce the pulse width. The operating frequency of the circuit 130 is modulated, thereby reducing manufacturing difficulty and cost. On the other hand, since the pulse width adjustment unit 140 of the control circuit 102 will fine-tune the output pulse width of the pulse width modulation circuit 130 according to the second control signal Ctl_2, the resolution of the output second pulse width modulation signal PWM2 , will be very close to the resolution of a PWM signal generated by the PWM circuit 130 according to the N4-bit modulation signal M0 at an operating frequency of ^2N4 ×F1. In other words, the structure of the aforementioned control circuit 102 can greatly reduce the operating frequency of the PWM circuit 130 without affecting the overall performance of the audio power amplifier 100 . From another point of view, compared with the conventional control circuit that also uses the pulse width modulation circuit 130, the aforementioned control circuit 102 has better output pulse width resolution, so it can effectively improve the performance of the audio power amplifier.

Please refer to FIG. 5 , which is a simplified block diagram of the second embodiment of the control module 120 of the present invention. In this embodiment, the control module 120 includes an N2-bit first delta-sigma modulator 510 and a N4-bit second delta-sigma modulator 520 , where N4=N2+N3. The first delta-sigma modulator 510 is used for performing a first delta-sigma modulation on the oversampled signal Ds to generate an N2-bit first control signal Ctl_1. The second delta-sigma modulator 520 is used to perform a second delta-sigma modulation on the oversampled signal Ds to generate a modulated signal of N4 bits, and use the N3 lower bits of the modulated signal as the first Two control signals Ctl_2. Since the N2-bit first control signal Ctl_1 generated by the first delta-sigma modulator 510 is substantially the same as the N2 high-order bits of the modulation signal generated by the second delta-sigma modulator 520, as shown in FIG. 5 The control module 120 is substantially equivalent to the aforementioned embodiment of FIG. 3 . In this case, the pulse width adjustment unit 140 can also be implemented by the embodiment of FIG. 4 .

In the foregoing embodiments, the pulse width adjustment unit 140 determines whether to increase the output pulse width of the pulse width modulation circuit 130 according to the second control signal Ctl_2 output by the control module 120 to generate the second pulse width modulation. Signal PWM2. However, this is only an example, rather than limiting the actual implementation of the present invention. Taking the control module 120 shown in FIG. 3 as an example, when the decision unit 320 receives the modulation signal M0 of N4 (=N2+N3) bits output by the delta-sigma modulator 310, the decision unit 320 can modulate the Adding 1 to the value represented by the N2 high-order bits in the signal M0 as the value of the first control signal Ctl_1, and subtracting 2 ^N3 from the value represented by the N3 low-order bits to obtain the second control signal The value of Ctl_2. Compared with the previous embodiments, the value of the first control signal Ctl_1 in this embodiment is larger, so the pulse width modulation circuit 130 will output a first pulse width modulation signal PWM1 ′ with a wider pulse width. In this case, the pulse width adjustment unit 140 can be realized by the embodiment shown in FIG. 6 .

As shown in FIG. 6 , the pulse width adjustment unit 140 of this embodiment includes a phase shifter 610 , a multiplexer 620 and an AND gate (AND gate) 630 . The operation of the phase shifter 610 is substantially the same as that of the phase shifter 410 in FIG. 4 , and for the sake of brevity, the description will not be repeated here. In this embodiment, when the value of the second control signal Ctl_2 is 0, the multiplexer 620 will output a logic "1"signal; when the value of the second control signal Ctl_2 is 1, the multiplexer 620 will output Select the delayed signal P1 as the output; when the value of the second control signal Ctl_2 is 2, the multiplexer 620 will select the delayed signal P2 as the output; and when the value of the second control signal Ctl_2 is 2 ^N3 -1, the multiplexer 620 The processor 620 will select the delayed signal Pn as the output, and so on.

The AND gate 630 is used to perform a logical AND operation on the first PWM signal PWM1' and the output of the multiplexer 620 to generate the second PWM signal PWM2. Specifically, when the value of the second control signal Ctl_2 is 0, the second pulse width modulation signal PWM2 output by the AND gate 630 is substantially the same as the first pulse width modulation signal PWM1'. But when the value of the second control signal Ctl_2 is not 0, the pulse width of the second pulse width modulation signal PWM2 output by the AND gate 630 will be smaller than the pulse width of the first pulse width modulation signal PWM1'. In other words, the pulse width adjustment unit 140 of this embodiment determines whether to reduce the output pulse width of the pulse width modulation circuit 130 according to the second control signal Ctl_2 output by the control module 120 to form the second pulse width modulation signal. PWM2.

Please refer to FIG. 3 again. In another embodiment, when the decision unit 320 of the control module 120 receives the modulation signal M0 of N4 (=N2+N3) bits output by the delta-sigma modulator 310, the decision unit 320 An N2+1-bit first control signal Ctl_1 is generated according to the N2 high-order bits of the modulation signal M0, wherein the N2 high-order bits of the first control signal Ctl_1 are the N2 high-order bits of the modulation signal M0 , and the least significant bit (LSB) of the first control signal Ctl_1 is fixed at 1. In this example, the decision unit 320 will subtract 2 ^N3-1 from the value represented by the N3 lower bits of the modulation signal M0 to generate an N3-bit second control signal Ctl_2, wherein the second control signal The most significant bit (MSB) of Ctl_2 is a sign bit. For example, assuming that N3 is equal to 3, if the value represented by the N3 lower bits of the modulation signal M0 is 7, the value of the second control signal Ctl_2 output by the determining unit 320 is 3, which means the bit sequence is "011"; if the value represented by the N3 low bits of the modulation signal M0 is 4, the bit sequence of the second control signal Ctl_2 is "000"; if the N3 low bits of the modulation signal M0 represent If the representative value is 1, the bit sequence of the second control signal Ctl_2 output by the determination unit 320 is “101”; and if the value represented by the N3 lower bits of the modulation signal M0 is 0, the determination unit The bit sequence of the second control signal Ctl_2 output by 320 is "100".

In this embodiment, the pulse width modulation circuit 130 outputs a first pulse width modulation signal PWM1 ″ whose pulse width is between the aforementioned pulse width modulation signals PWM1 and PWM1 ′. In this case, the pulse The width adjustment unit 140 can be realized by the embodiment shown in FIG. 7 .

As shown in FIG. 7 , the pulse width adjustment unit 140 of this embodiment includes a phase shifter 710 , a multiplexer 720 and a combinational logic 730 . The phase shifter 710 is composed of m delay stages, and is used to delay the first pulse width modulation signal PWM1 ″ to generate m delayed signals P1˜Pm, where m=2 ^N3-1 . The multiplexer 720 will be based on The value of the second control signal Ctl_2 selects one of the plurality of delay signals P1～Pm as an output. For convenience of description, the example that the aforementioned N3 equals 3 is used to illustrate below. In this embodiment, m equals 4 , when the bit sequence of the second control signal Ctl_2 is "000", the multiplexer 720 will output a logic "0"signal; when the bit sequence of the second control signal Ctl_2 is "001" or "101" , the multiplexer 720 will select the delayed signal P1 as the output; when the bit sequence of the second control signal Ctl_2 is "010" or "110", the multiplexer 720 will select the delayed signal P2 as the output; When the bit sequence of the second control signal Ctl_2 is “100”, the multiplexer 720 will select the delayed signal Pm as the output, and so on. Next, the combinational logic 730 performs a logical AND operation or a logical OR operation on the first pulse width modulation signal PWM1 ″ and the output of the multiplexer 720 according to the sign bit of the second control signal Ctl_2 to generate a The second pulse width modulation signal PWM2.

As shown in FIG. 7, the combinational logic 730 of this embodiment includes an OR gate 732, which is used to perform a logic OR (OR) operation on the first pulse width modulation signal PWM1 "and the output of the multiplexer 720 to generate A first signal S1; an AND gate 734, which is used to perform a logical AND (AND) operation on the first pulse width modulation signal PWM1" and the output of the multiplexer 720 to generate a second signal S2; and a The multiplexer 736 is used to select one of the first signal S1 and the second signal S2 as the second pulse width modulation signal PWM2 according to the sign bit in the second control signal Ctl_2. In this example, if the sign bit of the second control signal Ctl_2 is “0”, the multiplexer 736 will output the first signal S1 as the second pulse width modulation signal PWM2, and if the second control If the sign bit of the signal Ctl_2 is “1”, the multiplexer 736 will output the second signal S2 as the second pulse width modulation signal PWM2. As can be seen from the above, the pulse width adjustment unit 140 of this embodiment increases or decreases the output pulse width of the pulse width modulation circuit 130 according to the second control signal Ctl_2 output by the control module 120, so as to form the second pulse width modulation Change signal PWM2.

Please refer to FIG. 8 , which is a simplified block diagram of a third embodiment of the control module 120 of the present invention. In this embodiment, the control module 120 includes an N2-bit first delta-sigma modulator 810, an N4-bit second delta-sigma modulator 820, and a decision unit 830, wherein N4=N2+N3. The first delta-sigma modulator 810 is used for performing a first delta-sigma modulation on the oversampled signal Ds to generate a first modulated signal M1 of N2 bits. The second delta-sigma modulator 820 is used for performing a second delta-sigma modulation on the oversampled signal Ds to generate a second modulated signal M2 of N4 bits. Next, the decision unit 830 generates a first control signal Ctl_1 according to the first modulation signal M1, and generates a second control signal Ctl_2 according to at least one lower bit of the second modulation signal M2.

In one embodiment, the decision unit 830 generates an N2+1-bit first control signal Ctl_1 according to the first modulation signal M1, wherein the N2 high-order bits of the first control signal Ctl_1 are the first modulation N2 bits of the variable signal M1, and the least significant bit (LSB) of the first control signal Ctl_1 is fixed at 1. In addition, the decision unit 830 will also subtract 2 ^N3-1 from the value represented by the N3 lower bits of the second modulation signal M2 to generate an N3-bit second control signal Ctl_2, wherein the second control signal The most significant bit (MSB) of Ctl_2 is a sign bit. Since the manner in which the determining unit 830 generates the first control signal Ctl_1 and the second control signal Ctl_2 is substantially equivalent to the foregoing embodiment, the pulse width adjustment unit 140 that works in conjunction with the control module 120 in FIG. 8 can be used as shown in FIG. 7 to achieve.

In practice, a low-pass filter (such as a digital low-pass filter, not shown in the figure) can also be set between the super-sampling unit 110 and the control module 120 of the aforementioned control circuit 102, for the over-sampling unit 110 The output super-sampled signal Ds is subjected to a low-pass filtering operation to increase sampling points in the super-sampled signal Ds. For example, the low-pass filter can use interpolation to increase the number of sampling points in the super-sampled signal Ds. From one point of view, the operation of the low-pass filter can make the waveform of the over-sampled output signal smoother. In this way, the overall performance of the control circuit 102 can be further improved. Please note that the low-pass filter can actually be integrated into the same hardware unit as the above-mentioned super-sampling unit 110 or the control module 120 .

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (16)

1. A control circuit of a power amplifier, comprising: An oversampling unit is used for oversampling a digital input signal to generate an oversampling signal; a control module, used to generate a first control signal and a second control signal according to the oversampling signal; a pulse width modulation circuit, used to generate a first pulse width modulation signal according to the first control signal; and A pulse width adjustment unit is used for adjusting the pulse width of the first pulse width modulation signal according to the second control signal to generate a second pulse width modulation signal to control a power output stage of the power amplifier. 2. The control circuit as claimed in claim 1, wherein the control module comprises: a delta-sigma modulator for performing a delta-sigma modulation on the oversampled signal to generate a first modulated signal; and A decision unit is used for generating the first control signal and the second control signal according to the first modulation signal. 3. The control circuit according to claim 2, wherein the decision unit generates the first control signal according to a plurality of high bits of the first modulation signal, and generates the first control signal according to at least one low bit of the first modulation signal The second control signal is generated. 4. The control circuit as claimed in claim 1, wherein the control module comprises: a first delta-sigma modulator for performing a first delta-sigma modulation on the oversampled signal to generate the first control signal; and a second delta-sigma modulator for performing a second delta-sigma modulation on the oversampled signal to generate a second modulated signal, wherein the number of bits of the second modulated signal is higher than that of the first control signal, the second delta-sigma modulator uses at least one low bit of the second modulation signal as the second control signal. 5. The control circuit as claimed in claim 1, wherein the control module comprises: A first delta-sigma modulator, used to perform a first delta-sigma modulation on the oversampled signal to generate a third modulated signal; A second delta-sigma modulator, used to perform a second delta-sigma modulation on the oversampled signal to generate a fourth modulated signal with a bit number higher than that of the third modulated signal; and A decision unit is used for generating the first control signal according to the third modulation signal, and generating the second control signal according to at least one lower bit of the fourth modulation signal. 6. The control circuit as claimed in claim 1, wherein the pulse width adjustment unit comprises: a phase shifter, used to generate a plurality of delayed signals according to the first PWM signal; a multiplexer, coupled to the phase shifter, for selecting one of the plurality of delayed signals as an output according to the second control signal; and A logic circuit, coupled to the multiplexer, is used for performing a logic operation on the first PWM signal and the output of the multiplexer to generate the second PWM signal. 7. The control circuit as claimed in claim 1, wherein the number of bits of the first control signal is lower than the number of bits of the oversampled signal. 8. The control circuit as claimed in claim 1, further comprising a low-pass filter for increasing sampling points of the oversampled signal. 9. A method of controlling a power output stage of a power amplifier, comprising: oversampling a digital input signal to generate an oversampling signal; generating a first control signal and a second control signal according to the oversampled signal; generating a first PWM signal according to the first control signal; and The pulse width of the first PWM signal is adjusted according to the second control signal to generate a second PWM signal to control the power output stage. 10. The method as claimed in claim 9, wherein the step of generating the first control signal and the second control signal comprises: performing a delta-sigma modulation on the oversampled signal to generate a first modulated signal; and The first control signal and the second control signal are generated according to the first modulation signal. 11. The method as claimed in claim 10, wherein the step of generating the first control signal and the second control signal according to the first modulation signal comprises: generating the first control signal according to a plurality of high bits of the first modulation signal; and The second control signal is generated according to at least one lower bit of the first modulation signal. 12. The method as claimed in claim 9, wherein the step of generating the first control signal and the second control signal comprises: performing a first delta-sigma modulation on the oversampled signal to generate the first control signal; performing a second delta-sigma modulation on the oversampled signal to generate a second modulated signal with a bit number higher than that of the first control signal; and At least one low bit of the second modulation signal is used as the second control signal. 13. The method as claimed in claim 9, wherein the step of generating the first control signal and the second control signal comprises: performing a first delta-sigma modulation on the oversampled signal to generate a third modulated signal; performing a second delta-sigma modulation on the oversampled signal to generate a fourth modulation signal having a bit number higher than that of the third modulation signal; generating the first control signal according to the third modulation signal; and The second control signal is generated according to at least one lower bit of the fourth modulation signal. 14. The method as claimed in claim 9, wherein the step of generating the second PWM signal comprises: The first PWM signal is delayed to generate a plurality of delayed signals. 15. The method as claimed in claim 9, wherein the step of generating the second PWM signal comprises: delaying the first PWM signal to generate a plurality of delayed signals; selecting one of the plurality of delayed signals according to the second control signal; and Perform at least one logic operation on the first PWM signal and a selected delay signal according to the second control signal to generate the second PWM signal. 16. The method as claimed in claim 9, wherein the step of generating the first control signal and the second control signal according to the oversampled signal comprises: Before generating the first control signal and the second control signal according to the over-sampling signal, low-pass filtering is performed on the over-sampling signal.