CN101488462B - Modulated multi-die package construction and method thereof - Google Patents
Modulated multi-die package construction and method thereof Download PDFInfo
- Publication number
- CN101488462B CN101488462B CN2008100031714A CN200810003171A CN101488462B CN 101488462 B CN101488462 B CN 101488462B CN 2008100031714 A CN2008100031714 A CN 2008100031714A CN 200810003171 A CN200810003171 A CN 200810003171A CN 101488462 B CN101488462 B CN 101488462B
- Authority
- CN
- China
- Prior art keywords
- crystal grain
- those
- light
- metal wire
- wire sections
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 35
- 238000010276 construction Methods 0.000 title claims description 6
- 239000013078 crystal Substances 0.000 claims abstract description 156
- 239000002184 metal Substances 0.000 claims abstract description 93
- 229910052751 metal Inorganic materials 0.000 claims abstract description 93
- 239000011241 protective layer Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 54
- 238000000059 patterning Methods 0.000 claims description 50
- 238000004806 packaging method and process Methods 0.000 claims description 41
- 239000010410 layer Substances 0.000 claims description 38
- 239000002861 polymer material Substances 0.000 claims description 33
- 238000005520 cutting process Methods 0.000 claims description 23
- 238000012856 packing Methods 0.000 claims description 18
- 238000000576 coating method Methods 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 13
- 230000015654 memory Effects 0.000 claims description 13
- 230000006870 function Effects 0.000 claims description 8
- 235000012431 wafers Nutrition 0.000 description 35
- 238000005516 engineering process Methods 0.000 description 30
- 238000010586 diagram Methods 0.000 description 12
- 238000005538 encapsulation Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 239000010949 copper Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- NIXOWILDQLNWCW-UHFFFAOYSA-N 2-Propenoic acid Natural products OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229920000800 acrylic rubber Polymers 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920000058 polyacrylate Polymers 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229920002379 silicone rubber Polymers 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- -1 and simultaneously Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229920001688 coating polymer Polymers 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229920006336 epoxy molding compound Polymers 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Led Device Packages (AREA)
Abstract
The invention relates to a modularized multi-crystal grain encapsulating structure, comprising; a plurality of crystal grains, an encapsulated body, a plurality of patterned metal line sections, a patterned protective layer, a plurality of conductive components and a heat radiator, wherein, each of the crystal grains is provided with an active surface on which a plurality of weld pads are provided; the encapsulated body circles and covers five surfaces of each crystal grain and exposes the active surface and each weld pad of each crystal grain; two ends of part of the patterned metal line sections are electrically connected with a plurality of weld pads on the active surfaces of the crystal grains, while one end of part of the patterned metal line sections are electrically connected with a plurality of weld pads on the active surfaces of the crystal grains; the patterned protective layer covers a plurality of patterned metal line sections and exposes the other ends of part of the patterned metal line sections; the conductive components are electrically connected with the other end of each exposed patterned metal line section and the heat radiator is formed at the back of the encapsulated body.
Description
Technical field
The present invention relates to a kind of method for packaging semiconductor, particularly the encapsulation encapsulation method that the crystal grain of different size size and function is reconfigured.
Background technology
It is rapid that semi-conductive technology has developed quite, therefore microminiaturized semiconductor grain (Dice) must have the demand of diversified function, make semiconductor grain must in very little zone, dispose more I/o pad (I/O pads), thereby make the density of metal pin (pins) also improve apace.Therefore, early stage leaded package technology has been not suitable for the high-density metal pin; So develop the encapsulation technology that a kind of nodule number group (Ball Grid Array:BGA), the encapsulation of nodule number group is except having than the more highdensity advantage of leaded package, and its tin ball also relatively is not easy infringement and distortion.
Popular along with 3C Product, for example: mobile phone (Cell Phone), PDA(Personal Digital Assistant) or iPod etc., all the System on Chip/SoC of many complexity must be put into a very little space, therefore be this problem of solution, a kind of being called " wafer-level packaging (wafer levelpackage; WLP) " encapsulation technology develops out, and it can just encapsulate wafer earlier before cutting crystal wafer becomes many crystal grain.United States Patent (USP) announces the 5th, 323, and No. 051 patent has promptly disclosed this " wafer-level packaging " technology.Yet, this " wafer-level packaging " technology is along with the increase of the weld pad on the crystal grain active surface (pads) number, make between the weld pad (pads) apart from too small, except meeting causes the problem of signal coupling or signal interference, also can cause the problems such as reliability reduction of encapsulation because the weld pad spacing is too small.Therefore, after crystal grain further dwindles again, make aforesaid encapsulation technology all can't satisfy.
For solving this problem, United States Patent (USP) announces the 7th, 196, disclosed a kind of wafer that will finish semiconductor technology for No. 408, after test and cutting, with test result is that good crystal grain (gooddie) reapposes on another substrate, and then carry out packaging technology, so, make these intercrystallines that reapposed have distance between the broad, so (fan out) technology that stretches out is for example used in distribution that can the weld pad on the crystal grain is suitable, therefore can effectively solve because of spacing too small, the problem that causes signal coupling or signal to disturb except meeting.
Yet, for making semiconductor chip that less and thin encapsulating structure can be arranged, before carrying out the wafer cutting, can carry out thinning to wafer earlier and handle, for example grind (backside lapping) mode with wafer thinning to 2～20mil, and then cut into many crystal grain with the back of the body.This crystal grain through the thinning processing through reconfiguring on another substrate, forms a packaging body with injection molded with a plurality of crystal grain again; Because crystal grain is very thin, make that packaging body also is very thin, so after packaging body disengaging substrate, the stress of packaging body itself can make packaging body generation warpage increases follow-up difficulty of carrying out cutting technique.
In addition, after the wafer cutting, reconfigure when another substrate, be of a size of greatly because the size of new substrate is more original, therefore plant in the ball technology follow-up, can can't aim at, its encapsulating structure reliability reduces.For this reason, the invention provides a kind ofly before carrying out wafer cutting, it can solve effectively and can't aim at when planting ball and packaging body produces the problem of warpage to form registration mark (alignment mark) at wafer rear.
In addition, in the process of whole encapsulation, also can produce when planting ball, manufacturing equipment can produce local excessive pressure to crystal grain, and may damage the problem of crystal grain; Simultaneously, also may because the material of planting ball causes and crystal grain on weld pad between resistance value become big, and influence the problems such as performance of crystal grain.
Summary of the invention
Because plant that ball is aimed at and the problem of packaging body warpage described in the background of invention, the invention provides encapsulating structure and method thereof that a kind of crystal grain that utilizes the wafer alignment sign reconfigures, the method that a plurality of crystal grain are configured again and encapsulate.
So main purpose of the present invention provides a kind of preceding registration mark that forms earlier in the wafer cutting, carry out the method for packing that crystal grain reconfigures by registration mark then, make in planting the technology of ball, can aim at outside, packaging body itself can overcome stress and can make packaging body after breaking away from substrate, keep smooth, can effectively improve the yield and the reliability of manufacturing.
Another main purpose of the present invention provides a kind of method for packing that reconfigures at crystal grain, is that crystal grain with different size size and function reconfigures the method for packing on a substrate.
In addition, the present invention also has a main purpose to provide the method for packing that a kind of crystal grain reconfigures, it can be reconfigured in the crystal grain that wafer cut out on the substrate of 8 o'clock wafers at 12 o'clock, so can effectively use the sealed in unit that promptly has of 8 o'clock wafers, and need not to re-establish the sealed in unit of 12 o'clock wafers, can reduce the packaging cost of 12 o'clock wafers.
A main purpose more of the present invention makes that at the method for packing that provides a kind of crystal grain to reconfigure the chip that encapsulates all is " known is normally functioning chip " (Known good die), can save encapsulating material, so also can reduce the cost of technology.
According to the above, the invention provides a kind of modulated multi-die method for packing, comprising: a plurality of crystal grain are provided, and each crystal grain has and disposes a plurality of weld pads on an active surface and the active surface; Pick and place on a plurality of crystal grain to one substrates, each crystal grain is to cover crystal type the adhesion coating that active surface and is disposed on the substrate to be connected; Form a polymer material layer on a lower surface of substrate and part crystal grain; Break away from substrate, with active surface and each weld pad that exposes each crystal grain, to form a packaging body; Form the metal wire sections of a plurality of patternings, the two ends of the metal wire sections of a plurality of patternings of part electrically connect a plurality of weld pads on the active surface of a plurality of crystal grain, and an end of the metal wire sections of a plurality of patternings of part electrically connects a plurality of weld pads on the active surface of a plurality of crystal grain; Form patterned protective layer covering the metal wire sections of a plurality of patternings, and the other end of the metal wire sections of a plurality of patternings of expose portion; Form a plurality of conductive components, a plurality of conductive components are electrically connected on the other end of metal wire sections of each patterning that has exposed; And the cutting packaging body, to form a plurality of modulated multi-die package constructions.
The present invention discloses the method for packing that another kind of light-emitting diode reconfigures, and comprising: a plurality of light-emitting diodes are provided, and each light-emitting diode has and has a P electrode and a N electrode on an active surface and the active surface; Pick and place on a plurality of light-emitting diode to substrates, each light-emitting diode is to cover crystal type the adhesion coating that active surface and is disposed on the substrate to be connected; Form a polymer material layer on a lower surface of substrate and part light-emitting diode; The planarization polymer material layer makes polymer material layer riddle between a plurality of light-emitting diodes and coats a lower surface of each light-emitting diode; Break away from die device, with the active surface that exposes each light-emitting diode and each electrode to form a packaging body; Form the metal wire sections of a plurality of patternings, an end of the metal wire sections of a plurality of patternings electrically connects each P electrode and each the N electrode on the active surface of each light-emitting diode respectively, and the other end is connected to an outward extending metal wire sections respectively altogether; Form a patterned protective layer covering the metal wire sections of a plurality of patternings, and expose the part surface at outward extending two ends of the metal wire sections of a plurality of patternings; Form a plurality of conductive components, a plurality of conductive components are electrically connected on the surface of the outward extending metal wire sections that has exposed; And the cutting packaging body, to form a plurality of modular package structure for LED.
The present invention discloses the encapsulating structure that a kind of light-emitting diode reconfigures, and comprising: a plurality of light-emitting diodes, each light-emitting diode have and dispose a P electrode and a N electrode on an active surface and the active surface; One packaging body, ring are overlying on five faces of each light-emitting diode and expose active surface and each P electrode and each N electrode of each light-emitting diode; The metal wire sections of a plurality of patternings, one end electrically connect each P electrode and the N electrode on the active surface of each light-emitting diode respectively, and the other end then is connected to an outward extending metal wire sections respectively altogether; One patterned protective layer in order to covering the metal wire sections of a plurality of patternings, and exposes the part surface of outward extending metal wire sections; And a plurality of conductive components, be formed on the outward extending surface that has exposed, electrically connect to form.
The present invention discloses a kind of modulated multi-die package construction in addition, comprising: a plurality of crystal grain, each crystal grain have a plurality of weld pads of configuration body on an active surface and the active surface; One packaging body, ring are overlying on five faces of each crystal grain and expose active surface and each weld pad of each crystal grain; The metal wire sections of a plurality of patternings, the two ends of partially patterned metal wire sections electrically connect a plurality of weld pads on the active surface of a plurality of crystal grain, and an end of partially patterned metal wire sections electrically connects a plurality of weld pads on the active surface of a plurality of crystal grain; One patterned protective layer covers the other end of the metal wire sections of the metal wire sections of a plurality of patternings and expose portion patterning; Forming a plurality of conductive components, a plurality of conductive components are electrically connected on the other end of metal wire sections of each patterning that has exposed and a heat abstractor, is to be formed on the back side of packaging body.
Relevant characteristics and implementation of the present invention cooperate diagram to be described in detail as follows as most preferred embodiment now.
(for making purpose of the present invention, structure, feature and function thereof there are further understanding, cooperate embodiment to be described in detail as follows now.)
Description of drawings
Fig. 1 is the schematic diagram of expression prior art;
Fig. 2 is disclosed technology according to the present invention, at the vertical view of the encapsulating structure at the back side of the substrate with registration mark; And
Fig. 3 to Fig. 6 is disclosed technology according to the present invention, each step schematic diagram of the encapsulating structure that the method for packing that utilizes the crystal grain of wafer alignment sign to reconfigure forms;
Fig. 7 is disclosed technology according to the present invention, is the vertical view of presentation graphs 6;
Fig. 8 is disclosed technology according to the present invention, is to be illustrated in to form the schematic diagram that electrically connects on a plurality of light-emitting diodes;
Fig. 9 is disclosed technology according to the present invention, is illustrated in and forms the schematic diagram that electrically connects on a plurality of crystal grain;
Figure 10 A is disclosed technology according to the present invention, is to be illustrated in the schematic diagram that forms protective layer on a plurality of metal wire sections;
Figure 10 B is disclosed technology according to the present invention, is to be illustrated in the schematic diagram that forms a plurality of conductive components on the encapsulating structure;
Figure 11 is disclosed technology according to the present invention, and what be presentation graphs 8 along the BB line segment cuts open Shi Tu and Fig. 9 formula of cuing open figure along the CC line segment; And
Figure 12 A is disclosed technology according to the present invention, and expression has the schematic diagram of the encapsulating structure of heat abstractor; And
Figure 12 B is disclosed technology according to the present invention, and expression is through the schematic diagram of the encapsulating structure of thinning.
[primary clustering symbol description]
10 substrates
20 adhesion coatings
100 substrates
110 crystal grain
302 registration marks
305 micro treatmenting devices
310 crystal grain/memory device
312 weld pads
315 internal memory control device
320 light-emitting diodes
40 polymer material layers
410 Cutting Roads
50 metal wire sections
60 protective layers
70 conductive components
500 die devices
Embodiment
The present invention is the method for packing that a kind of crystal grain reconfigures in this direction of inquiring into, a plurality of crystal grain is reconfigured on another substrate the method that encapsulates then.In order to understand the present invention up hill and dale, detailed step and composition thereof will be proposed in following description.Obviously, execution of the present invention does not limit the specific details that skill person had the knack of of chip-stacked mode.On the other hand, the detailed step of last part technologies such as well-known chip generation type and chip thinning is not described in the details, with the restriction of avoiding causing the present invention unnecessary.Yet, for preferred embodiment of the present invention, can be described in detail as follows, yet except these were described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention do not limited, its with after claim be as the criterion.
In the semiconductor packaging process in modern times, all be that a wafer (wafer) of having finished FEOL (FrontEnd Process) is carried out thinning processing (Thinning Process) earlier, for example the thickness with chip is ground between 2～20mil; Then, the cutting (sawingprocess) of carrying out wafer is to form many crystal grain 110; Then, use fetching device (pick and place) that many crystal grain are positioned on another substrate 100, as shown in Figure 1 one by one.Clearly, the crystal grain interval region on the substrate 100 is bigger than crystal grain 110, therefore, and can be so that these be by 110 spacings with broad of crystal grain of being reapposed, so distribution that can the weld pad on the crystal grain 110 is suitable.In addition, the employed method for packing of present embodiment, the crystal grain 110 that wafer cut out in 12 o'clock can be reconfigured on the substrate of 8 o'clock wafers, so can effectively use the sealed in unit that promptly has of 8 o'clock wafers, and need not to re-establish the sealed in unit of 12 o'clock wafers, can reduce the packaging cost of 12 o'clock wafers.Be stressed that then, embodiments of the invention do not limit the substrate that uses 8 o'clock wafer sizes, as long as it can provide the function of carrying, for example: glass, quartz, pottery, circuit board or sheet metal (metal foil) etc., all can be used as the substrate 100 of present embodiment, so the shape of substrate 100 is not limited yet.
Please refer to Fig. 2, is that its back side of expression one substrate has the registration mark vertical view.As Fig. 2, be to be illustrated on the x-y direction at the back side on the upper surface of wafer substrate, be provided with a plurality of registration marks (alignment mark) 302.Known to prior statement, when a wafer (not expression in the drawings), for example have the wafer of a plurality of little processing crystal grain (microprocessor), the wafer that has the wafer of a plurality of internal memory crystal grain or have a plurality of internal memories control crystal grain through forming a plurality of crystal grain after the cutting, when again these crystal grain being configured in new substrate 10 one by one again, wherein the crystal grain on new substrate therefore, can the crystal grain of a plurality of identical functions and size, for example a memory modules on new substrate; Or by the crystal grain module that crystal grain constituted of difference in functionality and size, the crystal grain module of being formed by little processing crystal grain (microprocessor), internal memory crystal grain (memory) or internal memory control crystal grain (memorycontroller) for example.Because the crystal grain interval region between the new substrate 10 is bigger than the crystal grain of configuration again, the ball step (ball mount) of planting in follow-up packaging technology is understood and can't be aimed at, and conductive component (expression) in the drawings is formed on accurately desired position on the back side of crystal grain, and cause the reliability of encapsulating structure to reduce.Therefore, in specific embodiments of the invention, the mode that forms registration mark 302 can be utilized photoetch (photo-etching) technology, and it is to form a plurality of registration marks 302 at the back side of substrate and on the x-y direction, and it is shaped as the sign of cross.In addition, the mode that forms registration mark 302 also comprises utilizes laser label (laser mark) technology, to form a plurality of registration marks 302 on the back side of substrate.
Then, Fig. 3 to Fig. 6 is each step schematic diagram of the embodiment that reconfigures of expression the present invention disclosed crystal grain.At first, as shown in Figure 3, one substrate 10 is provided earlier, and on substrate 10, dispose an adhesion coating 20, this adhesion coating 20 is a rubber-like sticky material, for example silicon rubber (silicon rubber), silicones (silicon resin), elasticity PU, porous PU, acrylic rubber (acrylic rubber) or crystal grain cutting glue etc.Then, use fetching device (expression in the drawings) that adhesion coating 20 on the substrate 10 is placed and be pasted to a plurality of good crystal grain 310 one by one, wherein crystal grain 310 is to cover crystalline substance (flip chip) mode the weld pad on its active surface 312 to be connected with adhesion coating 20 on the substrate 10.In addition, be stressed that, in this fetching process, fetching device (expression) in the drawings can position according to a plurality of registration marks on registration mark on the back side of each crystal grain 310 302 and the reference substrate 10 (expression in the drawings) after, exactly each crystal grain 310 is connected with adhesion coating 20 on the substrate 10.Therefore, weld pad 312 positions on the active surface of each crystal grain 310 are known, so can solve the follow-up alignment issues of metal wire when connecting of carrying out.
Next, please continue with reference to figure 3, after a plurality of good crystal grain 310 have been placed and have been pasted to adhesion coating 20 on the substrate 10 exactly, then, in coating polymer material layer 40 on 310 on substrate 10 and the part crystal grain, wherein this polymer material layer 40 can be silica gel, epoxy resin, acrylic acid (acrylic), and benzocyclobutene materials such as (BCB); Then, use a die device 500 that polymer material layer 40 is flattened, make polymer material layer 40 form the surface of a planarization, and make polymer material layer 40 be filled between the crystal grain 310 and five faces of each crystal grain 310 coat by polymer material layer 40.
Then, can be optionally the polymer material layer 40 of planarization be carried out a baking program, so that polymer material layer 40 solidifies.Follow again, carry out demoulding program, with die device 500 with solidify after polymer material layer 40 separate, with the surface of the polymer material layer 40 that exposes planarization, as shown in Figure 4.Then, polymer material layer 40 is separated with adhesion coating 20, for example polymer material layer 40 is put into the groove of deionized water with substrate 10, polymer material layer 40 is separated with adhesion coating 20, form a packaging body; Each crystal grain 310 of this packaging body coats, and only expose weld pad 312 on the active surface of each crystal grain 310.Follow again, can optionally use cutter (not being shown among the figure) on the surface of polymer material layer 40, to form many Cutting Roads 410, as shown in Figure 4; The degree of depth of each Cutting Road 410 is 0.5～1 mil (mil), and the width of Cutting Road 410 then is 5 to 25 microns.In a preferred embodiment, this Cutting Road 410 can be mutual vertical interlaced, and the reference line when can be used as actual cutting crystal grain.Because the back side with respect to the active surface of crystal grain 310 at packaging body is formed with many Cutting Roads 410, therefore after polymer material layer 40 and substrate 10 are peeled off, stress on the packaging body can be offset by these Cutting Road 410 formed zones, so can solve the problem of packaging body warpage effectively.
Then, to Fig. 6, be to be illustrated in the vertical view that forms the metal wire sections of a plurality of patternings on a plurality of crystal grain 310 with reference to figure 5.In the present embodiment, with semiconductor technology each weld pad 312 on the active surface of a plurality of crystal grain 310 on the packaging body is all come out earlier.Then, can on the weld pad 312 of the active surface of crystal grain 310, form the metal wire sections 50 of a plurality of patternings, the outward extending two ends of each strip metal line segment 50 are that the mode with series connection electrically connects weld pad 312 on each adjacent crystal grain 310 respectively, and the step that forms the metal wire sections of a plurality of patternings comprises: at first, form a metal level 50A on each weld pad 312 of the active surface of each crystal grain 310, as shown in Figure 5; Then, utilize semiconductor process techniques, for example:, form a patterning photoresist layer (not expression in the drawings) earlier on metal level 50A in modes such as coating, development and etchings; Remove after the part metals layer 50A with etching mode then, again the photoresist layer of strip patternization; Therefore, can form the metal wire sections 50 of a plurality of patternings according to needed electric connection mode; And in the present embodiment, the outward extending two ends of the metal wire sections 50 of each patterning are a plurality of weld pads 312 that are electrically connected on each adjacent crystal grain 310, make that each adjacent crystal grain 310 is to electrically connect in the mode of connecting each other; Yet the electric connection mode of this series connection only is one embodiment of the invention, and its purpose is only disclosing the smithcraft of using patterning, a plurality of crystal grain can be finished connection according to desired electric connection mode.From the above mentioned, a plurality of crystal grain 310 can be formed a module (module) in the serial or parallel connection mode, for example: the DRAM module, as shown in Figure 6.In addition, metal wire sections 50 is formed by materials such as copper, gold or copper alloys, and simultaneously, metal wire sections 50 also can be to be formed by a UBM metal level, and the material of this UBM metal level can be Ti/Cu or TiW/Cu.
Be stressed that at this, the present invention is reconfiguring a plurality of good crystal grain 310 in the process of another substrate 10, owing to registration mark 302 is all arranged simultaneously further behind the position of a plurality of registration marks on the reference substrate 10 on the back side of each crystal grain 310, weld pad 312 positions on the active surface of each crystal grain 310 are known, so can solve the follow-up alignment issues of metal wire when connecting of carrying out.Therefore, after using macromolecular material 40 to form packaging body, because 5 faces of each crystal grain 310 are all coated by polymer material layer 40, only there is the weld pad 312 on the active surface of crystal grain 310 to come out, and weld pad 312 positions on this active surface are confirmable, so can be according to the disclosed mode of the present invention, a plurality of good crystal grain 310 identical or inequality are packaged together, and the metal wire 50 that forms patterning with semiconductor technology is electrically connected a plurality of crystal grain 310 that will be combined into module (MODULE) then.For example: with the DRAM crystal grain of 4 256M with polyphone or and the mode that connects be packaged together, form the memory module that memory capacity is 1G; Or, with a plurality of light-emitting diodes (LED) be concatenated into a column light source or and be linked to be a planar light source; Or, difference in functionality, different big or small die package being become a system etc., all can reach by present embodiment.Below will further instruction.
In addition, in the above-described embodiments, the mode that forms the polymer material layer 40 of planarization can select to use injection molded (molding process) to form.At this moment, a die device 500 is covered to substrate 10, and make 310 of die device 500 and crystal grain keep a space, therefore can be with polymer material layer 40, epoxy resin mould closure material (Epoxy MoldingCompound for example; EMC), inject the space of die device 500 and crystal grain 310, make polymer material layer 40 form the surface of a planarization and make polymer material layer 40 riddle between the crystal grain 310 and coat each crystal grain 310.Because, use injection molded to coat after each crystal grain 310, its manufacture process is identical with aforementioned manner, so repeat no more.
Then, please refer to Fig. 7, be the vertical view (being that Fig. 6 is the schematic diagram of Fig. 7 at the AA section) of above-mentioned Fig. 6.Fig. 7 is that expression is to utilize metal wire sections 50 to electrically connect to form a module in the mode of series connection between each crystal grain 310, and the crystal grain 310 that wherein can use four same size sizes and function (for example: DRAM) form crystal grain module or two crystal grain form a module.Certainly, also side by side crystal grain in twos can be connected into a module with series connection and mode in parallel.Yet,, can finish in the process via earlier figures 3 to Fig. 6 series connection of a plurality of crystal grain and together the mode of being connected in parallel.
Then, please refer to Fig. 8, is the schematic diagram that expression forms a LED light emitting module.As shown in Figure 8, crystal grain 320 is light-emitting diode (LED), and the P electrode 322 of each light-emitting diode 320 electrically connects with the P electrode 322 of adjacent light-emitting diode 320; And the N electrode 321 of light-emitting diode 320 to be N electrodes 321 with adjacent light-emitting diode 320 electrically connect, and the N electrode 321 of each light-emitting diode 320 and P electrode 322 are to electrically connect with weld pad 70 respectively by metal wire sections 50.Similarly, the present invention does not limit the quantity of light-emitting diode 320 or the mode of its electric connection yet, for example: with a plurality of light-emitting diodes (LED) be concatenated into a column light source or and be linked to be a planar light source; Simultaneously, the present invention does not limit the glow color of light-emitting diode 320 yet, promptly light-emitting diode 320 can be red light-emitting diode or green light LED or blue light-emitting diode or other color light-emitting diode (for example: white light) or the combination of aforementioned light-emitting diode etc.In addition, as shown in Figure 9, be the top view of the crystal grain envelope of difference in functionality or different sizes being finished encapsulation.Clearly, these crystal grain modules are the system in package (System-In-Package that are made of a plurality of crystal grain; SIP), these crystal grain comprise micro treatmenting device 305 (microprocessor means), memory device 310 (memory means) or internal memory control device 315 (memory controller means) at least; Wherein have a plurality of weld pads on the active surface of each crystal grain, and on the weld pad of each crystal grain, form many strip metals line segment, electrically connect adjacent crystal grain and electrically connect with conductive component with series connection or mode in parallel.
Aforementioned each crystal grain is finished modular encapsulation and is electrically connected after, and then, carry out the configuration of external coupling assembling.Shown in Figure 10 A; after finishing modular electric connection; immediately on the face with metal wire sections of packaging body; (for example: polyimide) metal wire sections 50 form a patterned protective layer 60 to cover a plurality of patternings; and on the part surface at the outward extending two ends of metal wire sections 50, form opening 62, so that expose the other end of the metal wire sections 50 of a plurality of patternings.This step that forms patterned protective layer 60 comprises: form a protective layer 60 on the metal wire sections 50 of a plurality of patternings; Utilize semiconductor technology, for example develop, form a patterned light blockage layer (not expression in the drawings) earlier on protective layer 60; Then; after developing; remove with respect to the protective layer on the outward extending two ends of the metal wire sections 50 of a plurality of patternings to form opening 62, can expose the part surface at the outward extending two ends of the metal wire sections 50 that is positioned at a plurality of patternings under the opening 62.
And then, shown in Figure 10 B, be to form a plurality of conductive components 70 at a plurality of openings 62 places of protective layer 60, wherein conductive component 70 can be tin ball (solder ball) or metal coupling (metal bump).At last, can cut packaging body, to form a plurality of modules of finishing encapsulation.Clearly, Figure 10 A and Figure 10 B are the packing forms of relative Fig. 7.In addition, as shown in figure 11, what be displayed map 8 along the BB line segment cuts open Shi Tu and Fig. 9 formula of cuing open figure along the CC line segment.
As the system in package (System-In-Package that Figure 11 shows that Fig. 9; SIP) time, in another preferred embodiment of the present invention, a fin can be pasted, shown in Figure 12 A on the back side of packaging body; Or select earlier by thinning technology, make that the back exposure of the crystal grain that packed body coats is come out after, stickup one fin on the back side of the crystal grain that has exposed again is shown in Figure 12 B.In addition, be stressed that the execution mode of this stickup fin also is useful among the embodiment of Fig. 7.Simultaneously, paste the time of fin, can be chosen in that packaging body cuts preceding or be chosen in after packaging body cuts is embodiments of the present invention all, and the present invention is not limited.
Though the present invention discloses as above with aforesaid preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of alike skill; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, therefore scope of patent protection of the present invention must be looked the appended claim person of defining of this specification and is as the criterion.
Claims (13)
1. modulated multi-die method for packing is characterized in that comprising:
A plurality of crystal grain are provided, and each this crystal grain has the back side of an active surface and relative this active surface, and disposes a plurality of weld pads on this active surface and this back side is provided with a plurality of registration marks;
Pick and place on those crystal grain to one substrates, each this crystal grain is to cover crystal type the adhesion coating that this active surface and is disposed on this substrate to be connected;
Form a polymer material layer on a lower surface of this substrate and those crystal grain of part;
This polymer material layer of planarization makes this polymer material layer riddle those intergranules and coats each this crystal grain;
Form a plurality of Cutting Roads on the surface of polymer material layer;
Break away from this substrate, with this active surface and each this weld pad that exposes each this crystal grain, to form a packaging body;
Form the metal wire sections of a plurality of patternings, the two ends of metal wire sections of those patternings of part electrically connect those weld pads on this active surfaces of those crystal grain, and an end of the metal wire sections of those patternings of part electrically connects those weld pads on this active surfaces of those crystal grain;
Form a patterned protective layer covering the metal wire sections of those patternings, and the other end of the metal wire sections of those patternings of expose portion;
Form a plurality of conductive components, those conductive components are electrically connected on the other end of metal wire sections of each this patterning that has exposed; And
Cut this packaging body, to form a plurality of modulated multi-die package constructions.
2. method for packing as claimed in claim 1 is characterized in that, those crystal grain are the internal memory with same size size.
3. method for packing as claimed in claim 1 is characterized in that, those crystal grain are made up of the different crystal grain of size dimension.
4. method for packing as claimed in claim 1 is characterized in that, the metal wire sections that forms those patternings comprises:
Form on a metal level those weld pads with this active surface of covering this each this crystal grain;
Form a patterned light blockage layer on this metal level; And
Remove this metal level of part, to remove the metal level on those weld pads of part, to form the metal wire sections of those patternings, wherein the two ends of metal wire sections of those patternings of part electrically connect a plurality of weld pads on this active surfaces of a plurality of crystal grain, and an end of the metal wire sections of those patternings of part electrically connects those weld pads on this active surfaces of those crystal grain.
5. method for packing that light-emitting diode reconfigures is characterized in that comprising:
A plurality of light-emitting diodes are provided, and each this light-emitting diode has the back side of an active surface and relative this active surface, and has a P electrode and a N electrode and this back side on this active surface and be provided with a plurality of registration marks;
Pick and place on those light-emitting diode to one substrates, each this light-emitting diode is to cover crystal type the adhesion coating that this active surface and is disposed on this substrate to be connected;
Form a polymer material layer on a lower surface of this substrate and those light-emitting diodes of part;
This polymer material layer of planarization makes this polymer material layer riddle between those light-emitting diodes and coats a lower surface of each this light-emitting diode;
Form a plurality of Cutting Roads on the surface of polymer material layer;
Break away from this substrate, with this active surface of exposing each this light-emitting diode and each this electrode to form a packaging body;
Form the metal wire sections of a plurality of patternings, an end of the metal wire sections of those patternings electrically connects each this P electrode and each this N electrode on this active surface of each this light-emitting diode respectively, and the other end then is connected to a metal wire sections to extension respectively altogether;
Form a patterned protective layer with metal wire sections that covers those patternings and the part surface that exposes this outward extending metal wire sections;
Form a plurality of conductive components, those conductive components are electrically connected on the surface of this outward extending metal wire sections that has exposed; And this packaging body of cutting, to form a plurality of modularized light emitting diode encapsulating structures.
6. method for packing as claimed in claim 5 is characterized in that, a back side of each this light-emitting diode has a pair of registration mark.
7. method for packing as claimed in claim 5 is characterized in that, those light-emitting diodes are selected in following group: red light-emitting diode, green light LED, blue light-emitting diode or white light emitting diode.
8. encapsulating structure that light-emitting diode reconfigures is characterized in that comprising:
A plurality of light-emitting diodes, each this light-emitting diode has the back side of an active surface and relative this active surface, disposes a P electrode and a N electrode and this back side on this active surface and is provided with a plurality of registration marks;
One packaging body, ring are overlying on five faces of each this light-emitting diode and expose this active surface and each this P electrode and each this N electrode of each this light-emitting diode;
The metal wire sections of a plurality of patternings, one end electrically connect each this P electrode and each this N electrode on this active surface of each this light-emitting diode respectively, and the other end then is connected to an outward extending metal wire sections respectively altogether;
One patterned protective layer in order to covering the metal wire sections of those patternings, and exposes the part surface of this outward extending metal wire sections; And
A plurality of conductive components are formed on the surface of this outward extending metal wire sections that has exposed, electrically connect to form.
9. encapsulating structure as claimed in claim 8 is characterized in that, a back side of each this light-emitting diode has a pair of registration mark.
10. encapsulating structure as claimed in claim 8 is characterized in that, those light-emitting diodes are to select in following group: red light-emitting diode, green light LED, blue light-emitting diode or white light emitting diode.
11. a modulated multi-die package construction is characterized in that comprising:
A plurality of crystal grain, each this crystal grain has the back side of an active surface and relative this active surface, disposes a plurality of weld pads on this active surface and this back side is provided with a plurality of registration marks;
One packaging body, ring are overlying on five faces of each this crystal grain and expose this active surface and each this weld pad of each this crystal grain;
The metal wire sections of a plurality of patternings, the two ends of metal wire sections of those patternings of part electrically connect those weld pads on the active surface of those crystal grain, and an end of the metal wire sections of those patternings of part electrically connects those weld pads on the active surface of those crystal grain;
One patterned protective layer covers the other end of the metal wire sections of the metal wire sections of those patternings and those patternings of expose portion;
Form a plurality of conductive components, those conductive components are electrically connected on the other end of metal wire sections of each this patterning that has exposed; And
One heat abstractor is to be formed on the back side of this packaging body.
12. encapsulating structure as claimed in claim 11 is characterized in that, those crystal grain are the crystal grain of identical function and size.
13. encapsulating structure as claimed in claim 11 is characterized in that, those crystal grain are the crystal grain of difference in functionality and size.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100031714A CN101488462B (en) | 2008-01-15 | 2008-01-15 | Modulated multi-die package construction and method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100031714A CN101488462B (en) | 2008-01-15 | 2008-01-15 | Modulated multi-die package construction and method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101488462A CN101488462A (en) | 2009-07-22 |
| CN101488462B true CN101488462B (en) | 2010-12-08 |
Family
ID=40891274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100031714A Expired - Fee Related CN101488462B (en) | 2008-01-15 | 2008-01-15 | Modulated multi-die package construction and method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101488462B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479726B (en) * | 2010-11-26 | 2014-01-22 | 矽品精密工业股份有限公司 | Manufacturing method of semiconductor packaging component |
| CN107038267B (en) * | 2016-02-04 | 2021-06-18 | 京微雅格（北京）科技有限公司 | Design method of basic unit of FPGA chip |
| CN109637564A (en) * | 2018-12-20 | 2019-04-16 | 惠州Tcl移动通信有限公司 | With more storage crystal grain storage devices and recognition methods |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5989982A (en) * | 1997-10-08 | 1999-11-23 | Oki Electric Industry Co., Ltd. | Semiconductor device and method of manufacturing the same |
| CN1340855A (en) * | 2000-08-31 | 2002-03-20 | 琳得科株式会社 | Method for manufacturing semiconductor device |
| US7196408B2 (en) * | 2003-12-03 | 2007-03-27 | Wen-Kun Yang | Fan out type wafer level package structure and method of the same |
| US7256066B2 (en) * | 2004-03-12 | 2007-08-14 | Advanced Semiconductor Engineering, Inc. | Flip chip packaging process |
-
2008
- 2008-01-15 CN CN2008100031714A patent/CN101488462B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5989982A (en) * | 1997-10-08 | 1999-11-23 | Oki Electric Industry Co., Ltd. | Semiconductor device and method of manufacturing the same |
| CN1340855A (en) * | 2000-08-31 | 2002-03-20 | 琳得科株式会社 | Method for manufacturing semiconductor device |
| US7196408B2 (en) * | 2003-12-03 | 2007-03-27 | Wen-Kun Yang | Fan out type wafer level package structure and method of the same |
| US7256066B2 (en) * | 2004-03-12 | 2007-08-14 | Advanced Semiconductor Engineering, Inc. | Flip chip packaging process |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101488462A (en) | 2009-07-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6897096B2 (en) | Method of packaging semiconductor dice employing at least one redistribution layer | |
| CN101477955B (en) | Encapsulation structure and method for tablet reconfiguration | |
| TWI423401B (en) | Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides | |
| US7888172B2 (en) | Chip stacked structure and the forming method | |
| US7198980B2 (en) | Methods for assembling multiple semiconductor devices | |
| TWI387077B (en) | Chip rearrangement package structure and the method thereof | |
| CN101621041B (en) | Packaging structure with reconfiguration chip and method thereof | |
| JP2003078106A (en) | Chip-stacked package and its manufacturing method | |
| KR20050022558A (en) | BGA package, manufacturing method thereof and stacked package comprising the same | |
| CN101477956B (en) | Encapsulation structure and method for tablet reconfiguration | |
| JP4919103B2 (en) | Land grid array semiconductor device package, assembly including the package, and manufacturing method | |
| CN101567322B (en) | Encapsulating structure and encapsulating method of chip | |
| CN106744646A (en) | MEMS chip encapsulating structure and method for packing | |
| CN101615583B (en) | Chip stacking structure forming method | |
| CN107958882A (en) | Encapsulating structure of chip and preparation method thereof | |
| CN101488462B (en) | Modulated multi-die package construction and method thereof | |
| CN101615584B (en) | Packaging method of chip reconfiguration structure | |
| CN101609822A (en) | Encapsulating structure that chip reconfigures and method thereof | |
| CN101436553B (en) | Method for manufacturing package structure with reconfigured chip by metal projection | |
| CN101452862B (en) | Encapsulation method with grains reconfigured | |
| CN100590823C (en) | Method for making registration mark used in packaging structure of crystal grain rearrangement | |
| CN101465299B (en) | Method for manufacturing grind used in encapsulation structure of chip reconfiguration | |
| US11616017B2 (en) | Integrated circuit package structure, integrated circuit package unit and associated packaging method | |
| TW200924133A (en) | Multichip package structure and the forming method thereof | |
| CN101447437B (en) | Encapsulation structure for reconfiguring crystal grain and preconfigured fan-out structure used thereinto |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101208 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |