CN101471665B - Analog-to-digital converter circuit using multi-stage amplifier partial multiplexing technique - Google Patents
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Abstract
The invention discloses an analog-digital converter circuit adopting a multistage amplifier partial multiplexing technology, which comprises a flash structure and at least one combined flow level, wherein the flash structure is used as the last flow level, the combined flow level comprises a first flow level and a second flow level, the first flow level is formed by sequentially connecting a first-level sub-amplifier A1, a second-level sub-amplifier A2 and a third-level sub-amplifier A3 in series, the second flow level is formed by sequentially connecting a second-level sub-amplifier A2, a third-level sub-amplifier A3 and a fourth-level sub-amplifier A4 in series, and the first flow level and the second flow level share the second-level sub-amplifier A2 and the third-level sub-amplifier A3. The invention reduces the power consumption of the amplifier and the system, and reduces the design complexity and the dynamic performance.
Description
Technical field
The present invention relates to the analog-digital converter circuit of the employing casacade multi-amplifier fractional reuse technology in production line analog-digital converter circuit engineering field, particularly a kind of low-voltage and low-power dissipation.
Background technology
Over the last couple of decades, the economic growth rate of China is up to 9.7%, and the energy resource consumption growth rate is 4.6%, far below the speed of economic growth.A few years from now on economy will keep the zooming impetus, and energy demand also will continue to rise.And along with to use the some areas cause and even the intensification gradually of global environment problem awareness because of the energy, the ambient pressure of China facing was also big more originally.
The National Program for Medium-to Long-term Scientific and Technological Development of promulgation on December 30th, 2005 has been set forth the target of high-new industry of China and energy industry development, in economic development from now on and technological progress, be embodied everywhere the principle of energy conservation priority.Propose according to the Lu Yongxiang president of the Chinese Academy of Sciences, to the year two thousand forty energy-consuming must accomplish zero growth rate, the development of China's national economy and the raising of living standards of the people then can only walk efficiently to utilize the energy-saving road of the energy.
The develop rapidly of deep submicron integrated circuit technology and handheld mobile device industry has brought the flourishing as never before of global electronic market.Handheld mobile device comprises handheld communication amusement and portable medical apparatus or the like, has suitable vast market potentiality and development prospect.More powerful, more the farm labourer makes the product of time and will take the good opportunity in market, therefore, the digital and analog circuit of high-performance low-power-consumption design just becoming one of focus of present research.But the high-speed high-performance analog to digital converter is just becoming one of system for restricting bottleneck of performance.
As the interface of radio frequency/intermediate frequency circuit and digital circuit, analog to digital converter is born and is become digital signal to enter the task that baseband circuit is further processed again analog signal conversion, the performance height of the good and bad directly decision systems of its performance.Therefore design high performance analog to digital converter and become one of the main product of domestic and international IC Chevron Research Company (CRC) and hot subject of institute already.
During required analog-to-digital converter resolution and switching rate require at present some applied environments and standard, the required analog to digital converter of popular HDTV (High-Definition Television) technology need 8 to 10, switching rate 50 to 75MS/sec.
Traditional high-performance analog to digital converter generally adopts BiCMOS technology or more good GaAs technology, reaches the high performance rapid rising that has brought chip cost simultaneously.And the development of wireless communication industry at present is badly in need of the circuit and the chip of more low-power consumption and is reached more performance.
Reach lower power consumption along with successively decreasing of CMOS technology device feature size makes circuit on higher operating frequency, this makes and adopts CMOS technology to realize that the analog to digital converter of high-performance low-power-consumption becomes possibility.Simultaneously, because digital circuit is more suitable for adopting CMOS technology to realize, for the consideration of cost, area, encapsulation, power consumption etc., digital circuit and simulation/radio circuit are integrated in in the chip piece like this, promptly so-called " SOC " become one of trend in the future.
But successively decreasing of CMOS technology device feature size makes that the working power voltage of chip is more and more lower, like this Design of Simulating Circuits proposed stern challenge.(supply voltage of low-power consumption chip in 2007 will be low to moderate 0.8V for Semiconductor Industry Association, the prediction of SIA) making according to international semiconductor TIA.Present considerable classical circuit structure can't be operated under this supply voltage, be applicable to more that meanwhile the circuit structure under the low supply voltage also will continue to bring out.
The successively decreasing of CMOS technology device feature size makes circuit be issued to lower power consumption in higher operating frequency becomes possibility.But present low power dissipation design exists following difficult point: at first, when supply voltage is reduced to 3V even when lower, for the performance of holding circuit constant, the operating current of circuit also must remain unchanged accordingly (even bigger), simultaneously in order to suppress the influence of thermal noise, big load capacitance is indispensable, and this makes that the lifting of operating frequency is very difficult, so low power dissipation design never is to reduce circuit voltage and device size in proportion; Secondly, at present popular many classics or by correlation technique in addition improved circuit structure all no longer be applicable under the low supply voltage.For example as, when supply voltage is under 5V or the 3.3V, adopt single tube can well be applied in the switched-capacitor circuit as switch, be reduced under the 1.8V and work as supply voltage, can adopt the multiplication of voltage technology to improve the control voltage of switching tube, reduce the conducting resistance of switch; When voltage was reduced to 1V, because the consideration of puncture voltage and working life, the multiplication of voltage technology also was restricted, and the performance of circuit has been subjected to very big influence like this, and therefore the single tube switching circuit also is eliminated.These restrictions have brought sizable difficulty all for the design of low-power consumption analog to digital converter.
Production line analog-digital converter can in high-performance and low-power consumption, reach one well compromise, in being suitable for/at a high speed and in the high-precision adc application scenario.The production line analog-digital converter without calibration up to 14 has report at present, and the production line analog-digital converter of employing time interleaving mode has reached the conversion speed of 11 1Gs/s.In analog to digital converter, mainly depend on the electric capacity matching precision of setting up precision and MDAC of operational amplifier by the remainder precision of MDAC generation, the power consumption of operational amplifier has then determined the overall power of analog to digital converter, especially for the production line analog-digital converter of high-resolution and high linearity, the power consumption of operational amplifier becomes dominant force.
At present existing a lot of documents relate to the power consumption that correlation technique reduces production line analog-digital converter.Reduces supply voltage and can directly reduce circuit power consumption, but the thing followed is the reduction of signal swing that in order to suppress thermal noise, sampling capacitance also must increase thereupon, keeps identical performance thereby must increase circuital current.
The power consumption of analog to digital converter mainly comes from operational amplifier.In general production line analog-digital converter, wherein each grade thick sign indicating number of generation numeral and the reconstruction remainder signal that offers next stage.General pipeline organization adopts capacitor array MDAC to finish and removes all functions that produce the thick sign indicating number of numeral, comprises subtracting each other and accurately doubly taking advantage of.The operation principle of each grade is summarized as follows: in sample phase, input signal is sampled maintenance, compares the thick sign indicating number of output numeral with reference level, and at amplification stage, the reconstruction signal that input signal and MDAC produce subtracts each other, and outputs to next stage through accurately doubly taking advantage of again.In order to realize that the redundant correction of numeral overcomes the restriction of non-ideal factors such as comparator and operational amplifier offset, this gain of accurately doubly taking advantage of has only half under the ideal case.Therefore, operational amplifier is only in amplification stage work, and is idle condition in sample phase, therefore can share at the operational amplifier of sample phase and another grade amplification stage to reduce the operational amplifier power consumption.
The basic principle of operational amplifier technology of sharing is to share the operation amplifier circuit in not at the same level in the streamline, makes this circuit keep operating state in the different stages.In sample phase, because the operational amplifier of this grade is not used, the input node of this circuit disconnects with a grade interior sampling capacitance, and this node links to each other with another grade capacitor array that is in magnifying state simultaneously, finishes the function that it subtracts each other and accurately doubly takes advantage of.In different clock phases, two different pipelining-stages have only adopted an amplifier to finish the remainder enlarging function like this.The number of amplifier reduces by half like this, has reduced the area of the power consumption of entire circuit simultaneously.It should be noted that because amplifier all keeps operating state in sampling and amplification stage, so the input point of amplifier is not set and makes zero, this input offset voltage that just means amplifier is determined by remainder voltage and the 1/f noise of last time simultaneously.
In addition, the operational amplifier multiplex technique is suggested, this technology is by independently amplifier is stacked realizes with two, these two shared same tail current sources of amplifier independently, this technology has solved the problem of importing extra time-delay in node set problem and the switching amplifier technology in the operational amplifier technology of sharing, less power consumption and area have only been increased simultaneously, there is following problem in this technology, because the output node of amplifier is shared by different pipelining-stages, therefore output node is not set and makes zero, and makes remainder doubly take advantage of corresponding increase settling time of amplification.
Because the input analog signal becomes digital signal to have a time-delay to this conversion of signals in production line analog-digital converter, in fact, production line analog-digital converter promptly is to sacrifice this to delay time and obtain high-performance and low-power consumption simultaneously, and this time-delay is not much often having performance and power consumption so important in the application.Trsanscondutance amplifier is a module indispensable in the production line analog-digital converter.Along with the renewal of CMOS technology, the reducing of supply voltage and transistor feature size makes Design of Amplifier become increasingly complex.At present the tube-in-tube structure trsanscondutance amplifier that widely adopts can be easy to obtain very high output impedance and design difficulty little; When supply voltage reduces, utilizable voltage margin more and more hour, foldable structure has obtained using widely; And when voltage was lower than 2V, the circuit performance of these two kinds of structures descended even can not work.And multistage trsanscondutance amplifier adopts multistage gain stage to improve the DC current gain of amplifier, but thereby every grade output resistance and electric capacity all can bring limit to influence the stability of circuit, therefore multistage trsanscondutance amplifier has often adopted the compensation technique of various complexity to improve the stable of system, and is more and more higher to designing requirement.
Adopting casacade multi-amplifier to be actually keeping in analog to digital converter sacrifices power consumption and reaches lower operating voltage under the constant situation of performance, this point is not wish to see in many mobile communication application environment, because higher power consumption promptly means the operating time still less.And in low-power consumption assembly line a/d converter, adopt that the multiplexing technology of amplifier is verified can to reduce system power dissipation greatly, but meanwhile, in order to make that amplifier can be multiplexing by multi-stage pipeline, in order to control complicated sequential and circuit structure, too much switch has brought a large amount of electric charges to inject noise and clock feed-through effect.
In addition, traditional two phase clock control amplifier amplifies and reset (perhaps from making zero) hockets, and in the amplifier multiplexing structure, amplifier will be born the amplification task of two stage pipeline structure, make to reset or make zero certainly and can't carry out, greatly reduce performance settling time of its amplification stage.
Therefore, the design proposes the multiplexing technology of amplifier section and solves the problems referred to above, compare traditional amplifier multiplex technique, comparatively simple topology is adopted in this design, significantly reduced the number of switch, can utilize simultaneously the amplifier of idle state to lack of proper care to eliminate or output voltage makes zero, improve the performance of system.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is to provide a kind of analog-digital converter circuit that adopts casacade multi-amplifier fractional reuse technology, with the power consumption of step-down amplifier and system, reduces design complexities and dynamic property.
(2) technical scheme
In order to achieve the above object, technical scheme of the present invention is achieved in that
A kind of analog-digital converter circuit that adopts casacade multi-amplifier fractional reuse technology, this analog to digital converter is made of a flash structure and at least one combination pipelining-stage, described flash structure is as the afterbody pipelining-stage, described combination pipelining-stage comprises first pipelining-stage and second pipelining-stage, described first pipelining-stage is by the sub-amplifier A1 of the first order, sub-amplifier A2 in the second level and the sub-amplifier A3 of the third level are followed in series to form, described second pipelining-stage is by the sub-amplifier A2 in the second level, sub-amplifier A3 of the third level and the sub-amplifier A4 of the fourth stage are followed in series to form, sub-amplifier A2 in described first pipelining-stage and the shared second level of second pipelining-stage and the sub-amplifier A3 of the third level;
Wherein, when described first pipelining-stage is in amplification stage, the sub-amplifier A1 of the first order, the sub-amplifier A2 in the second level and the sub-amplifier A3 of the third level form multistage trsanscondutance amplifier and finish accurate enlarging function, and the sub-amplifier A4 of the fourth stage closes it for the consideration of saving power consumption; This moment, described second pipelining-stage was in sample phase, will go up handled signal of a clock cycle and be saved on the sampling capacitance; When the described first pipelining-stage amplification stage finishes the beginning sample phase, described second pipelining-stage begins amplification stage, the sub-amplifier A2 in the second level, the sub-amplifier A3 of the third level and the sub-amplifier A4 of the fourth stage finish the amplification task of second level pipelining-stage input signal, and this moment, the first order sub-amplifier A1 carried out from rezero operation, and the offset voltage of the sub-amplifier A1 of the first order is stored on the input capacitance of amplifier.
In the such scheme, sub-amplifier A2 in the described second level and the sub-amplifier A3 of the third level are multiplex circuit, are used for enlarging function with second pipelining-stage in the different stages by first pipelining-stage.
In the such scheme, the sub-amplifier A1 of the described first order uses when not working from making zero, and eliminates the influence of offset voltage.
In the such scheme, the sub-amplifier A4 of the described fourth stage is used for output voltage is made zero when not working, and reduces output voltage swing, reduces the settling time of amplification stage.
In the such scheme, described first pipelining-stage that is followed in series to form by the sub-amplifier A1 of the first order, the sub-amplifier A2 in the second level and the sub-amplifier A3 of the third level adopts the network miller capacitance compensation technique NMCNR of zero suppression resnstance transformer to realize that the amplifier of production line analog-digital converter designs.
In the such scheme, described second pipelining-stage that is followed in series to form by the sub-amplifier A2 in the second level, the sub-amplifier A3 of the third level and the sub-amplifier A4 of the fourth stage adopts the network Miller capacitance compensation technique RNMCNR of upset zero suppression resnstance transformer to realize that the amplifier of production line analog-digital converter designs.
In the such scheme, described first pipelining-stage and second pipelining-stage adopt the network miller capacitance compensation technique NMCNR of zero suppression resnstance transformer and the staggered handoff technique of network Miller capacitance compensation technique RNMCNR of upset zero suppression resnstance transformer simultaneously.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, the analog-digital converter circuit of this employing casacade multi-amplifier fractional reuse technology provided by the invention, by the parton circuit in the shared casacade multi-amplifier, the quantity of operational amplifier is reduced to traditional 2/3rds, reduced the power consumption of system, adopt the network miller capacitance compensation technique (NMCNR) of zero suppression resnstance transformer and the staggered handoff technique of network Miller capacitance compensation technique (RNMCNR) of upset zero suppression resnstance transformer simultaneously, reduced design complexities and dynamic property.
2, the analog-digital converter circuit of this employing casacade multi-amplifier fractional reuse technology provided by the invention, in the advantage while of inheriting tradition multiplex technique, also the output point of pair amplifier is reined in the processing of making zero, and has reduced the settling time of circuit, has reduced the power consumption of amplifier.
3, the analog-digital converter circuit of this employing casacade multi-amplifier fractional reuse technology provided by the invention, adopt multistage amplifier circuits to make the gain of single-level circuit and bandwidth requirement reduce greatly, simplified the design of sub-amplifier circuit, above technology makes production line analog-digital converter can be operated in lower supply voltage.
4, the analog-digital converter circuit of this employing casacade multi-amplifier fractional reuse technology provided by the invention, adopt the production line analog-digital converter structure of casacade multi-amplifier fractional reuse technology novelty, be suitable for the necessary low supply voltage of following CMOS technology, wide application prospect is arranged.
5, the analog-digital converter circuit of this employing casacade multi-amplifier fractional reuse technology provided by the invention, utilize the reorganization of each submodule of casacade multi-amplifier, providing flexibly outside the production line analog-digital converter sampling-enlarging function module, this technology can minimize the multiplexing extra switch number that increases of amplifier, greatly reduces the decreased performance that switch brings; Utilize the amplifier outside multiplexing to make the MDAC module of analog to digital converter can lack of proper care easily simultaneously from making zero and the output buffer dynamic operation.
Description of drawings
Fig. 1 is the structural representation of the analog-digital converter circuit of employing casacade multi-amplifier fractional reuse technology provided by the invention;
Fig. 2 is the structural representation according to the analog-digital converter circuit of the employing casacade multi-amplifier fractional reuse technology of the embodiment of the invention;
Fig. 3 is the structural representation of combination pipelining-stage among Fig. 2;
Fig. 4 is the sequential scheduling figure of the analog-digital converter circuit of employing casacade multi-amplifier fractional reuse technology provided by the invention in the phase I;
Fig. 5 is the sequential scheduling figure of the analog-digital converter circuit of employing casacade multi-amplifier fractional reuse technology provided by the invention in second stage;
Fig. 6 is the schematic diagram that needs two kinds of different collocation structures in the casacade multi-amplifier fractional reuse technology.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The production line analog-digital converter structure of employing casacade multi-amplifier fractional reuse technology provided by the invention is suitable for the necessary low supply voltage of CMOS technology in the future, and wide application prospect is arranged.In addition, this technology is utilized the reorganization of each submodule of casacade multi-amplifier, providing flexibly outside the production line analog-digital converter sampling-enlarging function module, this technology can minimize the multiplexing extra switch number that increases of amplifier, the decreased performance that greatly reduces switch like this and brought.Utilize amplifier outside multiplexing to make the MDAC module of analog to digital converter simultaneously, can lack of proper care easily from making zero and the output buffer dynamic operation.
As shown in Figure 1, Fig. 1 is the structural representation of the analog-digital converter circuit of employing casacade multi-amplifier fractional reuse technology provided by the invention, and this analog to digital converter is made of a flash structure and at least one combination pipelining-stage.Described flash structure is as the afterbody pipelining-stage.Described combination pipelining-stage comprises first pipelining-stage and second pipelining-stage, described first pipelining-stage is followed in series to form by the sub-amplifier A1 of the first order, the sub-amplifier A2 in the second level and the sub-amplifier A3 of the third level, and described second pipelining-stage is followed in series to form by the sub-amplifier A2 in the second level, the sub-amplifier A3 of the third level and the sub-amplifier A4 of the fourth stage.The structure of first pipelining-stage and second pipelining-stage can be with reference to Fig. 3.
Sub-amplifier A2 in described first pipelining-stage and the shared second level of second pipelining-stage and the sub-amplifier A3 of the third level.Sub-amplifier A2 in the described second level and the sub-amplifier A3 of the third level are multiplex circuit, are used for enlarging function with second pipelining-stage in the different stages by first pipelining-stage.When the sub-amplifier A1 of the first order uses from making zero, eliminate the influence of offset voltage when not working.Sub-amplifier A4 is used for output voltage is made zero when not working when the fourth stage, reduces output voltage swing, reduces the settling time of amplification stage, and improves performance and reduce power consumption.
Described first pipelining-stage that is followed in series to form by the sub-amplifier A1 of the first order, the sub-amplifier A2 in the second level and the sub-amplifier A3 of the third level adopts the network miller capacitance compensation technique (NMCNR) of zero suppression resnstance transformer to realize that the amplifier of production line analog-digital converter designs.Described second pipelining-stage that is followed in series to form by the sub-amplifier A2 in the second level, the sub-amplifier A3 of the third level and the sub-amplifier A4 of the fourth stage adopts the network Miller capacitance compensation technique (RNMCNR) of upset zero suppression resnstance transformer to realize that the amplifier of production line analog-digital converter designs.Described first pipelining-stage and second pipelining-stage adopt the network miller capacitance compensation technique (NMCNR) of zero suppression resnstance transformer and the staggered handoff technique of network Miller capacitance compensation technique (RNMCNR) of upset zero suppression resnstance transformer simultaneously.
When described first pipelining-stage is in amplification stage, the sub-amplifier A1 of the first order, the sub-amplifier A2 in the second level and the sub-amplifier A3 of the third level form multistage trsanscondutance amplifier and finish accurate enlarging function, and the sub-amplifier A4 of the fourth stage closes it for the consideration of saving power consumption; This moment, described second pipelining-stage was in sample phase, will go up handled signal of a clock cycle and be saved on the sampling capacitance.
When the described first pipelining-stage amplification stage finishes the beginning sample phase, described second pipelining-stage begins amplification stage, the sub-amplifier A2 in the second level, the sub-amplifier A3 of the third level and the sub-amplifier A4 of the fourth stage finish the amplification task of second level pipelining-stage input signal, and this moment, the first order sub-amplifier A1 carried out from rezero operation, and the offset voltage of the sub-amplifier A1 of the first order is stored on the input capacitance of amplifier.
With 10bit, the 40Ms/s production line analog-digital converter is an example, this structural module transducer as shown in Figure 2, Fig. 2 is the structural representation according to the analog-digital converter circuit of the employing casacade multi-amplifier fractional reuse technology of the embodiment of the invention.This analog to digital converter is divided into Pyatyi, and wherein preceding level Four is every grade of 2.5bit, and afterbody is the flash structure of 2bit.
Traditional amplifier is multiplexing to be a shared independent amplifier between adjacent two-stage, in order to make that amplifier can be multiplexing at different inter-stages, must adopt complicated sequencing control to dispatch, increase a large amount of switches like this, make systematic function descend.
And in the described production line analog-digital converter of Fig. 2, amplifier is altogether by the sub-amplifier A1 of level Four, A2, A3 and A4 form (as shown in Figure 3), two-stage A2 and A3 are multiplex circuit wherein, be used for enlarging function by front and back stages in the different stages, and the sub-amplifier A1 of the first order can be with from making zero idle the time, eliminate the influence of offset voltage, the sub-amplifier A4 of afterbody can be used for output voltage is made zero in the time of idle, make that like this output voltage swing has reduced half, reduce the settling time of amplification stage, reduced power consumption when improving performance.
Refer again to Fig. 3, shown in the solid box is the required multistage trsanscondutance amplifier of the first pipelining-stage amplification stage, and frame of broken lines is depicted as the required multistage trsanscondutance amplifier of the second pipelining-stage amplification stage.When first pipelining-stage is in amplification stage, amplifier A1, A2 and A3 form multistage trsanscondutance amplifier and finish accurate enlarging function, A4 closes it for the consideration of saving power consumption, this moment, second pipelining-stage was in sample phase, and it will be gone up handled signal of a clock cycle and be kept on the sampling capacitance; When the first pipelining-stage amplification stage finishes the beginning sample phase, second pipelining-stage begins amplification stage, amplifier A2, A3 and A4 finish the amplification task of second level pipelining-stage input signal, and this moment, amplifier A1 carried out from rezero operation, the offset voltage of amplifier A1 is stored on the input capacitance of amplifier, because total offset voltage of cascade amplifier mainly determined by the offset voltage of first order amplifier, so the offset voltage of next clock cycle first pipelining-stage when utilizing amplifier A1, A2 and A3 to finish amplifieroperation eliminated.
This technology can be applied to single channel and channel structure.With the binary channels is example, in the time of the sampling of the previous stage of first passage after one-level amplify, and second passage is identical with it, adopts the diphasic clock that do not overlap to come the control circuit sequential, is divided into two stages, the phase I, concrete sequential scheduling can be seen Fig. 4.
In the phase I, the electric capacity on higher level's (i.e. the first half among the figure) left side first input value V1 that samples, n, the electric capacity on the right then is used to amplify V2, n, and A1 can be with from making zero in the time of sampling, also can close and save power consumption, A2, A3 and A4 have then formed three grades of trsanscondutance amplifiers of NMCNR (Nested Miller Compensation with Nulling Resistor), are used for signal is amplified, and amplifying signal is then sampled by the electric capacity on subordinate's (i.e. the latter half among the figure) left side; And this moment A2, the A3 of subordinate and A4 form amplifier and amplify the signal V1 that a last sequential is sent here, n-1.
The concrete sequential scheduling of second stage can be seen Fig. 5.In second stage, the next one value V2 of second input value of electric capacity sampling on higher level's (i.e. the first half among the figure) the right, n+1, the electric capacity on the input left side of amplifier then is used to amplify V1 at this moment, n, and A4 can be used for exporting and make zero this moment, also can close and save power consumption, A1, A2 and A3 have then formed three grades of trsanscondutance amplifiers of NMCNR, are used for signal is amplified, and amplifying signal is then by the electric capacity sampling on subordinate's (i.e. the latter half among the figure) the right; And this moment A1, the A2 of subordinate and A3 form amplifier and amplify the signal V1 ' that a last sequential is sent here, n.
The present invention adopts different CMCNR casacade multi-amplifier structures to realize high-gain amplifier.In described casacade multi-amplifier fractional reuse technology, need two kinds of different collocation structures, as shown in Figure 6.
Through deriving, the third stage amplifier of these two kinds of structures has similar transfer function expression formula.Amplifier architecture with the left side is an example, and it is as follows to derive the transfer function expression formula:
Wherein gm is the mutual conductance of the sub-amplifier of the first order and the second level, and R is output impedance, and gmt is the mutual conductance of the sub-amplifier of the third level, and Rt is output impedance, and Cl is output impedance, and Cm1 and Cm2 are miller compensation electric capacity, and Rm is the zero suppression compensating resistance.
We define kg=gm/gmt, and Rm=1/gmt is set, Cm1=4*kg*CL, and Cm1=2*kg/ (1-kg) * CL, then following formula can abbreviation be:
This moment, non-dominant pole was:
p
2，3＝(g
mt/2(1-kg)C
L)±j(g
mt/2(1-kg)C
L) (3)
Unity gain bandwidth is:
GBW＝1/4(g
mt/C
L) (4)
Consider left half-plane zero point, then the phase margin of this amplifier is generally greater than 60 degree.The expression formula that in like manner can release last figure the right circuit structure is similar above-mentioned.Be worth arousing attention be in the gmt on the left side structure for the third level then is the second level in the structure on the right, this problem can solve by the tail current source of adjusting amplifier.
So far, be appreciated that the production line analog-digital converter structure of employing casacade multi-amplifier fractional reuse technology novelty provided by the invention, be suitable for the necessary low supply voltage of following CMOS technology, wide application prospect is arranged.In addition, this technology is utilized the reorganization of each submodule of casacade multi-amplifier, providing flexibly outside the production line analog-digital converter sampling-enlarging function module, this technology can minimize the multiplexing extra switch number that increases of amplifier, the decreased performance that greatly reduces switch like this and brought; Utilize the amplifier outside multiplexing to make the MDAC module of analog to digital converter can lack of proper care easily simultaneously from making zero and the output buffer dynamic operation.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. analog-digital converter circuit that adopts casacade multi-amplifier fractional reuse technology, it is characterized in that, this analog to digital converter is made of a flash structure and at least one combination pipelining-stage, described flash structure is as the afterbody pipelining-stage, described combination pipelining-stage comprises first pipelining-stage and second pipelining-stage, described first pipelining-stage is by the sub-amplifier A1 of the first order, sub-amplifier A2 in the second level and the sub-amplifier A3 of the third level are followed in series to form, described second pipelining-stage is by the sub-amplifier A2 in the second level, sub-amplifier A3 of the third level and the sub-amplifier A4 of the fourth stage are followed in series to form, sub-amplifier A2 in described first pipelining-stage and the shared second level of second pipelining-stage and the sub-amplifier A3 of the third level;
Wherein, when described first pipelining-stage is in amplification stage, the sub-amplifier A1 of the first order, the sub-amplifier A2 in the second level and the sub-amplifier A3 of the third level form multistage trsanscondutance amplifier and finish accurate enlarging function, and the sub-amplifier A4 of the fourth stage closes it for the consideration of saving power consumption; This moment, described second pipelining-stage was in sample phase, will go up handled signal of a clock cycle and be saved on the sampling capacitance; When the described first pipelining-stage amplification stage finishes the beginning sample phase, described second pipelining-stage begins amplification stage, the sub-amplifier A2 in the second level, the sub-amplifier A3 of the third level and the sub-amplifier A4 of the fourth stage finish the amplification task of second level pipelining-stage input signal, and this moment, the first order sub-amplifier A1 carried out from rezero operation, and the offset voltage of the sub-amplifier A1 of the first order is stored on the input capacitance of amplifier.
2. the analog-digital converter circuit of employing casacade multi-amplifier fractional reuse technology according to claim 1, it is characterized in that, sub-amplifier A2 in the described second level and the sub-amplifier A3 of the third level are multiplex circuit, are used for enlarging function with second pipelining-stage in the different stages by first pipelining-stage.
3. the analog-digital converter circuit of employing casacade multi-amplifier fractional reuse technology according to claim 1 is characterized in that, the sub-amplifier A1 of the described first order uses when not working from making zero, and eliminates the influence of offset voltage.
4. the analog-digital converter circuit of employing casacade multi-amplifier fractional reuse technology according to claim 1, it is characterized in that, the sub-amplifier A4 of the described fourth stage is used for output voltage is made zero when not working, and reduces output voltage swing, reduces the settling time of amplification stage.
5. the analog-digital converter circuit of employing casacade multi-amplifier fractional reuse technology according to claim 1, it is characterized in that, described first pipelining-stage that is followed in series to form by the sub-amplifier A1 of the first order, the sub-amplifier A2 in the second level and the sub-amplifier A3 of the third level adopts the network miller capacitance compensation technique of zero suppression resnstance transformer to realize that the amplifier of production line analog-digital converter designs.
6. the analog-digital converter circuit of employing casacade multi-amplifier fractional reuse technology according to claim 1, it is characterized in that, described second pipelining-stage that is followed in series to form by the sub-amplifier A2 in the second level, the sub-amplifier A3 of the third level and the sub-amplifier A4 of the fourth stage adopts the network Miller capacitance compensation technique of upset zero suppression resnstance transformer to realize that the amplifier of production line analog-digital converter designs.
7. the analog-digital converter circuit of employing casacade multi-amplifier fractional reuse technology according to claim 1, it is characterized in that described first pipelining-stage and second pipelining-stage adopt the staggered handoff technique of the network Miller capacitance compensation technique of the network miller capacitance compensation technique of zero suppression resnstance transformer and the zero suppression resnstance transformer that overturns simultaneously.
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| CN2007103042186A CN101471665B (en) | 2007-12-26 | 2007-12-26 | Analog-to-digital converter circuit using multi-stage amplifier partial multiplexing technique |
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| CN2007103042186A CN101471665B (en) | 2007-12-26 | 2007-12-26 | Analog-to-digital converter circuit using multi-stage amplifier partial multiplexing technique |
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| JP2012227775A (en) * | 2011-04-20 | 2012-11-15 | Sony Corp | Analog-digital converter and signal processing system |
| CN104734646B (en) * | 2015-04-13 | 2018-11-23 | 无锡新硅微电子有限公司 | Single miller capacitance frequency compensation method applied to multistage amplifier circuit |
| CN104836585B (en) * | 2015-05-21 | 2019-01-18 | 豪威科技(上海)有限公司 | Gradual approaching A/D converter |
| CN105978496A (en) * | 2015-10-28 | 2016-09-28 | 温州墨熵微电子有限公司 | Frequency compensation technology for optimizing conversion speeds of operational amplifiers |
| CN107666288B (en) * | 2017-09-20 | 2021-02-02 | 西安电子科技大学 | High-gain large-bandwidth three-stage operational amplifier suitable for pipeline analog-to-digital converter |
| CN112690799A (en) * | 2020-12-25 | 2021-04-23 | 南京邮电大学 | Low-power consumption chopper amplifier circuit |
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