CN101452883A

CN101452883A - Semiconductor device and its making method and liquid spraying apparatus

Info

Publication number: CN101452883A
Application number: CNA2008101750029A
Authority: CN
Inventors: 下津佐峰生; 藤田桂; 早川幸宏
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 2000-12-28
Filing date: 2001-12-28
Publication date: 2009-06-10
Also published as: CN1825611A

Abstract

A semiconductor device comprises an insulated gate field effect transistor integrated in a first conductivity type well on a second conductivity type substrate; a conversion device is the insulated gate type FET, each transistor including: a semiconductor substrate to form the main surface of the second conductive type first semiconductor region; and the first semiconductor area formed to provide channel adjacent the first conductive type 1 The second semiconductor region; in the second side of the semiconductor surface to form the second conductive type source region; in the first side of the semiconductor surface to form the second conductive type drain area; and in the channel formed by a number of areas on the gate electrode , between the gate insulating film has; the second concentration of impurities in the semiconductor area is higher than the first semiconductor region; tied settings set up between the two missed the second semiconductor zone horizontal isolation area will be missed.

Description

Semiconductor device, method of manufacturing the same, and liquid ejecting apparatus

The present application is a divisional application of an invention patent application having an application number of 200510125188.3, an application date of 2001, 12 and 28, and an invention title of "semiconductor device and manufacturing method thereof, and liquid ejecting apparatus". Specifically, the present application is a divisional re-application of an invention patent application having an application number of 01145787.2, an application date of 2001, 12 and 28, and an invention title of "semiconductor device and manufacturing method thereof, and liquid ejecting apparatus".

Technical Field

The invention relates to a semiconductor device, a method of manufacturing the same, and a liquid ejecting apparatus. In particular, the present invention relates to a liquid ejecting apparatus usable for a recording apparatus such as a copying machine, a facsimile machine, a word processor, a computer, or the like as an output terminal of an information apparatus; to an apparatus for manufacturing a deoxyribonucleic acid (DNA) chip, an organic transistor, a color filter, etc. The present invention also relates to a semiconductor device which can be suitably used for the liquid ejecting apparatus and a method of manufacturing the same.

Background

The liquid ejecting apparatus is explained with a recording apparatus such as an ink jet printer shown in the drawing.

A conventional recording apparatus is equipped with an electrothermal conversion element as its recording head herein and a semiconductor device that drives the electrothermal conversion element (hereinafter referred to as "electrothermal conversion element driving semiconductor device").

Fig. 38 is a sectional view showing a partial sectional structure of a conventional ink jet recording head. Reference numeral 101 denotes a semiconductor substrate made of single crystal silicon.

Reference numeral 102 denotes an N-type well region, and reference numeral 108 denotes a drain region; reference numeral 115 denotes an N-type field attenuation drain region; reference numeral 107 denotes an N-type source region; reference numeral 104 denotes a gate. These elements constitute an electrothermal conversion element driving semiconductor device 130 using a metal-insulator-semiconductor (MIS) type field effect transistor.

Further reference numeral 117 denotes a silicon oxide layer as a thermal storage layer and an insulator layer; reference numeral 118 denotes a tantalum nitride film as a heat resistor layer; reference numeral 119 denotes an aluminum alloy film as wiring; and reference numeral 120 denotes a silicon nitride film as a protective film. All of the above elements constitute a substrate 140 of the recording head.

Here, reference numeral 150 denotes a heating portion, and reference numeral 160 denotes an ink ejecting portion. Further, the top plate 170 constitutes a liquid passage 180 together with the substrate 140.

Japanese laid-open patent publication nos. 5-185594, 6-069497, 10-034898, and the like disclose other electrothermal conversion element driving semiconductor devices.

Now, despite many improvements made to the recording head of the conventional structure and the electrothermal conversion element-driving semiconductor device, further demands have been recently made on the following properties of these products: can be driven at high speed, uses less energy, has high integration, low production cost and high performance. Especially, the high integration density of the switching devices in the conventional recording head structure is insufficient. Moreover, a breakdown voltage drop in operation of a conventional recording head structure more readily causes the substrate potential (i.e., the pinning potential) to rise.

Further, Japanese patent laid-open Nos. 62-098764, 5-129597, 8-097410, 9-307110, etc. disclose the structure of the electrothermal conversion element-driving semiconductor device.

When driving an electrothermal transducer element with an insulated gate transistor, in addition to the increase of the breakdown voltage thereof, the following properties are required to be improved: the high-speed driving can be realized, less energy is used, and the high integration is realized; low production cost and high performance. In particular, when transistor devices are integrated at high density in conventional semiconductor device structures, the transistor devices have insufficient uniformity of performance.

Disclosure of Invention

It is a 1 st object of the present invention to provide a semiconductor device, a method of manufacturing the same, and a liquid ejecting apparatus. The invention can reduce the occupied area of the conversion device on the chip, which is dominant in the aspect of breakdown resistance, and the electrothermal conversion element drives the semiconductor device to have higher integration level.

It is a 2 nd object of the present invention to provide a semiconductor device, a method of manufacturing the same, and a liquid ejecting apparatus which are extremely less likely to cause defects caused by channels and have a plurality of transistors with the same performance and which can make the integration degree of the semiconductor device higher.

The semiconductor device capable of achieving the 1 st object of the present invention comprises: a plurality of electrothermal conversion elements; a plurality of conversion devices that flow an electric current through a plurality of electrothermal conversion elements, wherein: an electrothermal conversion element and a conversion device are integrated on a semiconductor substrate of a 1 st conductivity type; each of the switching devices is an insulated gate field effect transistor, and each of the switching devices includes: a 1 st semiconductor region of a 2 nd conductivity type formed on one main surface of the semiconductor substrate; a 2 nd semiconductor region of the 1 st conductivity type for providing a channel region, said 2 nd semiconductor region being adjacent to said 1 st semiconductor region; a 2 nd conductivity type source region formed on a side of an upper surface of the 2 nd semiconductor region; a drain region of the 2 nd conductivity type formed on the upper surface side of the 1 st semiconductor region; and a plurality of gate electrodes formed on the channel region with a gate insulating film interposed therebetween; and the 2 nd semiconductor region has an impurity concentration higher than that of the 1 st semiconductor region, and the 2 nd semiconductor region is located between the drain regions arranged in parallel.

Here, the 2 nd semiconductor region is preferably formed close to the semiconductor substrate.

Further, it is preferable that the source regions and the drain regions are alternately arranged in a lateral direction.

The electrothermal conversion element is preferably connected to the drain region.

The two gate electrodes are preferably formed with the source region placed therebetween.

The arrangement direction of the plurality of electrothermal conversion elements and the arrangement direction of the plurality of conversion devices are preferably parallel.

The drain regions of at least two insulated gate field effect transistors are preferably connected to one electrothermal transducer element, and the source regions of a plurality of insulated gate field effect transistors are preferably commonly connected.

The effective channel length of the insulated gate field effect transistor is preferably determined by the difference between the amount of lateral diffusion in the 2 nd semiconductor region and the source region.

Each insulated gate field effect transistor preferably includes a diffusion layer of the 1 st conductivity type for the extraction electrode, which penetrates the source region.

The gate insulating film includes a thin insulating film and a thick insulating film, and a portion of each of the gate electrodes on a side close to the drain region is formed on the thick insulating film.

A portion of each gate electrode on the side close to the drain region is preferably formed on the field insulating film.

The 1 st semiconductor region is preferably formed by introducing an impurity of opposite conductivity type from the surface of the semiconductor substrate to form a well.

The 1 st semiconductor region is preferably formed by introducing impurities of opposite conductivity types from the surface of the semiconductor substrate to form a plurality of wells, and is laterally isolated at each drain region.

The 2 nd semiconductor region preferably includes a low region and a high region, and the impurity concentration of the high region is higher than that of the low region.

The drain region is preferably provided so as to be isolated from an end portion of the gate electrode on a side close to the drain region.

The source region preferably overlaps the gate electrode.

The drain region is preferably self-aligned with an end portion of the thicker insulating film.

The 2 nd semiconductor region, the source region and the drain region preferably have left and right symmetrical cross-sectional structures formed by introducing impurities by oblique ion implantation.

The semiconductor substrate is preferably a substrate inclined with respect to the direction of the single crystal orientation thereof.

It is preferable to form the liquid discharge portion corresponding to the electrothermal conversion element.

The above object 1 can be achieved by a manufacturing method of a semiconductor device in which a plurality of electrothermal conversion elements and a plurality of conversion devices for causing current to flow through the plurality of electrothermal conversion elements are integrated on a semiconductor substrate of a 1 st conductivity type, comprising the steps of: forming a semiconductor layer of a 2 nd conductivity type on a main surface of a semiconductor substrate of a 1 st conductivity type; forming a gate insulating film on the semiconductor layer; forming a gate electrode on the gate insulating film; doping a 1 st conductive type impurity between two adjacent gate electrodes using the gate electrodes as a mask; forming a semiconductor region on the 2 nd conductive type semiconductor layer between the adjacent two gate electrodes by diffusing the 1 st conductive type impurity; and forming a source region of the 2 nd conductivity type on an upper surface side of the semiconductor region and a drain region of the 2 nd conductivity type on an upper surface side of the semiconductor layer of the 2 nd conductivity type using the gate electrode as a mask.

The above object 1 can be achieved by a manufacturing method of a semiconductor device in which a plurality of electrothermal conversion elements and a plurality of conversion devices for causing current to flow through the plurality of electrothermal conversion elements are integrated on a semiconductor substrate of a 1 st conductivity type, comprising the steps of: forming a semiconductor layer of a 2 nd conductivity type on a main surface of a semiconductor substrate of a 1 st conductivity type; selectively forming a field insulating film on the semiconductor layer; forming a gate insulating film on the semiconductor layer; forming a gate electrode on the gate insulating film and the field insulating film; doping a 1 st conductive type impurity between two adjacent gate electrodes using the gate electrodes as a mask; forming a semiconductor region on the 2 nd conductive type semiconductor layer between the adjacent two gate electrodes by diffusing the 1 st conductive type impurity; and forming a source region of the 2 nd conductivity type on the upper surface side of the semiconductor region using the gate electrode as a mask; and forming a drain region of the 2 nd conductivity type on an upper surface side of the semiconductor layer of the 2 nd conductivity type using the field insulating film as a mask.

Preferably, the method further comprises the following steps: performing ion implantation of the 1 st conductivity type to at least one channel region between the source region and the semiconductor layer placed on the surface side of the semiconductor region via the gate electrode after the step of forming the semiconductor region; and performing a heat treatment to electrically activate the implanted impurities.

Preferably also comprising the steps of: performing ion implantation of the 1 st conductivity type to at least one channel region between the source region and the semiconductor layer placed on the surface side of the semiconductor region via the gate electrode after the step of forming the semiconductor region; and performing a heat treatment to electrically activate the implanted impurity, wherein the ion implantation is performed with boron (B) ion implantation at an energy of more than less than 100 keV.

At least two drain regions of the MIS type field effect transistor as the switching device are preferably connected to one electrothermal conversion element, and sources of the plurality of MIS type field effect transistors are preferably commonly connected.

Further, the object 2 can be achieved by the above-mentioned method for manufacturing a semiconductor device, in which a transistor structure symmetrical to a source region can be formed.

Here, the doping step of the 1 st conductive type impurity preferably includes: and performing oblique ion implantation on the main surface of the semiconductor substrate while the semiconductor substrate is rotated.

The forming of the 2 nd conductive-type source region preferably includes: and performing oblique ion implantation on the main surface of the semiconductor substrate while the semiconductor substrate is rotated.

The forming of the 2 nd conductive type drain region preferably includes: and performing oblique ion implantation to the main surface of the semiconductor substrate while the semiconductor substrate is rotated.

The doping step of the impurity of the 1 st conductivity type preferably includes a step of performing ion implantation in a direction normal to the main surface of the semiconductor substrate into the main surface of the substrate as a substrate inclined with respect to a crystal orientation direction of a single crystal thereof.

The step of forming the 2 nd conductivity type source region preferably includes the step of performing ion implantation in a direction normal to the main surface of the semiconductor substrate into the main surface of the substrate which is inclined with respect to the crystal orientation direction of the single crystal thereof as the semiconductor substrate.

The step of forming the 2 nd conductivity type drain region preferably includes the step of performing ion implantation in a direction normal to the main surface of the semiconductor substrate into the main surface of the substrate which is inclined with respect to a crystal orientation direction of a single crystal thereof as the semiconductor substrate.

The doping step of the impurity of the 1 st conductivity type preferably includes a step of performing B ion implantation at a high energy of 100keV or less.

The present invention also provides a method of manufacturing a semiconductor device having a plurality of insulated gate field effect transistors arranged in a matrix type, the method comprising the steps of: forming a 1 st semiconductor region of a 2 nd conductivity type on one main surface of a 1 st conductivity type semiconductor substrate; forming a gate insulating film on the 1 st semiconductor region; forming a plurality of gate electrodes on the gate insulating film; implanting an impurity of the 1 st conductivity type between two adjacent gate electrodes at a fixed angle to a normal direction of the semiconductor substrate with the two adjacent gate electrodes as a mask while the semiconductor substrate is rotated, and thereafter diffusing the impurity to form a 2 nd semiconductor region of the 1 st conductivity type; and performing ion implantation of impurities at a fixed angle to a normal direction of the semiconductor substrate with the semiconductor substrate rotated, forming a 2 nd conductivity type source region in the 2 nd semiconductor region with the two gate electrodes as masks, and forming 2 nd conductivity type drain regions in the two 1 st semiconductor regions with the 2 nd semiconductor region placed therebetween, respectively.

In another semiconductor device manufacturing method according to the present invention, the semiconductor device has a plurality of insulated gate field effect transistors arranged in a matrix type, the method comprising the steps of: forming a 1 st semiconductor region of a 2 nd conductivity type on one main surface of a 1 st conductivity type semiconductor substrate; selectively forming a field insulating film on the 1 st semiconductor region; forming a gate insulating film on the 1 st semiconductor region; forming a gate electrode on the gate insulating film and the field insulating film; implanting an impurity of the 1 st conductivity type between the two gate electrodes at a fixed angle to a normal direction of the semiconductor substrate with the two gate electrodes as masks while the semiconductor substrate is rotated, and thereafter forming a 2 nd semiconductor region of the 1 st conductivity type by diffusing the impurity; and performing impurity implantation at a fixed angle to a normal direction of the semiconductor substrate with the semiconductor substrate rotated, forming a 2 nd conductivity type source region in the 2 nd semiconductor region with the two gate electrodes as masks, and forming 2 nd conductivity type drain regions in the 1 st semiconductor region with the 2 nd semiconductor region interposed therebetween, respectively, with the field insulating film as a mask.

Here, the 2 nd semiconductor region is preferably formed deeper than the 1 st semiconductor region.

It is preferable to form a heat-resistant element electrically connected to the drain region.

The invention also provides a manufacturing method of the semiconductor device. The method comprises the following steps: forming a 1 st semiconductor region of a 2 nd conductivity type on one main surface of a 1 st conductivity type semiconductor substrate; selectively forming a field insulating film on the 1 st semiconductor region; forming a gate insulating film on the 1 st semiconductor region; forming a gate electrode on the gate insulating film and the field insulating film; implanting an impurity of the 1 st conductivity type between the two gate electrodes at a fixed angle to a normal direction of the semiconductor substrate with the two gate electrodes as masks while the semiconductor substrate is rotated, and thereafter forming a 2 nd semiconductor region of the 1 st conductivity type by diffusing the impurity; and performing impurity implantation at a fixed angle to a normal direction of the semiconductor substrate with the semiconductor substrate rotated, forming a 2 nd conductivity type source region in the 2 nd semiconductor region with the two gate electrodes as masks, and forming 2 nd conductivity type drain regions in the 1 st semiconductor region with the 2 nd semiconductor region interposed therebetween, respectively, with the field insulating film as a mask.

The present invention provides a method for manufacturing a semiconductor device, the method comprising the steps of: forming a 1 st semiconductor region of a 2 nd conductivity type on a 1 st conductivity type semiconductor substrate including one main surface having a crystal plane orientation inclined with respect to a low-dimensional crystal plane direction; selectively forming a field insulating film in the 1 st semiconductor region; forming a gate insulating film in the 1 st semiconductor region; forming a gate electrode on the gate insulating film and the field insulating film; forming a 2 nd semiconductor region by diffusing an impurity of the 1 st conductivity type after ion implantation of the impurity in a vertical direction into the semiconductor substrate with the gate electrode as a mask; and performing impurity ion implantation perpendicularly to the semiconductor substrate, respectively, to form a source region of the 2 nd conductivity type in the 2 nd semiconductor region using the gate electrode as a mask, and to form a drain region of the 2 nd conductivity type in the 2 nd semiconductor region of the 2 nd conductivity type using the field insulating film as a mask.

Here, the crystal plane orientation of the main surface of the semiconductor substrate is preferably inclined toward the lower dimensional crystal direction by an angle ranging from 3 degrees to 10 degrees.

Further, the crystal plane orientation of the main surface of the semiconductor substrate is preferably inclined at an angle ranging from 3 degrees to 10 degrees with respect to the (100) crystal plane.

The crystal plane orientation of the main surface of the semiconductor substrate is preferably inclined at an angle of 4 degrees with respect to the (100) crystal plane.

The step of forming the 2 nd semiconductor region is preferably to perform diffusion of the 1 st conductivity type impurity so that the impurity is deeper than the 1 st semiconductor region.

A plurality of insulated gate field effect transistors are arranged in a matrix shape.

In a semiconductor device according to the present invention, a plurality of insulated gate field effect transistors are provided in a matrix type, the plurality of insulated gate field effect transistors respectively including: a 1 st semiconductor region of a 2 nd conductivity type formed on a 1 st conductivity type semiconductor substrate including one main surface having a crystal plane orientation inclined with respect to a low-dimensional crystal plane direction; a 2 nd semiconductor region of the 1 st conductivity type is formed to partition the 1 st semiconductor region, the 2 nd semiconductor region having an impurity concentration higher than that of the 1 st semiconductor region; a source region of a 2 nd conductivity type formed in the 2 nd semiconductor region; and a drain region of a 2 nd conductivity type formed in the 1 st semiconductor region.

Here, the crystal plane orientation of the main surface of the semiconductor substrate is preferably inclined at an angle ranging from 3 degrees to 10 degrees with respect to the low-dimensional crystal plane orientation.

Further, the plane direction of the main surface of the semiconductor substrate is preferably inclined at an angle ranging from 3 degrees to 10 degrees with respect to the (100) crystal plane.

Further, the plane direction of the main surface of the semiconductor substrate is preferably inclined at an angle of 4 degrees with respect to the (100) crystal plane.

The depth of the 2 nd semiconductor region is preferably deeper than the depth of the 1 st semiconductor layer.

The liquid spraying apparatus according to the present invention comprises: the above-described semiconductor device, which includes the liquid discharge portion corresponding to the electrothermal conversion element, and the liquid container for containing the liquid ejected from the liquid discharge portion by the electrothermal conversion element; and a controller for supplying a drive control signal for driving the insulated gate field effect transistor in the semiconductor device.

According to the present invention, since the concentration of the drain region can be set lower than that of the channel, a sufficiently deep drain can be formed, so that the semiconductor device has a high breakdown voltage which allows a large current to flow therethrough, and the semiconductor device has a low resistance value and can be operated at a higher speed, and the semiconductor device can realize a high integration level and save power consumption. Then, according to the structure of the present invention, even in the case where a semiconductor device is required to have a matrix structure with a plurality of transistors, electrical insulation between the devices does not increase the production cost.

Further, according to the present invention, a transistor matrix having uniform characteristics and high integration can be manufactured. Particularly when a double diffused MOSFET (DMOS transistor) is used as the switching device, it is possible to suppress a leakage current flowing from a drain to a substrate, and suppress the electric field intensity. Therefore, the breakdown voltage can be improved.

Drawings

The above objects, other objects, features and advantages of the present invention will become more apparent from the following description of preferred embodiments of the present invention taken in conjunction with the accompanying drawings. Wherein,

fig. 1 is a schematic plan view of a semiconductor device according to embodiment 1 of the present invention;

fig. 2 is a schematic cross-sectional view of a semiconductor device according to embodiment 1 of the present invention;

fig. 3 is a schematic circuit diagram of a semiconductor device according to the present invention;

fig. 4 is a circuit diagram of a semiconductor device according to the present invention;

fig. 5 is a schematic plan view of a semiconductor device according to embodiment 2 of the present invention;

fig. 6A to 6F are schematic cross-sectional views illustrating a semiconductor device manufacturing process according to embodiment 2 of the present invention;

fig. 7 is a schematic cross-sectional view illustrating a semiconductor device manufacturing process according to embodiment 3 of the present invention;

fig. 8A to 8G are schematic cross-sectional views of a semiconductor device manufacturing process according to embodiment 4 of the present invention;

fig. 9 is a schematic cross-sectional view of a semiconductor device manufacturing process according to embodiment 5 of the present invention;

FIG. 10 is a schematic sectional view showing an example of a recording head structure according to the present invention;

fig. 11 is a schematic plan view of a semiconductor device;

fig. 12 is a schematic cross-sectional view of the semiconductor device;

fig. 13 is a schematic plan view of yet another semiconductor device;

fig. 14 is a schematic cross-sectional view of the semiconductor device;

fig. 15 is a schematic plan view of a semiconductor device according to embodiment 7 of the present invention;

FIG. 16 is a cross-sectional view taken along line 16-16 of FIG. 15;

fig. 17 is a schematic view of a semiconductor device of the present invention;

fig. 18A to 18F are schematic cross-sectional views of a semiconductor device manufacturing process according to embodiment 8 of the present invention;

fig. 19 is a schematic cross-sectional view of a manufacturing process of a semiconductor device according to embodiment 9 of the present invention;

fig. 20A to 20G are schematic sectional views of a manufacturing process of a semiconductor device according to embodiment 10 of the present invention;

fig. 21 is a schematic cross-sectional view of a semiconductor device manufacturing process according to embodiment 11 of the present invention;

FIG. 22 is a schematic sectional view showing a part of a liquid ejecting head according to the present invention;

fig. 23 is a sectional structural view of the semiconductor device;

fig. 24A is a schematic plan view showing a layout example of a semiconductor device to a main surface of a semiconductor substrate;

FIG. 24B shows a schematic view of the surface ion implantation angle of the semiconductor substrate;

fig. 25A is a schematic plan view of another layout example of semiconductor devices to a main surface of a semiconductor substrate;

fig. 25B is a schematic view showing a surface ion implantation angle of a semiconductor substrate;

fig. 26 is a sectional structural view of a semiconductor device;

fig. 27 is a schematic cross-sectional view of a semiconductor device in accordance with the present invention;

fig. 28 shows a schematic view of an ion implantation method of a semiconductor device according to the present invention;

fig. 29A is a schematic plan view of a semiconductor device according to the present invention;

FIG. 29B is a schematic cross-sectional view taken along line 29B-29B in FIG. 29A;

fig. 30A to 30E are schematic cross-sectional views of a semiconductor device according to an embodiment of the present invention;

fig. 31A to 31F are schematic cross-sectional views of a semiconductor device according to an embodiment of the present invention;

fig. 32 is a schematic view showing a plane direction of a main surface of a semiconductor substrate according to the present invention;

fig. 33 is a schematic cross-sectional view of a semiconductor device in accordance with the present invention;

fig. 34 is a circuit block diagram of a semiconductor device according to the present invention;

FIG. 35 is a schematic view showing a liquid jet head structure of the present invention;

FIG. 36 is a schematic perspective view showing the outer shape of a liquid ejecting head according to the present invention;

FIG. 37 is a schematic view showing a liquid ejecting apparatus according to the present invention;

fig. 38 is a schematic sectional view of a conventional liquid ejecting head;

Detailed Description

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[ example 1]

First, referring to fig. 1 to 4, a semiconductor device used for the liquid ejection apparatus according to embodiment 1 of the present invention is explained in detail.

Reference numeral 1 denotes a P-type semiconductor substrate; reference numeral 2 denotes an N-type well region (1 st semiconductor region); reference numeral 4 denotes a gate electrode; reference numeral 6 denotes a P-type base region (2 nd semiconductor region); reference numeral 7 denotes an N-type source region;

reference numerals

8 and 9 denote N-type drain regions, respectively; reference numeral 10 denotes a diffusion layer for extracting a base electrode; reference numeral 11 designates a contact point; reference numeral 12 denotes a source electrode; reference numeral 13 denotes a drain electrode; further, reference numeral 30 denotes an insulated gate Field Effect Transistor (FET); reference symbols Tr1, Tr2, and Tr3 respectively denote switching devices formed of insulated gate field effect transistors;

reference numerals

31, 32, and 33 respectively refer to electrothermal conversion elements as loads.

The electrothermal conversion elements 31 to 33 are integrated on the main surface with a thin film process. Similarly, the switching devices Tr1 to Tr3 are provided on the surface of the semiconductor substrate 1. By making the arrangement directions of the electrothermal conversion elements 31 to 33 and the conversion devices Tr1 to Tr3 parallel to each other as needed, the degree of integration of the semiconductor device can be further improved. In this case, it is preferable to provide the switching devices Tr1 to Tr3 in the manner shown in fig. 1 to 3. In the configuration used here, all the transistors of the switching devices Tr1 to Tr3 connected to the electrothermal conversion elements 31 to 33 have the same structure, and no isolation region is required between the transistors in the transistor matrix.

The two gate electrodes 4 and the two source regions 7 between which the

drain region

8 or 9 is arranged as described above form a segment. In these elements, the source region 7 is shared by adjacent segments.

In the example shown in fig. 3, the

drain regions

8 and 9 of the two segments are connected to one side terminal of each

electrothermal conversion element

31, 32, and 33, and the common source region 7 is connected to a low reference voltage source supplying a lower reference voltage, for example, 0 v. The other side terminal of each of the

electrothermal conversion elements

31, 32 and 33 is connected to a high reference voltage source which supplies a high reference voltage VDD, for example, from +10V to + 30V.

The operation of the semiconductor device is summarized below. A reference voltage, for example, a ground potential, is applied to the P-type semiconductor substrate 1 and the source region 7. After that, the reference voltage VDD is increased to one side terminals of the electrothermal conversion elements 31 to 33. When a current flows only through, for example, the electrothermal conversion elements 31 among them by turning on only the switches 34, the gate voltage VG is applied to the gate electrodes 4 of the transistors constituting the two segments of the conversion device Tr1, turning on the conversion device Tr 1. Then, a current flows from the power supply terminal to the ground terminal through the electrothermal conversion element 31 and the conversion device Tr1, generating heat in the electrothermal conversion element 31. Thereafter, the generated spray liquid is used, as is well known.

In this embodiment, as shown in fig. 1, a deep base region 6 is formed to divide a previously formed well into well regions 2 from the lateral direction. The well region 2 and the base region 6 in the transistor 30 constitute the drain and channel, respectively, of the transistor 30. Therefore, in contrast to the case where the drain region is formed after the channel semiconductor region of a conventional metal-oxide-semiconductor (MOS) transistor is formed, since the channel is formed after the drain formation, the impurity atom concentration of the drain region (donor impurity concentration in the 1 st semiconductor region) can be set smaller than the impurity atom concentration in the channel (acceptor impurity concentration in the 2 nd semiconductor region). The breakdown voltage of the transistor is determined by the breakdown voltage of the drain, which normally becomes higher as the impurity concentration of the drain region decreases or the depth of the drain becomes deeper. Therefore, in this embodiment, the rated voltage of the semiconductor device can be set higher, the current can be increased, and thus high-speed operation of the device can be realized.

Furthermore, the effective channel length of the transistor 30 according to the present embodiment is determined by the difference in the amount of lateral diffusion in the base region 6 and the source region 7. Since the amount of lateral diffusion is determined based on the physical coefficient, the effective channel length can be set shorter than that of the conventional transistor. Therefore, the on-resistance of the transistor 30 can be reduced. The reduction of the on-resistance increases the amount of current flowing per unit size, thereby enabling high-speed operation, saving energy, and improving integration.

Furthermore, a source region 7 is provided between the two gate electrodes 4, and both the base region 6 and the source region 7 can be formed in a self-aligned manner using the gate electrode 4 as a mask. Therefore, a difference in size of the base region 6 and the source region 7 caused by self-alignment does not occur, the transistor 30 can be constructed without any dispersion in threshold value thereof, and high productivity can be realized and high reliability can be obtained.

In order to completely separate the well region 2, the bottom of the base region 6 is formed to have a sufficient depth to be in contact with the grounded P-type semiconductor substrate 1, so that the base region 6 reaches the substrate 1. Due to this structure, each drain of each segment can be electrically isolated independently.

Therefore, even when the plurality of source and

drain regions

7 and 8 and 9 are laterally arranged without any dedicated isolation region, the operation of each of the switching devices Tr1, Tr2, and Tr3 is not hindered.

Moreover, since the diffusion layer 10 that draws out the base electrode is formed so as to penetrate the source region 7, the base region 6 can be held at a predetermined potential without increasing the area occupied by the base region 6.

Fig. 3 and 4 show an example of a structure in which two drains of two segments of a transistor are connected to one load that can be driven separately. When an on signal for driving a load is supplied to a gate of the transistor, the transistor is in an on state. Current then flows from one drain to the common source adjacent to both sides of the drain. As described above, the sources located at the boundaries of adjacent segments may be common.

Therefore, in the case where the transistors of the present embodiment are arranged in a matrix form and used as a liquid ejecting apparatus, it is not necessary to form an isolation region made of a special semiconductor between the respective transistors to separate the P-N junctions, and it is also not necessary to form a local oxidation of silicon (LOCOS) region, a medium for separating channels, and the like, and moreover, a semiconductor device capable of flowing a large current and high integration can be made, and the production cost can be reduced. In addition, a leakage current flowing from the drain through the substrate 1 can be sufficiently suppressed.

[ example 2]

The basic structure of the semiconductor device for a liquid ejection apparatus according to embodiment 2 of the present invention is the same as that of the semiconductor device described in embodiment 1 above. The main difference between them is the location of the drain region 8 and the process of forming it.

Fig. 5 shows a planar structure of a semiconductor device for a liquid ejection apparatus according to embodiment 2 of the present invention, and fig. 6A to 6F show sectional views thereof.

The manufacturing method of the semiconductor device is roughly such a method that: a plurality of electrothermal conversion elements and a plurality of conversion devices that cause electric current to flow through the plurality of electrothermal conversion elements are integrated on a semiconductor substrate of the 1 st conductivity type. The method comprises the following steps: forming a semiconductor layer 2 of the 2 nd conductivity type on the main surface of the semiconductor substrate 1 of the 1 st conductivity type, see fig. 6A; forming a gate insulating film 203 on the semiconductor layer; forming a gate electrode 4 on the gate insulating film 203, see fig. 6B; doping the 1 st conductive type impurity using the gate electrode 4 as a mask, see fig. 6C; diffusing the 1 st conductive type impurity to a diffusion depth deeper than the 2 nd conductive type semiconductor layer, thereby forming a semiconductor region, see fig. 6D; a source region 7 of the 2 nd conductivity type is formed on the surface side of the semiconductor region with the gate electrode 4 as a mask, and

drain regions

8 and 9 of the 2 nd conductivity type are formed on the surface side of the 2 nd conductivity type semiconductor layer, see fig. 6E.

The production method will be described in detail below.

First, as shown in fig. 6A, a P-type semiconductor substrate 1 is prepared. An N-type impurity is selectively introduced into a region to be a well on the surface of a P-type semiconductor substrate 1 to form an N-type well region 2. The N-type well region 2 can be formed on the entire surface of the P-type semiconductor substrate 1. Further, when the N-type well region 2 is formed on the entire surface of the P-type semiconductor substrate 1, an epitaxial growth method may be used.

Thereafter, as shown in fig. 6B, a gate insulating film (gate oxide film) 203 having a thickness of 50nm is grown on the N-type well region 2 by, for example, a thermal oxidation method, and polysilicon having a film thickness of 300nm is deposited on the gate insulating film 203 by, for example, a Low Pressure Chemical Vapor Deposition (LPCVD) method. Polysilicon having a desired wiring resistance value is produced by doping phosphorus at the same time as deposition by an LPCVD method, by doping phosphorus by an ion implantation method, or by doping phosphorus by a solid diffusion method after deposition, for example. Thereafter, the polysilicon film is patterned by photolithography, and the polysilicon film is etched. This enables the gate electrode 4 of the MIS type field effect transistor to be formed.

Next, as shown in fig. 6C, a photoresist mask for ion implantation (not shown) is formed by the photolithography patterning property, and the gate electrode 4 is also used as a mask. Thereafter, ion implantation of a P-type impurity such as boron is performed to form the impurity layer 205.

Next, as shown in fig. 6D, a base region 6 having a depth of 2.2 μm and electrically isolated from the well region 2 in a lateral direction was formed by heat treatment at 1100 ℃ for 60 minutes in an electric furnace. In this embodiment, it is important to design that the base region 6 is deeper than the well region 2 through the heat treatment for the complete isolation of the well region 2, and the conditions of the heat treatment are determined according to the depth of the well region 2, the impurity concentration, the impurity type, and the impurity concentration and the type of the impurity layer 205. The depth of the base region 6 used in the present invention is selected in a range of, for example, about from 1 μm to 3 μm, and the impurity concentration at the outermost surface of the base region 6 may be selected in a range of, for example, about from 1 × 10¹⁵/cm³To 1X 10¹⁹/cm³。

Thereafter, as shown in fig. 6E, for example, arsenic ion implantation is performed using the gate electrode 4 as a mask to form a source region 7, a 1 st drain region 8, and a 2 nd drain region 9. Thus, the source region 7 and the

drain regions

8 and 9 are self-aligned with each other with the gate electrode 4 to form a small overlap.

As shown in fig. 6F, a photoresist mask (not shown) is formed by patterning by photolithography, and the diffusion layer 10 for extracting the base electrode is formed by, for example, ion implantation. Although the diffusion layer for extracting the base electrode is not always necessary, it is preferable to form the diffusion layer 10 on the circuit design. Moreover, when the P-type MIS type field effect transistor is configured at the same time as the signal processing, no process is added to form the diffusion layer 10. Thereafter, heat treatment is performed at 950 ℃ for, for example, 30 minutes, thereby activating the 1 st drain region 8, the 2 nd drain region 9, and the diffusion layer 10 from which the base electrode is extracted.

Thereafter, although not shown, an oxide film is deposited by Chemical Vapor Deposition (CVD) to form an interlayer insulating film. Then, contact holes serving as contacts 11 are opened, and an insulating material is deposited, see fig. 1. Thereafter, patterning is performed to form a wiring. After that, a multilayer wiring is performed as necessary, and thus, an integrated circuit is manufactured.

Electrothermal conversion elements, which are integrated on the substrate 1, are fabricated by a wiring process known as a thin film process. The circuit configuration in this case is the same as that in the foregoing embodiment.

Since the base region 6, the source region 7 and the

drain regions

8 and 9 are formed by ion implantation using the gate electrode 4 as a mask, and these

regions

6, 7 and 8 are formed by being adjusted with respect to the gate electrode 4, a high integration of the switching device matrix can be obtained and a uniform performance of each device can be achieved. Further, since the source region 7 and the

drain regions

8 and 9 are formed in the same process, the present embodiment can reduce the production cost.

[ example 3]

When it is required to further increase the breakdown voltage of the drain region, it is preferable to form the end portions of the

drain regions

8 and 9 apart from the end portion of the gate electrode 4, as shown in fig. 1 and 2. In particular, the number of photolithography steps is not increased when the semiconductor device is formed by the following method.

Fig. 7 is a sectional view of a semiconductor device manufacturing method according to embodiment 3 of the present invention. The following describes the manufacturing method after having undergone the process shown in fig. 6A to 6D.

As shown in fig. 7, a photoresist mask 211 is formed using photolithographic patterning. Thereafter, ion implantation is performed using, for example, arsenic using the photoresist mask 211 and the gate electrode 4 as masks, and the source region 7, the 1 st drain region 8, and the 2 nd drain region 9 are formed. At this time, it is important to form a photoresist mask so that the 1 st drain region 8 and the 2 nd drain region 9 are offset from the gate electrode 4. Thereby, the distance between each drain region and each source region is sufficiently maintained. Further, since there is no high concentration diffusion layer directly under each gate, a breakdown voltage drop due to electric field concentration can be prevented.

Thereafter, after the process shown in FIG. 6F, an integrated circuit provided with electrothermal conversion elements similar to example 2 was produced.

[ example 4]

A method for manufacturing a semiconductor device according to embodiment 4 of the present invention is explained with reference to fig. 8A to 8G.

The present embodiment is characterized in that the drain edge of the gate electrode 4 is formed on an insulating film thicker than the gate insulating film 203.

The semiconductor device manufacturing method manufactures a semiconductor device in which a plurality of electrothermal conversion elements are integrated on a semiconductor substrate of the 1 st conductivity type, and a conversion device that causes an electric current to flow through the plurality of electrothermal conversion elements. The method comprises the following process steps: forming a semiconductor layer of 2 nd conductivity type on the main surface of semiconductor substrate 1 of 1 st conductivity type, see fig. 8A; selectively forming a field insulating film 221 on the semiconductor layer, see fig. 8B; forming a gate insulating film 203 on the semiconductor layer, see fig. 8B; forming a gate electrode 4 on the gate insulating film 203 and the field insulating film 221, see fig. 8C; doping the 1 st conductive type impurity using the gate electrode 4 as a mask, see fig. 8D; diffusing the 1 st conductive type impurity deeper than the 2 nd conductive type semiconductor layer to form a semiconductor region, see fig. 8E; a 2 nd conductivity type source region 7 is formed on the surface side of the semiconductor region with the gate electrode 4 as a mask, and 2 nd conductivity

type drain regions

8 and 9 are formed on the surface side of the 2 nd conductivity type semiconductor layer with the field insulating film 221 as a mask, see fig. 8F. The method is described in detail below.

First, as shown in fig. 8A, an N-type well region 2 is formed on the surface of a P-type semiconductor substrate 1.

Next, a pad oxide film (not shown) having a thickness of 10nm is grown on the surface of the well region 2 by, for example, a thermal oxidation method, and a silicon nitride film (not shown) having a thickness of 150nm is deposited on the pad oxide film by, for example, an LPCVD method. Then, the silicon nitride film is patterned by photolithography etching. Then, the field insulating film 221 is selectively grown to a thickness of 500nm by, for example, a thermal oxidation method. Thereafter, the silicon oxide film is completely removed with, for example, phosphoric acid, and the pad oxide film is removed with, for example, a 10 wt% hydrofluoric acid solution. A gate insulating film 203 having a thickness of 10nm is grown on the N-type well region 2 by, for example, a thermal oxidation method. At this time, although the pad oxide film can be used as the gate insulating film 203, it is preferable to be not used because of its reliability. Therefore, as shown in fig. 8B, a gate insulating film 203 serving as a thin oxide film and a field insulating film (field oxide film) 221 serving as a thick oxide film are provided at predetermined positions of the N-type well region 2.

Next, as shown in fig. 8C, polysilicon having a thickness of about 300nm is deposited on the gate insulating film 203 and the field insulating film 221 by, for example, LPCVD. The polysilicon having a desired wiring resistance value is formed by doping phosphorus while depositing by, for example, an LPCVD method, or doping phosphorus after deposition, or ion implantation using phosphorus, or solid diffusion. Thereafter, the polysilicon film is patterned by photolithography so that one end of the film is terminated on the gate insulating film 203 and the other end is terminated on the field insulating film 221; and etching the polysilicon film. Thus, the gate electrode 4 of the MIS type field effect transistor can be formed.

Next, as shown in fig. 8D, an impurity layer 205 is formed by selective ion implantation of, for example, a P-type impurity of boron by photolithography patterning using the gate electrode 4 as a mask.

Thereafter, as shown in fig. 8E, the base region 6 of the lateral electrically isolated well region 2 is formed by performing a heat treatment at, for example, 1100 ℃ for 60 minutes using an electric furnace. In this embodiment, it is important to design the heat treatment so that the base region 6 becomes deeper than the well region 2 to completely separate the well region 2 in the longitudinal direction by the base region 6, and it is required to design the heat treatment so that the base region 6 is located in the vicinity of the boundary between the gate insulating film 203 and the field insulating film 221 in the lateral direction.

The reason for this is that if the base region 6 is formed only half the distance from the gate insulating film 203, an electric field generated under the gate electrode 4 may concentrate on the thin gate insulating film 203, damaging the gate insulating film 203. Further, if the base region 6 is formed up to the thick field insulating film 221, the base region 6 under the thick field insulating film 221 is not inverted even if a predetermined voltage is applied to the gate electrode 4, and the base region 6 does not function as a switching function of the MIS type field effect transistor. Therefore, even if the switching device is turned on, its drivability is greatly deteriorated.

Thus, the heat treatment conditions are determined by the depth, concentration, impurity species of the well region 2, and impurity concentration, impurity species, and mask size of the impurity layer 205.

Thereafter, as shown in fig. 8F, ion implantation is performed with, for example, arsenic, and the source region 7, the 1 st drain region 8, and the 2 nd drain region 9 are formed. At this time, the gate electrode 4 functions as a mask to align the end of the source electrode 7; the field insulating film 221 functions as a mask to align the end portions of the

drain regions

8 and 9. Thus, the source region is self-regulated with the gate electrode 4, and the

drain regions

8 and 9 are self-regulated with the field insulating film 221.

Thereafter, as shown in fig. 8G, the diffusion layer 10 extracting the base electrode 4 is formed by, for example, ion implantation by photolithography patterning. Although the diffusion layer 10 leading out the base electrode 4 is not always necessary, it is preferable to form the diffusion layer 10 on the circuit design. Further, when the P-type MIS type field effect transistor is configured while the signal processing circuit is manufactured, the diffusion layer 10 is formed without adding any process. Thereafter, the source region 7, the 1 st drain region 8, the 2 nd drain region 9 and the diffusion layer 10 for extracting the base 4 are activated by heat treatment at 950 ℃ for 30 minutes, for example. Accordingly, an insulator is formed with the field insulating film 221 which is a field oxide film on the drain side where the electric field is concentrated under the gate electrode 4, thereby improving the breakdown voltage between the gate and the drain of the MIS type field effect transistor. For example, in the case where it is also required to simultaneously form a complementary MIS type field effect transistor that requires high-speed operation on the same substrate, an insulator may be formed with the field insulating film 221 in the insulating region forming process of the complementary MIS type field effect transistor. Therefore, a very effective insulator can be formed without any additional process.

Thereafter, although not shown, an interlayer insulating film is formed by depositing an oxide film by a CVD method. Then, contact holes serving as contacts 11 (see fig. 1) are opened, and wirings are formed. Multilayer wiring is performed as needed, thereby manufacturing an integrated circuit. The electrothermal conversion elements are formed by a wiring forming process using a known thin film process, and the elements are integrated on the substrate 1. The circuit configuration in this case is the same as that in the above-described embodiment.

[ example 5]

Fig. 9 shows a method for manufacturing a semiconductor device according to embodiment 5 of the present invention. Here, a manufacturing method after the process shown in fig. 6A to 6D of embodiment 3 has been performed will be described.

As shown in fig. 9, a photoresist mask 211 is formed by photolithography patterning, and then, ion implantation is performed using the photoresist mask 211 as a mask with, for example, boron at an acceleration energy of 100keV or more, for example, 120keV, to form a channel doping layer 232. In this case, it is important to form the channel doping layer 232 at least in the source region 7 on the base region 6 (actually, the source region 7 is not formed in the present process, but is formed in the next process or a later process and in a portion of the channel 233 between the two well regions 2.

Although the photoresist mask 211 is not always required, performing ion implantation on the entire surface is not problematic. However, when the concentration of the well region 2 is extremely low, the photoresist mask 211 is preferably used. Furthermore, the formation of the channel dope layer 232 is not necessarily performed in the present process. The formation of the channel dope layer 232 may be performed in the process from the formation of the base region 6 to the final activation annealing. Thus, the channel 233 can be designed to have a desired concentration, and a threshold required for the MIS field effect transistor can be controlled.

Thereafter, the same process as that after fig. 6E is performed, and an integrated circuit provided with a similar electrothermal conversion element is manufactured.

[ example 6]

Fig. 10 is a sectional view showing a partial structural example of a recording head including a semiconductor device manufactured by the manufacturing method of one embodiment of the present invention shown in fig. 1 to 9 in a liquid ejecting apparatus such as an ink jet recording head. Here, reference numeral 1 denotes a P-type semiconductor substrate made of single crystal silicon. Reference numeral 2 denotes an N-type well region; reference numeral 4 denotes a gate electrode; reference numeral 6 denotes a P-type base region, and reference numeral 7 denotes an N-type source region; reference numeral 8 denotes an N-type drain region. Fig. 10 schematically shows elements constituting the MIS type field effect transistor 30. As described above. Preferably, no dedicated isolation regions are provided between each transistor (or each segment) arranged in the array.

Further, reference numeral 817 denotes an insulating layer such as silicon oxide, which functions as a heat storage layer and an insulating layer; reference numeral 818 denotes a heat-resistant layer made of tantalum nitride, tantalum silicon nitride, or the like; reference numeral 819 denotes a wiring such as an aluminum alloy or the like; reference numeral 820 refers to a protective layer such as silicon nitride. These elements constitute a substrate 940 of the recording head. Here, reference numeral 850 denotes a heating section, and reference numeral 860 denotes an ink ejecting section. Further, the top plate 870 and the substrate 940 constitute a liquid channel 880 in combination.

The operation of each of the above embodiments of the present invention will now be described.

Fig. 11 and 12 are a plan view and a sectional view, respectively, of an MIS type field effect transistor array. By the individual operation of one of the plurality of MIS type field effect transistors formed on the semiconductor substrate 1, or by the collective operation of the plurality of MIS type field effect transistors therein, it is possible to keep the electric isolation between the electrothermal conversion elements connected in matrix. Here, reference numeral 4 denotes a gate electrode; reference numeral 7 denotes an N-type source region; reference numeral 8 denotes an N-type drain region; reference numeral 9 denotes another N-type drain region; reference numeral 11 designates a contact point; reference numeral 12 denotes a source electrode; reference numeral 13 denotes a drain electrode; reference numeral 15 designates an N-type field-attenuating drain region.

However, when the conventional MIS type field effect transistor array is driven at a large current necessary for driving the electrothermal transducer elements, the P-N reverse bias junction portion between the drain and the well (here, between the drain and the semiconductor substrate 1) cannot withstand a high electric field to generate a leakage current. Therefore, the conventional MIS type field effect transistor array cannot satisfy the requirement of the electrothermal conversion element driving semiconductor device with respect to the breakdown voltage. Further, when the on-resistance of the MIS type field effect transistor is large, since the MIS type field effect transistor is used in a state where a large current flows, a current is consumed uselessly by the on-resistance, and thus a current necessary for the operation of the electrothermal conversion element cannot be obtained.

Further, in order to increase the breakdown voltage, an array of MIS type field effect transistors shown in a plan view of fig. 13 and a cross-sectional view of fig. 14 may be considered. Here, reference numeral 1 denotes a P-type semiconductor substrate, reference numeral 2 denotes an N-type well region, reference numeral 4 denotes a gate electrode, and reference numeral 6 denotes a P-type base region; reference numeral 7 denotes an N-type source region; reference numeral 8 denotes an N-type drain region; reference numeral 9 denotes another N-type drain region; reference numeral 10 denotes a diffusion layer leading out the base electrode; reference numeral 11 denotes a contact, reference numeral 12 denotes a source electrode, and reference numeral 13 denotes a drain electrode.

The structure of the MIS type field effect transistor is different from that of a commonly used one. In this structure, a channel is formed in the drain so that the drain, which determines the breakdown voltage of the transistor, is made deeper and low in concentration. Thereby increasing its breakdown voltage.

However, when the MIS type field effect transistors are arranged in a matrix, the drain of each transistor is formed by only one common semiconductor layer, and all the drain potentials are the same common potential. Thus, if the drain is not used to form a special isolation region isolation between the conversion devices to be individually converted, respectively, the electrical isolation between the electrothermal conversion elements cannot be ensured. Moreover, in an attempt to re-form these isolation regions, the manufacturing process of the semiconductor device becomes complicated and the production cost rises. In addition, the area for forming the device becomes larger. Therefore, the MIS type field effect transistor structure shown in fig. 13 and 14 is not suitable for a transistor array for a liquid ejection apparatus.

On the other hand, according to the semiconductor devices of the above-described embodiments, their drain concentration can be set lower than their channel concentration, and their drains can be formed deep enough. Thus, these semiconductor devices can have a high breakdown voltage and can flow a large current. Also, they can operate at high speed due to their low on-resistance values, can achieve high integration, and save energy. Further, in a semiconductor device requiring a matrix-shaped structure of a plurality of transistors, the semiconductor device of each of the above-described embodiments allows each device to be easily isolated.

In fact, when the MIS type field effect transistor having substantially the same single device characteristics (the structure shown in fig. 13 and 14) as the semiconductor device of the present invention is designed with the same number of masks under the same design principle to have an isolation region maintaining electrical isolation, the MIS type field effect transistor of the technique shown in fig. 13 and 14 requires a length of 12.0 μm in the matrix arrangement direction to form its transistor section. On the contrary, a length of 6.0 μm in the matrix arrangement direction, that is, a half of the length of the segment shown in FIGS. 13 and 14, can constitute a segment of the MIS type field effect transistor of the structure of the present invention shown in FIGS. 1 and 2. The trend is that the finer the design principle described above becomes, the larger the length ratio becomes.

[ example 7]

A semiconductor device according to embodiment 7 of the present invention includes a transistor matrix formed of a plurality of insulated gate field effect transistors, wherein each transistor includes: a 1 st semiconductor region of a 2 nd conductivity type formed on a main surface of a 1 st conductivity type semiconductor substrate 1; a 2 nd semiconductor region of the 1 st conductivity type for separating the 1 st semiconductor region; a 3 rd semiconductor region of the 1 st conductivity type contained in the 2 nd semiconductor region, an impurity atom concentration of which is higher than that of the 2 nd semiconductor region; a source region 7 of the 2 nd conductivity type formed on a surface of the 3 rd semiconductor region; and a drain region 8 of the 2 nd conductivity type formed on a surface of the 1 st semiconductor region.

In the foregoing semiconductor device and method of manufacturing the same, the concentration of the drain region thereof may be set lower than the impurity concentration of the channel thereof. The drain can be formed deep enough. Thus, the semiconductor device has a high breakdown voltage and can flow a large current. Furthermore, the semiconductor device has a low on-resistance, enabling it to operate at high speed. Moreover, high integration and low power consumption can be achieved. Further, by forming a P-type well region with a low concentration around the source region 7, isolation between devices can be ensured even in a semiconductor device in which a matrix structure of a plurality of semiconductor devices is required.

Fig. 15 is a schematic plan view of a semiconductor device according to embodiment 7 of the present invention; fig. 16 is a cross-sectional view taken along line 16-16 of fig. 15.

In fig. 15 and 16, reference numeral 1 denotes a P-type semiconductor substrate; reference numeral 22 denotes an N-type well region (1 st semiconductor region); reference numeral 29 denotes a P-type well region (2 nd semiconductor region); reference numeral 4 denotes a gate; reference numeral 26 denotes a P-type base region (3 rd semiconductor region); reference numeral 7 denotes an N-type source region; reference numeral 8 denotes an N-type drain region; reference numeral 10 designates a diffusion layer of the base; reference numeral 11 designates a contact point; reference numeral 12 denotes a source electrode; reference numeral 13 denotes a drain electrode.

Fig. 17 is a diagram showing an example of wiring connection of a plurality of semiconductor devices of the present invention arranged in a matrix form. These semiconductor devices drive the semiconductor devices with electrothermal conversion elements to be used as liquid ejection heads of liquid ejection apparatuses.

In fig. 17, reference numeral 1 denotes a P-type semiconductor substrate; reference numeral 22 denotes an N-type well region; reference numeral 29 denotes a P-type well region; reference numeral 4 denotes a gate electrode; reference numeral 26 denotes a P-type base region; reference numeral 7 denotes an N-type source region; reference numeral 8 denotes an N-type drain region. The circuit configuration of fig. 17 is the same as that of fig. 4.

In this embodiment, the low concentration P-well region 29 is formed deep to laterally separate the low concentration N-well regions 22 formed in advance at a sufficient depth. Base region 26 is formed in low-concentration P-type well region 29. The P-type well region 29 and the base region 26 perform the functions of the drain and channel of the MIS-type field effect transistor, respectively. Thereafter, the drain concentration may be set lower than the channel concentration. The breakdown voltage of the drain is used to determine the breakdown voltage of the transistor. The lower the impurity concentration of the drain, the deeper the depth of the drain, and the higher the breakdown voltage of the transistor generally becomes. Thus, the rated voltage of the transistor can be set higher, the current flowing through the transistor can be increased, and moreover, high-speed operation of the transistor can be realized.

Since the transistor has a structure in which the P-type well region 29 is formed to separate the N-type well regions 22, the drains of the respective segments can be electrically isolated in a well-separated state, respectively.

[ example 8]

The basic structure of the semiconductor device for a liquid ejecting apparatus according to embodiment 8 of the present invention is the same as that of the semiconductor device of the above-described embodiment 7. The difference therebetween is the location of the drain region 8 and its formation process.

A manufacturing process of the semiconductor device according to the present embodiment is explained with reference to fig. 18A to 18F. The semiconductor device is manufactured with a plurality of electrothermal conversion elements integrated on a semiconductor substrate of the 1 st conductivity type, and a plurality of conversion devices that cause electric current to flow through the plurality of electrothermal conversion elements. The method comprises the following process steps: forming a 2 nd conductivity type semiconductor layer on the main surface of the 1 st conductivity type semiconductor substrate 1, see fig. 18A; forming a gate insulating film 203 on the semiconductor layer, see fig. 18B; forming a gate electrode 4 on the gate insulating film 203, see fig. 18B; doping the 1 st conductive type impurity using the gate electrode 4 as a mask, see fig. 18C; forming a semiconductor region by diffusing the 1 st conductive type impurity, see fig. 18D; using the gate electrode 4 as a mask, a 2 nd conductivity type source region 7 is formed on the surface side of the semiconductor region, and 2 nd conductivity

type drain regions

8 and 9 are formed on the surface side of the 2 nd conductivity type semiconductor layer, see fig. 18E.

The method is described in detail below.

First, as shown in fig. 18A, an N-type well region 22 is formed on the surface of a P-type semiconductor substrate 1. Thereafter, P-type well regions 29 laterally isolating N-type well regions 22 are formed as desired.

Thereafter, as shown in fig. 18B, a gate insulating film (i.e., a gate oxide film) 203 of 50nm thickness is grown on the N-type well region 22 and the P-type well region 29 by, for example, a thermal oxidation method, and a polysilicon film of about 300nm thickness is deposited on the gate insulating film 203 by, for example, an LPCVD method. The polysilicon is given a desired wiring resistance value by, for example, doping phosphorus simultaneously with the deposition by the LPCVD method, or by doping, for example, phosphorus by, for example, ion implantation after the deposition of the polysilicon by the LPCVD method. Then, the photoresist is patterned by photolithography, and the polysilicon film is etched using the photoresist pattern as a mask. As a result, the gate electrode 4 of the MIS type field effect transistor is formed.

Thereafter, a photoresist not shown is applied, and the photoresist is patterned by photolithography, and only the photoresist in the region for forming the base region 26 (or the impurity layer 205) is removed. Then, as shown in fig. 18C, selective ion implantation of P-type impurities such as boron is performed using a resist (not shown) and the gate electrode 4 as a mask.

Thereafter, as shown in fig. 18D, the base region 26 is formed by performing heat treatment at 1100 ℃ for 60 minutes, for example, in an electric furnace. It is important to design base region 26 so as to form a desired effective channel length with a heat treatment without raising the on-resistance of base region 26, the heat treatment conditions being determined by the depth of P-type well region 29, its impurity concentration and impurity type, and the impurity concentration and impurity type of impurity layer 205.

Thereafter, as shown in fig. 18E, the source region 7, the 1 st drain region 8, and the 2 nd drain region 9 are formed by ion implantation of, for example, arsenic using the gate electrode 4 as a mask.

Thereafter, an unillustrated photoresist is applied thereon, and the photoresist is patterned by photolithography. Next, as shown in fig. 18F, the diffusion layer 10 for extracting the base electrode is formed by, for example, ion implantation. Although the diffusion layer 10 for extracting the base electrode is not always required, it is preferable to form the diffusion layer 10 on the circuit design. Further, when the P-type MIS type field effect transistor is formed simultaneously with the signal processing circuit, there is no need to add any process. Thereafter, heat treatment is performed at, for example, 950 ℃ for 30 minutes, and thus, the source region 7, the 1 st drain region 8, the 2 nd drain region 9, and the diffusion layer 10 from which the base electrode is extracted are activated.

Thereafter, although not shown, an oxide film is deposited by a CVD method to form an interlayer insulating film. After that, the contact hole is opened and a wiring is formed. Then, as necessary, a multilayer wiring is performed to produce an integrated circuit. Electrothermal conversion elements are formed in a wiring forming process by a known thin film process, and these elements are integrated on the substrate 1. The circuit configuration in this case is the same as that in each of the embodiments described above.

[ example 9]

Fig. 19 is a sectional view illustrating a manufacturing process of a semiconductor device according to another embodiment of the present invention. In fig. 19, reference numeral 29 denotes a P-type well region; reference numeral 4 denotes a gate electrode; reference numeral 26 denotes a P-type base region; reference numeral 7 denotes an N-type source region; reference numeral 8 denotes an N-type 1 st drain region; reference numeral 9 denotes an N-type 2 nd drain region; reference numeral 211 denotes a photoresist mask.

The purpose of this embodiment is to increase the breakdown voltage between the drain and the source. After the process steps shown in fig. 18A to 18D are performed, as shown in fig. 19, a photoresist mask 211 is formed by patterning a photoresist by photolithography, and thereafter, a source region 7, a 1 st drain region 8, and a 2 nd drain region 9 are formed by ion implantation using, for example, arsenic using the photoresist mask 211 and the gate electrode 4 as masks. At this time, it is important to form the photoresist mask 211 so that the 1 st drain region 8 and the 2 nd drain region 9 are offset from the gate electrode 4. Thereby, the distance between each drain and each source can be sufficiently maintained. Further, since there is no high concentration diffusion layer directly under each gate, a breakdown voltage drop due to electric field concentration can be prevented.

After that, after a process similar to that shown in fig. 18F is performed, an integrated circuit provided with an electrothermal conversion element is similarly manufactured.

[ example 10]

Fig. 20A to 20G are sectional views illustrating a semiconductor device manufacturing process according to embodiment 10 of the present invention.

The method of manufacturing a semiconductor device according to the present embodiment, wherein the semiconductor device integrates a plurality of electrothermal conversion elements on a 1 st conductivity type semiconductor substrate, and a plurality of conversion devices that cause electric current to flow through the plurality of electrothermal conversion elements. The method comprises the following steps: forming a semiconductor layer of 2 nd conductivity type on the main surface of the semiconductor substrate 1 of 1 st conductivity type, see fig. 20A; selectively forming a field insulating film 221 on the semiconductor layer, see fig. 20B; forming a gate insulating film 203 on the semiconductor layer, see fig. 20B; forming a gate electrode 4 on the gate insulating film 203 and the field insulating film 221, see fig. 20C; doping the 1 st conductive type impurity using the gate electrode 4 as a mask, see fig. 20D; forming a semiconductor region by diffusing the 1 st conductive type impurity, see fig. 20E; a 2 nd conductivity type source region 7 is formed on the surface side of the semiconductor region with the gate electrode 4 as a mask, and 2 nd conductivity

type drain regions

8 and 9 are formed on the surface side of the 2 nd conductivity type semiconductor layer with the field insulating film 221 as a mask, see fig. 20F. The method will be described in detail below.

First, as shown in fig. 20A, an N-type well region 22 is formed on the surface of a P-type semiconductor substrate 1. Thereafter, P-well regions 29 are formed that isolate N-well regions 22, as desired.

Thereafter, as shown in fig. 20B, a pad oxide film (not shown) having a thickness of 10nm is grown on the surfaces of N-type well region 22 and P-type well region 29 by, for example, thermal oxidation. A silicon nitride film (not shown) having a thickness of 150nm is deposited on the pad oxide film by, for example, LPCVD. Then, the silicon nitride film is subjected to photolithography etching to pattern the silicon nitride film. Then, the field insulating film 221 is selectively grown to a thickness of 500nm by, for example, a thermal oxidation method. Thereafter, the silicon oxide film is completely removed with, for example, phosphoric acid, and the pad oxide film is removed with, for example, a 10 wt% hydrofluoric acid solution. Thereafter, a gate insulating film 203 having a thickness of 10nm is grown on the N-type well region 22 by, for example, a thermal oxidation method. At this time, although the pad oxide film described above can be used as the gate insulating film 203, it is preferable not to be used because of its reliability. Therefore, as shown in fig. 20B, the gate insulating film 203 as a thin oxide film and the field insulating film 221 as a thick oxide film are deposited at predetermined positions on the N-type well region 22.

Thereafter, as shown in fig. 20C, polysilicon having a thickness of about 300nm is deposited on the gate insulating film 203 and the field insulating film 221 by, for example, LPCVD. Polysilicon is doped, for example, with phosphorus, or doped, for example, by ion implantation with phosphorus, or is subjected to solid phosphorus diffusion after deposition, while being deposited by LPCVD, to give the polysilicon a desired wiring resistance value. Thereafter, as shown, the polysilicon film is patterned by photolithography so that one end of the film is terminated on one of the gate insulating films 203 and the other end is terminated on one of the field insulating films 221, and the polysilicon film is etched. As a result, the gate electrode 4 of the MIS type field effect transistor is formed.

Next, a photoresist not shown is applied, and thereafter, the photoresist is patterned by photolithography so as to remove the photoresist in a region where the base region 26 (or the impurity layer 205) is to be formed. Thereafter, as shown in fig. 20D, selective ion implantation of P-type impurities such as boron is performed using a photoresist mask (not shown) and the gate electrode 4 as masks, thereby forming an impurity layer 205.

Thereafter, as shown in fig. 20E, a base region 26 for determining the effective channel length of the MIS type Field Effect Transistor (FET) is formed by performing a heat treatment at, for example, 1100 ℃ for 60 minutes in an electric furnace. It is important to design the thermal process so that the base region 26 is used to determine the required effective channel length to prevent its on-resistance from rising. Further, in the lateral direction, it is required to design the heat treatment so that the base region 26 is located near the boundary between the gate insulating film 203 and the field insulating film 221. The reason for this is that if the base region 26 is formed only half the distance to the gate insulating film 203, an electric field generated under the gate electrode 4 is concentrated on the thin gate insulating film 203, damaging the gate insulating film 203. Moreover, if the base region 26 is formed up to the thick field insulating film 221, even when a predetermined voltage is applied to the gate electrode 4, the base region under the thick field insulating film 221 is not inverted, and the base region 26 does not perform the switching function of the MIS type field effect transistor. Therefore, even when the switching device is turned on, its driving performance is greatly deteriorated. Thus, the heat treatment conditions are appropriately determined by the depth of P-type well region 29, the impurity concentration and the impurity type of impurity layer 205, and the mask size.

Thereafter, as shown in fig. 20F, ion implantation is performed with, for example, arsenic using the gate electrode 4 as a mask to form a source region 7; the same ion implantation is performed using the field insulating film 221 as a mask, and the 1 st drain region 8 and the 2 nd drain region 9 are formed.

Thereafter, an unillustrated photoresist is applied and the photoresist is patterned by photolithography. After that, the photoresist is removed only in the region where the diffusion layer 10 of the extraction base electrode 4 is to be formed. Thereafter, as shown in fig. 20G, the diffusion layer 10 from which the base electrode 4 is to be extracted is formed by, for example, ion implantation. Although the diffusion layer 10 for extracting the electrode of the base electrode 4 is not always necessary, it is preferable to form a diffusion layer on the circuit design. Further, the P-type MIS type field effect transistor is formed at the same time as the signal processing circuit, without increasing the number of processes. Thereafter, heat treatment is performed at, for example, 950 ℃ for 30 minutes, after which the source region 7, the 1 st drain region 8, the 2 nd drain region 9, and the diffusion layer 10 from which the base electrode 4 is extracted are activated. Therefore, the insulator formed with the field insulating film 221 at the electric field concentration on the drain side under the gate electrode 4 can improve the breakdown voltage between the gate and the drain of the MIS type field effect transistor. For example, in the case where a complementary MIS type field effect transistor requiring high-speed operation is formed simultaneously on the same substrate on which a MIS type field effect transistor requiring high breakdown voltage is formed, an insulator can be formed without any additional process. Therefore, the field insulating film 221 is formed extremely efficiently.

After that, although not shown, an oxide film is deposited by a CVD method to form an interlayer insulating film. After that, the contact hole is opened to form a wiring. As necessary, a plurality of layers of wirings are formed, and thus, an integrated circuit is manufactured. The electrothermal conversion elements are formed in a wiring forming process by a known thin film process, and the electrothermal conversion elements are integrated on the substrate 1. The circuit configuration in this case is the same as that in the foregoing several embodiments.

[ example 11]

FIG. 21 is a sectional view of another production process in accordance with example 11 of the present invention. In fig. 21, reference numeral 22 denotes an N-type well region; reference numeral 26 denotes a P-type base region; reference numeral 7 denotes an N-type source region; reference numeral 211 denotes a photoresist mask; reference numeral 232 denotes a channel doping layer; reference numeral 233 denotes a channel.

The present embodiment is directed to controlling the threshold level of the MIS type field effect transistor to a predetermined threshold level. After the processes shown in fig. 18A to 18D are performed, as shown in fig. 21, a photoresist mask 211 is formed by photolithography, and then, boron ion implantation, for example, is performed using acceleration energy of 100keV or more, for example, 120keV, using the photoresist mask 211 as a mask, to form a channel dope layer 232. At this time, it is important that the channel dope layer 232 is formed at least in the source region 7 in the base region 26 (actually, the source region is not formed in the present process but the source region 7 is formed in a subsequent process), and in a portion to become the channel 233 between the N-type well regions 22. Although the photoresist mask 211 is not always required, it does not cause a problem when ion implantation is performed on the entire surface. However, when the concentration of N-type well region 22 is extremely low, it is preferable to use photoresist mask 211. Furthermore, the formation of the channel dope layer 232 is not necessarily performed in the present process, and it may be formed during the processes from the formation of the base region 26 to the final activation annealing. Thus, the channel 233 can be designed to have a desired concentration, and the MIS field effect transistor can be controlled to have a predetermined threshold.

Thereafter, a process similar to that after fig. 18E is performed, and an integrated circuit provided with an electrothermal conversion element is similarly manufactured.

[ example 12]

Fig. 22 is a partially cross-sectional schematic view of a recording head of an electrothermal conversion element-driving semiconductor device according to the foregoing embodiments 7 to 11 of the present invention. In fig. 22, reference numeral 1 denotes a P-type semiconductor substrate made of single crystal silicon; reference numeral 29 denotes a P-type well region; reference numeral 22 denotes an N-type well region; reference numeral 8 denotes an N-type drain region; reference numeral 26 denotes a P-type base region; reference numeral 7 denotes an N-type source region; reference numeral 4 denotes a gate electrode. These elements constitute a semiconductor device 930 driven with one electrothermal conversion element of the MIS type field effect transistor. 817 denotes an insulating layer such as silicon oxide, which functions as a heat storage layer; 818 to heat resistant layer; 819 means a wiring; 820 refers to a protective layer. These elements constitute a substrate 940 of the recording head. Here 850 refers to the heating section; ink is ejected from the discharge portion 860. Also, the top plate 870, in combination with the substrate 940, forms a liquid channel 880.

As described above, according to embodiments 7 to 12 of the present invention, their drain concentration can be set lower than their channel concentration, and the drain can be formed deeper. Therefore, these semiconductor devices have high breakdown voltages and can flow large currents. Also, since their on-resistances are low, high-speed operation is possible, thereby enabling high integration and power saving. Further, in the semiconductor device having a plurality of transistors in a matrix-shaped structure as required in the embodiments, the respective devices are easily isolated without increasing any cost.

In embodiments 7 to 12, as a measure in the case of forming the deep N-type well region 22, the P-type well region 29 is formed by introducing an impurity, and thereafter, the base region 26 is formed in another process. When the deeper N-type well region 22 is not required, isolation is formed in the lateral direction for the N-type well region 22 in each drain region, and thus even if the base region 26 is not formed deeper than the N-type well region 22, the base region 26 is adjacent to the P-type substrate 1 in which the upper portion of the substrate 1 is left between two adjacent N-type well regions. Thus, the base region 26 and the substrate 1 can be at the same potential.

The following describes a method for manufacturing a semiconductor device according to each embodiment, which is roughly characterized by including the steps of: forming a semiconductor layer of a 2 nd conductivity type on a main surface of a semiconductor substrate of a 1 st conductivity type; forming a gate insulating film on the semiconductor layer; forming a gate electrode on the gate insulating film; doping the 1 st conductive type impurity using the gate electrode as a mask; diffusing the 1 st conductive type impurity to form a semiconductor region; a2 nd conductivity type source region is formed on a surface side of the semiconductor region and a 2 nd conductivity type drain region is formed on a surface side of the 2 nd conductivity type semiconductor layer using the gate electrode as a mask. These methods are also characterized by: a transistor structure can be made that is symmetrical with respect to the source region. These methods are described in detail below.

[ example 13]

The semiconductor device according to the manufacturing method of the semiconductor device of embodiment 13 of the present invention is provided with a plurality of insulated gate field effect transistors in a matrix shape. The method comprises the following steps: forming a well region of a 2 nd conductivity type on a main surface of a semiconductor substrate of a 1 st conductivity type; forming a gate insulating film in the well region; forming a plurality of gate electrodes on the gate insulating film; performing ion implantation at a fixed angle with respect to a normal line of the semiconductor substrate while the semiconductor substrate is rotated, in such a manner that a 1 st conductivity type semiconductor region is formed by diffusing a 1 st conductivity type impurity after performing ion implantation between two adjacent gate electrodes on a source region formation side using the two gate electrodes as masks; forming a 2 nd conductivity type source region in the semiconductor region using the two gate electrodes as masks, and forming a 2 nd conductivity type drain region in the two deposited well regions, respectively, at a fixed angle with respect to a normal direction of the semiconductor substrate with the semiconductor region interposed therebetween, in a case where the semiconductor substrate is rotated.

In many cases, in various devices made using a semiconductor wafer, an Orientation Flat (OF) is formed in a surface direction OF 90 degrees or 45 degrees with respect to a main crystal direction OF the semiconductor wafer. And the coordinate axis of the semiconductor device is made perpendicular or parallel to the orientation flat. When ion implantation is performed in the vertical direction toward the planar direction of the semiconductor substrate (for example, (100) crystal plane), if a device configured in this way is formed by ion implantation, a channel is generated.

When a crystal of, for example, single crystal silicon is viewed from a direction perpendicular to a crystal plane having a small index such as a (100) plane, (110) plane, (111) plane, or the like, the area occupied by the atom train in the crystal plane is several percent, and almost all of the crystal plane is occupied by space. That is, when ions are irradiated to the crystal plane at the same angle as the crystal axis, a phenomenon occurs in which most of the ions reach the inside of the crystal without any large collision with atoms.

When such a channel phenomenon occurs, the impurity distribution in the silicon substrate is greatly different from the implanted impurity distribution in the substrate calculated assuming that the silicon substrate is amorphous. Thus, the electrical characteristics of the device are quite different from the design characteristics.

Therefore, when ion implantation is performed at an implantation angle larger than a crystal angle calculated using a crystal axis of a substrate, a kind of impurity to be implanted, implantation energy, and the like as parameters, a channel prevention technique is generally used.

In the case of a matrix of MIS type field effect transistors having a common drain for each stage, as shown in fig. 1, since the drain of each transistor is common, the crystal plane direction of the main surface direction of the substrate constituting the semiconductor device is the low-sized crystal plane direction of single crystal silicon, there is a case where the characteristics are different between adjacent transistors.

That is, as shown in fig. 23, in the case where a common drain is provided in a matrix of MIS type field effect transistors, after a well region 2, a base region 6, a gate electrode 4 and a photoresist mask 211 are formed on a semiconductor substrate 1, an incident angle θ of an ion beam 312 is set so as to be obliquely incident toward the drain or the source from a normal line 311 from the gate electrode 4 to a main surface of the semiconductor substrate (wafer) 1, and ions are implanted into source regions provided on both sides of the drain at incident angles (- θ) in respective opposite directions as viewed from one side of the drain.

In the above-described method of manufacturing the MIS type field effect transistor, since the effective channel is adjusted by the impurity diffusion in the P type base region 6 and the N type source region 7, if the ion implantation is performed at an oblique incident angle, the effective channel lengths of two adjacent MIS type field effect transistors are different from each other.

In this case, the following performance deterioration occurs; threshold voltages of adjacent transistors are different, and when the MIS type field effect transistor operates, current values flowing through the adjacent transistors are different.

Due to the fact that the impurity amount of ion implantation is different, different ion implantation devices are used for forming the P-type base region 6 and the N-type source region 7. When the critical implantation angles specified in each ion implantation apparatus are different from each other, the characteristics of adjacent transistors are more significantly different in the matrix arrangement of the MIS type field effect transistors having the common drain.

Further, the larger the critical incident angle of the ion implantation apparatus for forming the base region is, the smaller the critical incident angle of the ion implantation apparatus for forming the source region is, and the larger the difference in effective channel length between adjacent transistors is.

However, when the MIS type field effect transistors having the common drain are arranged in a matrix, as shown in fig. 24A and 24B, the incident angle θ or- θ at which the ion beam 313 or 314 is inclined from the normal line 311 of the main surface of the semiconductor substrate 1 is set in the same direction as the arrangement direction of the gate electrode 4, and the above-described change in the characteristics between the adjacent transistors does not occur. However, as shown in fig. 25A and 25B, assuming that the ion beam direction is set to the direction of the incident angle θ or- θ inclined from the direction of the normal 311 to the main surface of the semiconductor substrate 1 in the arrangement direction perpendicular to the gate electrode 4, as the

ion beam

315 or 316, the matrix arrangement becomes a transistor matrix having a symmetrical cross-sectional structure shown on the right and left sides of fig. 26. As a result, a defect of inconsistency in characteristics between adjacent transistors arranged in a matrix shape is generated. This dependence of the ion beam incident angle becomes a significant limitation on the circuit layout.

Thus, this embodiment performs ion implantation while the semiconductor substrate is rotating, enabling each transistor to maintain symmetry regardless of the circuit layout on the wafer.

According to the method of manufacturing a semiconductor device of the present embodiment, in forming the base region 6, the source region 7 and the drain region 8, impurities are implanted into the channel at a critical angle while the substrate 1 (i.e., the wafer 121) is rotated in its peripheral direction, as shown in fig. 27 and 28. Therefore, the positional relationship among the end face of the base region 6 formed by ion-implanting an impurity introduced by thermal diffusion implantation, the end face of the source region 7 and the end face of the drain region 8 formed by ion-implanting an impurity introduced by thermal diffusion implantation, and the end faces of the source region 7 and the drain region 8 formed by ion-implanting an impurity introduced by thermal diffusion implantation, can be formed in a well-controlled state regardless of how the transistor is provided on the main surface of the semiconductor substrate 1.

That is, in the case of the matrix arrangement of the MIS type field effect transistors having the common drain, as shown in fig. 27, after the well region 2, the base region 6, the gate electrode 4, and the mask 211 are formed, an incident angle 192 between the ion beam 317 in a direction from the gate electrode 4 to the surface of the substrate 1 into the

drain

8 or 9 or the source 7 and the normal line 311 of the semiconductor substrate 1 (wafer) is set to θ. While the semiconductor substrate 1 is rotated in its outer circumferential direction, ion beams can be implanted in the following manner so that ions are uniformly implanted into the mask 211. Moreover, the effective channel lengths of two adjacent MIS type field effect transistors become the same or substantially the same.

Incidentally, in the process of implanting impurities in forming the base region 6, the source region 7 and the

drain regions

8, 9, the substrate 1 is preferably rotated at a speed of 10 to 60 rpm. Although the center of rotation is associated with the scan region of the ion beam, the center of rotation may be the center of the wafer or may be a location other than the center of the wafer. Further, it is preferable that the ion implantation of the impurity is divided into 4 to 8 times, and the ion implantation is performed at angular intervals in the range of 45 to 90 degrees, and the substrate 1 is rotated. It is preferable to perform ion implantation at angular intervals of 45 degrees by dividing 8 times.

The semiconductor device thus manufactured has a cross-sectional structure symmetrical on the right and left as shown in fig. 29A and 29B. Here, the transistor includes a well region 2 on a semiconductor substrate 1, a deeply formed base region 6 completely isolating the well region 2, a source region 7 formed on the base region 6, a drain region 8 formed in the well region 2, a gate electrode 4 formed on a gate insulating film, a source electrode 12 connected to the source region 7, and a drain electrode connected to the drain region 8. Reference numeral 14 denotes a contact hole.

Further, the base region 6 and the source region 7 are formed using the gate electrode 4 as a mask. As described above, the substrate 1 is preferably rotated at a speed of 10 to 60rpm when the above-mentioned region is formed. Alternatively, it is preferable to rotate the substrate 1 at angular intervals of 45 to 90 degrees and perform ion implantation 4 to 8 times. It is preferable to perform ion implantation at angular intervals of 45 degrees by dividing 8 times. Further, when the main surface of the semiconductor substrate 1 is, for example, a (100) plane, a (110) plane or a (111) plane, the inclination angle of the ion beam with respect to the normal line of the semiconductor substrate 1 is in the range of 3 degrees to 10 degrees, preferably 7 degrees. As a preferable condition for the production, the direction of the ion beam is preferably inclined at an angle of 7 degrees with respect to the normal direction of the semiconductor substrate 1 which is the (100) plane.

As a result, the channel lengths of the transistors arranged in a matrix shape become uniform. Thus, no dimensional difference due to alignment is caused. An MIS type field effect transistor whose threshold value does not have any dispersion can be produced. Moreover, high yield and high reliability can be achieved.

[ example 14]

Fig. 13A to 13E are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the present invention.

This embodiment is a method of manufacturing a field effect transistor having a plurality of insulated gates arranged in a matrix shape, the method including the steps of: forming a 1 st semiconductor region of the 2 nd conductivity type on the main surface of the 1 st conductivity type semiconductor substrate 1, see fig. 30A; forming a gate insulating film 203 over the 1 st semiconductor region, see fig. 30B; a plurality of gate electrodes 4 are formed on the gate insulating film 203, see fig. 30B; using the two gate electrodes as a mask, diffusing the 1 st conductivity type impurity after implanting the impurity between the two adjacent gate electrodes at a fixed angle to the normal direction of the semiconductor substrate with the semiconductor substrate 1 being rotated to form a 1 st conductivity type 2 nd semiconductor region, see fig. 30C and 30D; a 2 nd conductivity type source region is formed in the 2 nd semiconductor region using the two gate electrodes as masks, and in the case where the semiconductor substrate 1 is rotated, 2 nd conductivity type drain regions 9 are formed in the two deposited 1 st semiconductor regions at fixed angles with respect to the normal direction of the semiconductor substrate 1, respectively, with the 2 nd semiconductor region placed therebetween for ion implantation, see fig. 30E. The method will be described in detail below.

As shown in fig. 30A, an N-type well region 2 is formed on the main surface of a P-type semiconductor substrate 1. The N-type well region 2 may also be formed on the entire main surface of the P-type semiconductor substrate 1, or the well region 2 may be selectively formed as needed. Further, when the N-type well region 2 is formed over the entire main surface of the P-type semiconductor substrate 1, an epitaxial growth method can be used.

Thereafter, as shown in fig. 30B, a gate insulating film 203 having a thickness of 50nm is grown on the N-type well region 2 by, for example, a thermal oxidation method, and a polysilicon film having a thickness of 300nm is deposited on the gate insulating film 203 by, for example, an LPCVD method. The polysilicon film is doped with phosphorus by, for example, doping phosphorus by an LPCVD method while depositing the polysilicon film, or by doping phosphorus by, for example, an ion implantation method, or by solid-state diffusion after depositing the polysilicon film, so that the polysilicon film has a prescribed resistance value. Thereafter, a resist mask (not shown) is formed by a photolithography patterning method, and the polysilicon film is etched, whereby the gate electrode 4 of the MIS type field effect transistor can be formed.

Thereafter, as shown in fig. 30C, a resist mask (not shown) is formed by photolithography patterning, and the gate electrode 4 is also used as a mask. Selective ion implantation of P-type impurities such as boron ion implantation is performed on the main surface of semiconductor substrate 1 while substrate 1 is rotated about its center in the peripheral direction thereof, as shown in fig. 28, and thereafter, impurity layer 205 is formed.

Thereafter, as shown in fig. 30D, the base region 6 electrically isolating the well region 2 in the horizontal direction is formed by performing a heat treatment at 1100 ℃ for 60 minutes in an electric furnace, for example. The heat treatment is preferably designed such that the base region 6 is formed deeper than the well region 2 to completely isolate the well region 2, and the heat treatment conditions are determined according to the depth of the well region 2, the impurity concentration and the impurity type, the impurity concentration of the impurity layer 205, and the impurity type. In the structure shown here, the base region 6 reaches the P-type semiconductor substrate 1, but the structure of the base region 6 is not limited to this structure.

Thereafter, as shown in fig. 30E, while the substrate 1 is rotated, arsenic ion implantation, for example, is performed using the gate electrode 4 as a mask, and the 1 st drain region 8 and the 2 nd drain region 9 are formed. As shown in fig. 28.

Thereafter, heat treatment is performed at, for example, 950 ℃ for 30 minutes, and thus, the source region 7, the 1 st drain region 8, and the 2 nd drain region 9 are activated.

Here, since the source is common, the source region 7, the base region 6, the well region 2, and the 1 st drain region 8 on the left side of the drawing constitute a source, a channel, and a drain of one MIS type field effect transistor, respectively, and the source region 7, the base region 6, the well region 2, and the 2 nd drain region 9 on the right side of the drawing constitute a source, a channel, and a drain of another MIS type field effect transistor, respectively.

Then, although not shown, an oxide film is deposited by a CVD method to form an interlayer insulating film. After that, a contact hole is opened to form a wiring, and then, a multilayer wiring is performed as necessary, thereby manufacturing an integrated circuit. Electrothermal conversion elements, which are integrated on the substrate 1, are formed by a wiring forming process using a known thin film process. The circuit configuration in this case is the same as that in each of the above embodiments.

The manufacturing method of the present embodiment is suitable for manufacturing the recording head of the liquid ejecting apparatus described above.

[ example 15]

Fig. 31A to 31F are sectional views illustrating a manufacturing process of the semiconductor device according to the present embodiment.

The semiconductor device in the semiconductor device manufacturing process of the present embodiment has a plurality of insulated gate field effect transistors arranged in a matrix type, and the method includes the steps of: a well region 2 of the 2 nd conductivity type is formed on the main surface of the 1 st conductivity type semiconductor substrate 1, see fig. 31A; a field insulating film 221 is selectively formed over the well region 2, see fig. 31B; a gate insulating film 203 is formed over the well region 2, see fig. 31B; forming a gate electrode 4 on the gate insulating film 203 and the field insulating film 221, see fig. 31C; implanting impurities between two adjacent gate electrodes on the source region formation side at a fixed angle to the normal direction of the semiconductor substrate 1 while the semiconductor substrate 1 is rotated, using the two gate electrodes as masks, to form a 1 st conductivity type semiconductor region by diffusing the 1 st conductivity type impurities, see fig. 31D and 31E; a source region 7 of the 2 nd conductivity type is formed in the semiconductor region using the two gate electrodes 4 as masks, and

drain regions

8, 9 of the 2 nd conductivity type are formed in the two deposited well regions 2, respectively, with the semiconductor substrate 1 rotated, at a fixed angle to the normal direction of the semiconductor substrate 1 using the field insulating film 211 as a mask, with the semiconductor region disposed therebetween, see fig. 31F, the method of which will be described in detail below.

As shown in fig. 31A, an N-type well region 2 is formed on the surface of a P-type semiconductor substrate 1.

Thereafter, a pad oxide film (not shown) having a thickness of about 10nm is grown on the surface of the well region 2 by, for example, a thermal oxidation method. A silicon nitride film (not shown) having a thickness of 150nm is deposited on the pad oxide film by, for example, LPCVD. Thereafter, the silicon nitride film is etched by a photolithography pattern. Thereafter, the field insulating film 221 is selectively grown to a thickness of 500nm by, for example, a thermal oxidation method. Thereafter, the silicon oxide film is completely removed with, for example, phosphoric acid, and the pad oxide film is removed with, for example, a 10 wt% hydrofluoric acid solution. After that, a gate insulating film 203 having a thickness of 10nm is grown on the N-type well region 2 by, for example, a thermal oxidation method. At this time, although the pad oxide film can be used as the gate insulating film 203, it is not preferable because of its reliability. Therefore, as shown in fig. 31B, a gate insulating film 203 as a thin oxide film and a field insulating film as a thick oxide film are deposited at desired positions on the N-type well region 2.

Thereafter, as shown in fig. 31C, a polysilicon film having a thickness of about 300nm is deposited on the gate insulating film 203 and the field insulating film 221 by, for example, LPCVD. The polysilicon film is doped with phosphorus by, for example, doping phosphorus by an LPCVD method, or doping phosphorus by, for example, ion implantation, or doping phosphorus by solid state diffusion after depositing the polysilicon film, so that the polysilicon film has a desired resistance value. Thereafter, as shown in the drawing, a polysilicon film is patterned by photolithography so that one end of the polysilicon film is terminated on one of the gate insulating films 203 and the other end of the polysilicon film is terminated on one of the field insulating films 221, and the polysilicon film is etched. As a result, the gate electrode 4 of the MIS type field effect transistor is formed.

Thereafter, as shown in fig. 31D, an impurity layer 205 is formed by selective ion implantation of a P-type impurity, for example, boron, into the main surface of the P-type semiconductor substrate 1 using the gate electrode 4 as a mask with the substrate 1 being rotated by photolithography patterning, as shown in fig. 28.

Thereafter, as shown in fig. 31E, the base region 6 of the lateral electrically isolated well region 2 is formed by heat treatment at, for example, 1100 ℃ for 60 minutes in an electric furnace. The heat treatment is required to be designed so that the base region 6 becomes deeper than the well region 2, the well region 2 is completely isolated in the vertical direction by the base region 6, and the heat treatment is required to be designed so that the base region 6 is located in the vicinity of the lateral boundary between the gate insulating film 203 and the field insulating film 221. The reason for this is that if the base region 6 is formed only half of the gate insulating film 203, an electric field generated under the gate electrode 4 may be concentrated to the thin gate insulating film 203, damaging the gate insulating film 203. Moreover, if the base region 6 is formed so as to reach the thick field insulating film 221, the base region 6 under the thick field insulating film 221 is not inverted even if a predetermined voltage is applied to the gate electrode 4, and it is difficult for the base region 6 to perform the switching function of the MIS type field effect transistor. Therefore, even when the switching device is turned on, its drivability is greatly impaired. Therefore, the heat treatment conditions are determined by the depth, the impurity concentration and the impurity species of the well region 2, and the impurity concentration and the impurity species of the impurity layer 205 and the size of the mask.

Thereafter, as shown in fig. 31F, when the substrate 1 is rotated, for example, arsenic ion implantation is performed on the main surface of the P-type semiconductor substrate 1, the source region 7 is formed using the gate electrode 4 as a mask, and the 1 st drain region 8 and the 2 nd drain region 9 are formed using the field insulating film 211 as a mask, as shown in fig. 28.

Thereafter, heat treatment is performed at, for example, 950 ℃ for 30 minutes, after which the source region 7, the 1 st drain region 8, and the 2 nd drain region 9 are activated. Therefore, forming the insulator on the drain side where the electric field is concentrated under the gate electrode 4 with the field insulating film 221 can improve the breakdown voltage between the gate and the drain of the MIS type field effect transistor. For example, in the case where a complementary MIS type field effect transistor requiring high-speed operation is formed on the same substrate while forming a MIS type field effect transistor requiring high breakdown voltage, an insulator can be formed very efficiently without any additional process.

After that, although not shown, an oxide film is deposited by a CVD method to form an interlayer insulating film. After that, the contact hole is opened to form a wiring. Multiple layers of wiring may be performed as needed, thus ultimately making an integrated circuit. Electrothermal conversion elements, which are integrated on the substrate 1, are formed by a wiring forming process using a known thin film process. The circuit configuration in this case is the same as that of the above-described embodiment.

As described above, according to embodiments 13 to 15, since impurity ion implantation is performed with the substrate 1 rotated when at least one of the base region 6, the source region 7, and the

drain regions

8, 9 is formed, in a semiconductor device required to have a matrix-shaped structure constituted by a plurality of transistors, the device structures of the transistors with the commonly-drawn source electrode interposed therebetween on both sides can be formed into the same and symmetrical structure, and the threshold voltage and the on-resistance at the time of their operation can be accurately formed in the design values.

Therefore, a MIS type field effect transistor having a high breakdown voltage and capable of high-speed operation can be manufactured at a high yield, high reliability and low cost.

[ example 16]

The above-mentioned examples 13 to 15 are effective in the case where the wafer (substrate) used has a main surface oriented in a low-dimensional crystal plane of the silicon single crystal constituting the wafer, for example, a (100) plane, that is, in the case of a so-called junst substrate.

In the following embodiments, a method of manufacturing a semiconductor device is described in which a rotating substrate is not always required.

In the semiconductor device of this embodiment, there are a plurality of insulated gate field effect transistors arranged in a matrix shape. Each insulated gate Field Effect Transistor (FET) includes: a 1 st semiconductor region of a 2 nd conductivity type formed on a 1 st conductivity type semiconductor substrate, the 1 st conductivity type semiconductor substrate including one crystal plane orientation inclined toward a low-dimensional crystal direction (e.g., θ ═ 4)⁰) A major surface of (a); a 2 nd semiconductor region of the 1 st conductivity type separating the 1 st semiconductor region, the 2 nd semiconductor region having a higher concentration than the 1 st semiconductor region; a source region of a 2 nd conductivity type formed in the 2 nd semiconductor region; and a drain region of the 2 nd conductivity type formed in the 1 st semiconductor region.

Further, the manufacturing method of the semiconductor device includes the steps of; the crystal plane orientation at its main surface is inclined with respect to a lower-dimensional crystal direction (e.g., θ 4)⁰) Forming a well region of a 2 nd conductivity type on the semiconductor substrate of the 1 st conductivity type; forming a gate insulating film in the well region; forming a gate electrode on the gate insulating film; using the gate electrode as a mask, after doping impurities into the semiconductor substrate in a vertical direction (including a substantially vertical direction), diffusing the impurity of the 1 st conductivity type to form a base region; impurity ions are implanted into the semiconductor substrate in vertical directions (including substantially vertical directions), respectively: a source region of the 2 nd conductivity type is formed in the base region using the gate electrode as a mask, and a drain region of the 2 nd conductivity type is formed in the well region.

Further, another manufacturing method of the semiconductor device includes the steps of: forming a well region of a 2 nd conductivity type on a semiconductor substrate of the 1 st conductivity type having a main surface whose crystal plane direction is inclined to a lower-dimensional crystal plane direction (e.g., θ is 4 degrees); selectively forming a field insulating film in the well region; forming a gate insulating film in the well region; forming a gate electrode on the gate insulating film and the field insulating film; using the gate electrode as a mask, doping impurities into the semiconductor substrate in a vertical direction (including a substantially vertical direction), and then diffusing the impurities of the 1 st conductivity type to form a base region; impurity ions are implanted into the semiconductor substrate in vertical directions (including a substantially vertical direction) to form a source region of the 2 nd conductivity type in the base region using the gate electrode as a mask, and to form a drain region of the 2 nd conductivity type in the 2 nd conductivity type well region using the field insulating film as a mask, respectively.

In the present embodiment, as shown in fig. 32, the crystal plane direction of the main surface of the semiconductor substrate 201 is inclined, for example, by θ, by 4 degrees with respect to the low-dimensional crystal plane direction 412 used in the conventional semiconductor device fabrication ((100 > crystal direction of the 100) plane substrate). Even when ion implantation is performed in the normal direction of the semiconductor substrate 201 in this manner, a channel does not occur. In addition to the <100> crystal orientation of the (100) crystal plane, there are also a <110> crystal orientation of the crystal plane (110) and a <111> crystal orientation of the crystal plane (111) as the low-dimensional crystal orientation. It is desirable to set the direction to be inclined at an angle of 3 to 10 degrees, preferably 4 degrees, with respect to the normal direction.

For example, by slicing a wafer from a single crystal ingot, the wafer is tilted at a fixed angle with respect to the direction of the low-dimensional crystal plane, thereby achieving the tilt of the low-dimensional crystal direction. Further, in order to indicate a crystal plane of the semiconductor main surface, a Miller index, for example, an indication of (100) is generally used. And a crystal axis corresponding to the main surface is indicated by, for example, a symbol <100> and corresponds to a normal line of the (100) crystal plane. The term "inclination with respect to the crystal direction" means that the main surface of the substrate is inclined with respect to, for example, the (100) crystal plane of a single crystal, that is, inclined with respect to the normal direction <100> of the main surface.

A substrate inclined with respect to the crystal orientation of its single crystal is called an OFF substrate, and a substrate having an inclination of 0 is called a JUST substrate.

For example, when simple N-type MOS FETs are actually formed on various substrates, the carrier mobility thereof is measured, and as a result,

< Carrier mobility of NMOS >

Type of substrate	P (100) JUST substrate	P (100)4 DEG OFF substrate
Type of substrate	P (100) JUST substrate	P (100)4 DEG OFF substrate	NMOS50/50(μm)	619(cm²/v·sec)	586(cm²/v·sec)
NMOS50/3	609	569	NMOS50/50(μm)	619(cm²/v·sec)	586(cm²/v·sec)
NMOS50/3	609	569	NMOS12/3	617	576

That is, the carrier mobility of the OFF substrate inclined by 4 degrees becomes smaller by 3% compared to the JUST substrate without inclination. However, this difference does not matter in actual use.

In the semiconductor device and the manufacturing method thereof according to the present invention, since impurity implantation is performed in a direction perpendicular to the semiconductor substrate 1 when forming the base region 6, the source region 7, and the

drain regions

8 and 9, the transistor structure is formed in which the positional relationship between the end face of the base region 6, the end faces of the source region 7 and the

drain regions

8 and 9 is symmetrical to each other, the end face of the base region 6 is formed with an impurity introduced by ion implantation and an impurity subjected to thermal diffusion implantation, and the end faces of the source region 7 and the

drain regions

8 and 9 are formed with an impurity subjected to the same ion implantation and impurity introduction and thermal diffusion implantation, whereby the transistor can be formed in a well-controlled state regardless of how the transistor is provided on the main surface of the semiconductor substrate 1.

That is, in the case of a matrix type arrangement of MIS type field effect transistors having a common drain, as shown in fig. 32 and 33, after forming the well region 2, the base region 6, the gate electrode 4 and the photoresist mask 211 on the semiconductor substrate 201 whose crystal orientation of the main surface is inclined (for example, θ is 4 degrees) with respect to the crystal orientation of the low size, uniform ion implantation 413 is performed into the main surface from the gate electrode 4 to the right and left for the drain or the source to the mask in the vertical direction. Therefore, the effective channel lengths of two adjacent MIS type field effect transistors are made the same (even if there is a small error, the lengths can be considered to be the same).

The manufacturing process of the present embodiment is substantially the same as that of the embodiment described with reference to fig. 6 to 9. The difference is only that the present embodiment uses an OFF substrate as the substrate. According to this embodiment, the limitation on the wafer is removed, and a good semiconductor device can be manufactured at low cost.

As described above, according to embodiment 16 of the present invention, even when impurity implantation is performed in the vertical direction into the semiconductor substrate 801 while forming the base region 6, the source region 7, and the

drain regions

8 and 9, no variation in design value due to the channel occurs at the time of impurity implantation. Further, like the semiconductor device described in the related art, in the semiconductor device requiring a matrix-shaped structure composed of a plurality of transistors, embodiment 16 can form the same device structure on both sides of the common source electrode drawn out, and can form transistors having precise threshold values and on-resistances at the time of operation according to their design values.

Therefore, example 16 can produce a MIS type field effect transistor having a high breakdown voltage and capable of high-speed operation at a low cost with high yield and high reliability.

< liquid ejecting apparatus >

An ink jet printer is described as an example of the liquid ejecting apparatus according to the present invention.

Fig. 34 is a circuit configuration diagram of a semiconductor device constituting a recording head of an ink jet printer according to the present invention. Semiconductor devices made in conjunction with all of the above embodiments may be used.

Reference numeral 41 denotes a matrix of electrothermal conversion elements as a load; reference numeral 42 denotes a matrix of switching devices; reference numeral 43 denotes a logic gate matrix; reference numeral 44 denotes a self-locking circuit; reference numeral 45 denotes a shift register.

Reference numeral 46 denotes a terminal for supplying a source voltage VDD; reference numeral 47 denotes a terminal supplied to a ground voltage VSS; reference numeral 48 denotes a terminal to which a timing control signal is input to the switching devices in the matrix 42; reference numeral 49 denotes a terminal to which a control signal is input to the self-lock circuit 44; reference numeral 50 denotes a terminal to which an image signal is input; reference numeral 51 denotes a terminal to which a clock signal is input.

A matrix 41 of electrothermal transducer elements, a matrix 42 of transducer devices, a matrix 43 of logic gates, a latch circuit 44 and a shift register 45 are arranged in parallel with each other on one chip, and the layout is substantially the same as that shown in fig. 34.

The digital image signal inputted from the terminal 50 is reset to a parallel signal by the shift register 45, and the reset image signal is latched by the latch circuit 44. When the logic gate is activated, the switching devices in the matrix 42 are turned on or off according to a signal latched by the latch circuit 44, and a current is caused to flow through the electrothermal conversion elements selected in the matrix 41.

The transistors in each of the embodiments described above are suitable for use as switching devices in the matrix 42. It is preferable that no dedicated isolation region is formed between the switching devices in the matrix 42, and isolation regions such as a field insulating film are preferably not formed between a plurality of matrices, for example, between the

matrices

42 and 41, between the matrices 42 and 43 (or between the latch circuit 44 and the shift register 45).

Fig. 35 is a schematic view of a liquid ejecting head.

A plurality of rows of electrothermal conversion elements (i.e., heaters) are provided on a device substrate 52 on which a circuit shown in fig. 34 is formed, and ink is ejected from the discharging portion 53 by bubbles generated by heat generated by current flowing through the elements. Each electrothermal conversion element 41 is provided with wiring electrodes 54, and the wiring electrodes 54 are electrically connected at end edges to the conversion devices 42 in the matrix 42.

A passage 55 for supplying ink to the discharging portions 53 disposed opposite the electrothermal conversion elements is formed corresponding to each discharging portion 53. Walls constituting the discharging portions 53 and the channels 55 are formed in the grooved member 56, and the channels 55 and a common liquid tank 57 for supplying ink to the plurality of channels 55 are formed with the grooved member 56 and the device substrate 52.

Fig. 36 shows the structure of a liquid ejecting head equipped with a device substrate 52 according to the present invention. The device substrate 52 is mounted in a frame 58. The members 56 constituting the discharging portions 53 and the channels 55 are connected to the device substrate 52. A contact 59 is provided on the device substrate 52 for receiving signals from a printer, and electric signals as various driving signals are supplied to the device substrate 52 via the contact 59 and the flexible printed wiring board 60.

Fig. 37 is a schematic perspective view of the overall structure of an ink jet printer IJRA in which an ink jet head according to the present invention is mounted. The slide holder HC is engaged with a spiral groove 5004 of a screw shaft 5005, the screw shaft 5005 is rotated via driving force transmission gears 5011 and 5009 interlocked with the forward and reverse rotation of a driving motor 5013 having a positioning pin (not shown), and the slide holder HC is reciprocated in the directions indicated by arrows "a" and "b". Reference numeral 5002 denotes a laminate sheet which is pressed against a plate 5000, and the plate 5000 is a recording medium conveying device which conveys the sheet in the moving direction of the carriage.

Reference numerals

5007 and 5008 denote photo-couplers, and the photo-

couplers

5007 and 5008 are detection means for detecting whether the lever 5006 of the slide holder HC is at a switching position of the rotational direction of the drive motor 5013 and other operation positions. Reference numeral 5016 denotes a support member which supports a cap 5022 covering the front of the recording head, and reference numeral 5015 denotes a suction member which sucks the inside of the cap 5022 to reposition the recording head through an opening 5023 of the cap 5022. Reference numeral 5017 denotes a cleaning plate, and reference numeral 5019 denotes a moving member which enables the cleaning plate 5017 to move in a longitudinal direction, and a main body supporting plate 5018 is supported on the moving member 5019. It goes without saying that an existing cleaning plate can be used for this embodiment in addition to the cleaning plate of the disclosed shape. Also, reference numeral 5012 refers to a joystick for initiating the suck reset. The lever 5012 moves together with the cam 5020, and transmits and controls the driving force from the driving motor 5013 with a known transmission mechanism such as a clutch switching mechanism.

Further, the printer according to the present invention is provided with a controller (not shown) configured with a circuit for supplying an image signal, a drive control signal, and the like to the device substrate 52.

Although the present invention has been described in some detail with a certain degree of particularity with respect to its preferred form, it is to be understood that the invention has been specifically described and illustrated herein without departing from the scope and spirit of the invention.

Claims

1. A manufacturing method of a semiconductor device in which a plurality of electrothermal conversion elements and a plurality of conversion devices that flow electric current through the plurality of electrothermal conversion elements are integrated on a semiconductor substrate of a 1 st conductivity type, the method comprising the steps of:

forming a semiconductor layer of a 2 nd conductivity type on one main surface of a semiconductor substrate of a 1 st conductivity type;

forming a gate insulating film on the semiconductor layer;

forming a gate electrode on the gate insulating film;

doping a 1 st conductive type impurity between two adjacent gate electrodes using the gate electrodes as a mask;

forming a semiconductor region on a portion of the 2 nd conductive type semiconductor layer between the adjacent two gate electrodes by diffusing the 1 st conductive type impurity; and

forming a source region of the 2 nd conductivity type on a surface side of the semiconductor region, and forming a drain region of the 2 nd conductivity type on a surface side of the semiconductor layer of the 2 nd conductivity type, using the gate electrode as a mask.

2. A manufacturing method of a semiconductor device in which a plurality of electrothermal conversion elements and a plurality of conversion devices that cause electric current to flow through the plurality of electrothermal conversion elements are integrated on a semiconductor substrate of a 1 st conductivity type, comprising the steps of:

selectively forming a field insulating film on the semiconductor layer;

forming a gate insulating film on the semiconductor layer;

forming a gate electrode on the gate insulating film and the field insulating film;

forming a source region of the 2 nd conductivity type on a surface side of the semiconductor region using the gate electrode as a mask; and forming a drain region of the 2 nd conductivity type on a surface side of the semiconductor layer of the 2 nd conductivity type using the field insulating film as a mask.

3. The method of manufacture according to claim 1 or 2, further comprising the steps of:

implanting ions of a 1 st conductivity type impurity into at least a channel region between the source region and the semiconductor layer on a surface side of the semiconductor region through the gate electrode after the step of forming the semiconductor region; and

performing a heat treatment to electrically activate the implanted impurities.

4. The method of manufacture according to claim 1 or 2, further comprising the steps of:

performing a heat treatment to electrically activate the implanted impurities,

wherein the ion implantation is ion implantation in which boron ions are implanted with an energy of 100keV or more.

5. The manufacturing method according to claim 1 or 2, wherein:

at least two of the drain regions of the MIS type field effect transistor as a conversion device are connected to one of the electrothermal conversion elements; and

the source regions of the plurality of MIS type field effect transistors are connected together in common.

6. A method of manufacturing a semiconductor device having a plurality of insulated gate field effect transistors arranged in a matrix type, comprising the steps of:

forming a 1 st semiconductor region of a 2 nd conductivity type on one main surface of a 1 st conductivity type semiconductor substrate;

forming a gate insulating film on the 1 st semiconductor region;

forming a plurality of gate electrodes on the gate insulating film;

implanting an impurity of the 1 st conductivity type between two adjacent gate electrodes at a fixed angle to a normal direction of the semiconductor substrate with the two adjacent gate electrodes as a mask while the semiconductor substrate is rotated, and thereafter diffusing the impurity to form a 2 nd semiconductor region of the 1 st conductivity type; and

ion implantation of an impurity is performed at a fixed angle to a normal direction of the semiconductor substrate with the semiconductor substrate rotated, a 2 nd conductivity type source region is formed in the 2 nd semiconductor region with the two gate electrodes as masks, and 2 nd conductivity type drain regions are formed in the two 1 st semiconductor regions with the 2 nd semiconductor region placed therebetween, respectively.

7. A method of manufacturing a semiconductor device having a plurality of insulated gate field effect transistors arranged in a matrix type, comprising the steps of:

selectively forming a field insulating film on the 1 st semiconductor region;

forming a gate insulating film on the 1 st semiconductor region;

implanting an impurity of the 1 st conductivity type between the two gate electrodes at a fixed angle to a normal direction of the semiconductor substrate with the two gate electrodes as masks while the semiconductor substrate is rotated, and thereafter forming a 2 nd semiconductor region of the 1 st conductivity type by diffusing the impurity; and

performing impurity implantation at a fixed angle to a normal direction of the semiconductor substrate with the semiconductor substrate rotated, forming a 2 nd conductivity type source region in the 2 nd semiconductor region with the two gate electrodes as masks, and forming 2 nd conductivity type drain regions in the 1 st semiconductor region with the 2 nd semiconductor region interposed therebetween, respectively, with the field insulating film as a mask.

8. The method of claim 6 or 7, wherein said 2 nd semiconductor region is formed deeper than said 1 st semiconductor region.

9. A method according to claim 6 or 7, wherein a heating resistor element is formed in electrical connection with said drain region.

10. A method of manufacturing a semiconductor device, the method comprising the steps of:

forming a 1 st semiconductor region of a 2 nd conductivity type on a 1 st conductivity type semiconductor substrate including one main surface having a crystal plane orientation inclined with respect to a low-dimensional crystal plane direction;

forming a gate insulating film on the 1 st semiconductor region;

forming a gate electrode on the gate insulating film;

forming a 2 nd semiconductor region by diffusing an impurity after vertically performing particle implantation of the 1 st conductivity type impurity into the semiconductor substrate with the gate electrode as a mask; and

impurity ion implantation is performed perpendicularly to the semiconductor substrate, and a 2 nd conductivity type source region is formed in the 2 nd semiconductor region and a 2 nd conductivity type drain region is formed in the 2 nd semiconductor region, respectively, using the gate electrode as a mask.

11. A method of manufacturing a semiconductor device, the method comprising the steps of:

selectively forming a field insulating film in the 1 st semiconductor region;

forming a gate insulating film in the 1 st semiconductor region;

forming a 2 nd semiconductor region by diffusing an impurity of the 1 st conductivity type after vertically performing ion implantation of the impurity into the semiconductor substrate with the gate electrode as a mask; and

impurity ion implantation is performed perpendicularly to the semiconductor substrate, respectively, with the gate electrode as a mask, a 2 nd conductivity type source region is formed in the 2 nd semiconductor region, and with the field insulating film as a mask, a 2 nd conductivity type drain region is formed in the 2 nd semiconductor region of the 2 nd conductivity type.

12. The method of claim 10 or 11, wherein a crystal plane orientation of said main surface of said semiconductor substrate is inclined at an angle ranging from 3 degrees to 10 degrees with respect to said lower dimensional crystal direction.

13. The method of claim 10 or 11 wherein said crystal plane of said major surface of said semiconductor substrate is oriented at an angle ranging from 3 degrees to 10 degrees relative to the (100) crystal plane.

14. The method of claim 10 or 11 wherein said crystal orientation of said major surface of said semiconductor substrate is tilted at an angle of 4 degrees relative to the (100) crystal plane.

15. The method of claim 10 or 11, wherein said step of forming said 2 nd semiconductor region diffuses said 1 st conductivity type impurity to a position deeper than said 1 st semiconductor region.

16. The method of claim 10 or 11, wherein the plurality of insulated gate field effect transistors are arranged in a matrix type.

17. A semiconductor device in which a plurality of insulated gate field effect transistors are provided in a matrix type, the plurality of insulated gate field effect transistors respectively comprising:

a 1 st semiconductor region of a 2 nd conductivity type formed on a 1 st conductivity type semiconductor substrate including a main surface having a crystal plane orientation inclined with respect to a low-dimensional crystal plane direction;

forming a 2 nd semiconductor region of a 1 st conductivity type for partitioning the 1 st semiconductor region, the 2 nd semiconductor region having an impurity concentration higher than that of the 1 st semiconductor region;

a source region of a 2 nd conductivity type formed in the 2 nd semiconductor region; and

a drain region of a 2 nd conductivity type formed in the 1 st semiconductor region.

18. The semiconductor device of claim 17 wherein said crystal plane orientation of said major surface of said semiconductor substrate is inclined at an angle ranging from 3 degrees to 10 degrees with respect to said lower dimensional crystal direction.

19. The semiconductor device of claim 17 wherein said crystal plane orientation of said major surface of said semiconductor substrate is inclined at an angle ranging from 3 degrees to 10 degrees with respect to the (100) crystal plane.

20. The semiconductor device of claim 17 wherein said crystal plane orientation of said major surface of said semiconductor substrate is inclined at an angle of 4 degrees relative to a (100) crystal plane.

21. The semiconductor device of claim 17 wherein said 2 nd semiconductor region is deeper than said 1 st semiconductor region.

22. A liquid ejection apparatus comprising:

the semiconductor device according to claim 17, which comprises a liquid discharge portion corresponding to an electrothermal conversion element;

a liquid container for containing liquid ejected from the liquid discharge portion through the electrothermal conversion element; and

a controller for providing a driving control signal for driving the insulated gate field effect transistor in the semiconductor device.