CN101442309A - Analog probability same-effect gate circuit designed using CMOS transistor - Google Patents

Abstract

The invention provides a simulated probability equivalent gate circuit designed by utilizing a CMOS device, which mainly comprises a current mirror circuit and an analog multiplier circuit. By utilizing input and output current values to replace input and output probability values, and adopting different structural forms of the circuit to realize the equivalent computation of the probability, the probability equivalent gate circuit can be applied to the computation in an electronic neuron network and the decoding computation of a signal channel in the field of digital communication, and compared with the adoption of the prior digital logic gate circuit, the computation by adopting the probability equivalent gate circuit can be improved by two orders of magnitude in the aspects of speed and power consumption. The circuit is a modular circuit, and can be widely applied to biology, digital communication and other chip design in which the probability computation is needed.

Description

A kind of analog probability same-effect gate circuit that utilizes the CMOS transistor design

The present invention relates to a kind of probability calculation circuit in the integrated circuit (IC) design that is applied to, particularly a kind of analog probability same-effect gate circuit that utilizes the CMOS transistor design.

(technical field)

The present invention relates to Signal and Information Processing and integrated circuit (IC) design field.

(background technology)

In digital communication system,, generally all adopt the error correcting code codec in order to overcome channel disturbance.The decoding of error correcting code has been seen algebraic decoding and probabilistic decoding dual mode from the mathematics angle.Generally all adopt digital circuit to realize error-correcting code decoder from the circuit way of realization.Digital circuit and algebraic decoding are well matched, but implement more complicated for probabilistic decoding with digital circuit.

Realize the decoding of error correcting code with analog circuit, its Fundamentals of Mathematics are probabilistic decoding algorithms, motivation mainly contains following several respects: the one, along with the raising of traffic rate, the error-correcting code decoder of realizing with digital circuit more and more can not satisfy the requirement of speed, need make full use of analog circuit advantage at a high speed; The 2nd, owing to particularly require low-power consumption in the mobile communication in the communication, need to reduce circuit power consumption by novel circuit design.The 3rd, all the time, we know between algebraically encoding and decoding theory and the digital VLSI well matched.General digital circuit (binary storage cell and gate) is suitable for the algebraic operation of finite field.Yet, this be engaged in be similar in the probabilistic decoding technology used in the Veterbi decoding improper.In fact, realize the BCH decoder big considerable chip area of Viterbi decoder at a high speed than identical bit.This situation is more outstanding in Turbo code and loe-density parity-check code.At first, the minimum-sum algorithm in the Veterbi decoding is replaced by sum-product algorithm, particularly is equal to the probability propagation in the Bayesian network, is not suitable for the realization of digital circuit more.Secondly, decoding has iterative process (identical calculating repeats repeatedly), makes and must carry out a lot of operations, realizes very loaded down with trivial details with digital circuit.

Therefore need to consider to realize probabilistic decoding that key is based on suitable algorithm and design units corresponding analog circuit with analog circuit.Sum-product algorithm is suitable for realizing that with simulation VLSI a major advantage of this analog decoder is that iteration has not had that decoder is an asynchronous electric network.

Advantage of the present invention is, designed a kind of analog probability same-effect gate cell circuit that adopts metal-oxide-semiconductor based on sum-product algorithm, utilize the probability gate circuit of this element circuit and other kind can construct Turbo code, convolution trellis code, the analog decoder of similar sign indicating number such as loe-density parity-check code.

Generally speaking, analog circuit is subject to interference of noise to the deviation sensitivity of device, is subjected to Temperature Influence, complex circuit designs.If but make full use of transistorized non-linear, by system design, reach whole accurately, and the inaccuracy of part or individual devices does not influence the accuracy of entire circuit work.Owing to be directly sum-product algorithm to be mapped to transistor circuit, circuit itself has corresponding network, is convenient to modularized design simultaneously, has reduced the design complexity of the LSI realization of analog probability decoder, for the practicability of decoder has been created condition.

(summary of the invention)

Content of the present invention is: the characteristic when utilizing MOS transistor to be in the subthreshold value pattern, design the various probability gate circuits that are used for probability propagation calculating.Logic in probability same-effect door and the digital circuit is corresponding with imitating door, and logic is a voltage signal of representing logical value 0 or 1 with the input and output of imitating door, the probability same-effect door be that input and output are current signals of representing probable value.

Algebraic decoder at first will be the restituted signal that receives (represent the actual waveform signal of 0,1 value, be also referred to as soft bit signal), by decision circuit, ruling out is 0 or 1, exports with voltage form, be called hard bit signal, by various Digital Logical Circuits, decode again.Shortcoming is that judgement the time only utilizes sampled point to adjudicate, and has error, and it is slow to separate (translating) sign indicating number speed, and power consumption is big, and during for the needs iterative decoding, is difficult for realizing with digital circuit.

Probabilistic decoding is directly to utilize the soft bit signal that receives to carry out carrying out probability calculation by the probability door to realize decoding, after decoding is finished, utilizes decision circuit again, rules out hard bit signal, offers the digital circuit of back level.Probabilistic decoding adopts analog circuit to realize, be similar to filter circuit during calculating, speed is fast, and is low in energy consumption, realize easily for iterative computation, and antijamming capability is poor unlike the corresponding digital circuit.

The probability same-effect door can form fixing module, can overcome the loaded down with trivial details drawback of Analog Circuit Design as utilizing logic convenient with effect door design digital circuit when the design decoding circuit.

(embodiment)

The objective of the invention is to be achieved through the following technical solutions: mainly form by electric current input, output circuit and analog multiplier circuit etc.Utilize the big or small representative input of current value of input, output, the probable value of output, realize the same effect calculating of probability by the different structure form of circuit.Utilize the CMOS transistor device, designed the current input circuit of representing X road, Y road, represent the current output circuit on Z road, and utilize current value to carry out the analog circuit that probability same-effect calculates.The probable value that realizes output on function is the same effect result of two-way input probability value.

Advantage of the present invention is:

1. the metal-oxide-semiconductor of analog multiplier unit works in the subthreshold value state, has the indicial response that is similar to the bipolarity triode between the voltage and current.The circuit structure of realizing multiplication is simple, utilizes a metal-oxide-semiconductor just can realize the multiplication relation of two-way electric current.

2. owing to be to utilize single tube to realize that multiplication calculates, when chip design, the chip area that takies is little, designs simply relatively, is convenient to the realization of large scale integrated circuit.

3. when metal-oxide-semiconductor works in the subthreshold value state, operating current is minimum, the power consumption of circuit is extremely low, in the chip design of telecommunication circuit, when particularly the mobile communication circuit chip designs, the meaning with particular importance low in energy consumption, in some occasion, low-power consumption is necessary requirement, reduces the power consumption of complete machine, has great practical value.

4. what the input of the analog probability same-effect gate circuit of the present invention's design, output interface adopted is the inferior current source circuit of Weir, compare with common current source circuit, has higher current replication precision, adopt possible current source circuit designs to be convenient to interconnected between the various probability gate circuits simultaneously, be convenient to design large-scale analog decoder chip circuit.

5. the analog probability same-effect gate circuit of the present invention's design is general analog probability counting circuit, can be widely used in Turbo code, and the convolution trellis code is in the analog decoder design of similar sign indicating number such as loe-density parity-check code.

6. the analog decoder that utilizes analog probability same-effect gate circuit that the present invention designs to realize belongs to soft decision decoder, compares with the Hard decision decoding device that traditional digital circuit realizes, under the condition of identical signal to noise ratio, has the Soft decision decoding gain of 2-3dB.Perhaps under identical decoding gain condition, has the lower error rate.

7. nerve network circuit design at present adopts analog circuit to realize mostly, and the analog probability gate circuit of the present invention's design also can be applicable in the neural network chip design.

(description of drawings)

Further describe below in conjunction with drawings and Examples:

Fig. 1 is a block diagram of the present invention.

The course of work of analog probability same-effect gate circuit of the present invention is: the two-way input is respectively X road and Y road, the input of every road has two ports, with the form of the electric current probable value that to have represented this road signal respectively be logical zero or 1, output circuit is the Z road, two ports are also arranged, represented the probable value that is output as logical zero or 1 with the form of electric current, import four road current signals, utilize the metal-oxide-semiconductor indicial response to realize taking advantage of the relation of adding, make the two-way electric current of output equal the result of calculation of input current respectively, on function, realize the same effect computing of probable value, simultaneously in input, the inferior current source circuit of Weir is adopted in output, be convenient to the cascade with other analog probability gate circuit, can realize the design of large-scale analog codec chip design and other neural network chip.

Fig. 2 is circuit theory diagrams of the present invention.

Symbol description is as follows among the figure:

M1-M6-six NMOS pipe, six multiplication computing units.

M7-M9-three NMOS pipe constitutes the wilson current mirror circuit.

M10-M12-three NMOS pipe constitutes the wilson current mirror circuit.

M13-M15-three PMOS pipe constitutes the wilson current mirror circuit.

M16-M18-three PMOS pipe constitutes the wilson current mirror circuit.

VCC-positive supply

VSS-negative supply

The operating voltage of V1-V4-four point

Operating current on I1-I4-four line

Ix0-X road input information is 0 probability current value

Ix1-X road input information is 1 probability current value

Iy0-Y road input information is 0 probability current value

Iy1-Y road input information is 1 probability current value

Iz0-Z road output information is 0 probability current value

Iz1-Z road output information is 1 probability current value

In Fig. 2, M ₁-M ₆Six NMOS pipe constitutes six multiplication computing units, all is to be operated in the subthreshold value state, so its electric current, voltage have following exponential relationship:

$I_D=I_{D0}\left(\frac{W}{L}\right)e^{-V_{\mathrm{BS}}[(1-n{V}_{\mathrm{th}})-(1/V_{\mathrm{th}})]}\·[1-e^{-V_{\mathrm{DS}}/V_{\mathrm{th}}}]\·e^{(V_{\mathrm{GS}}-V_T)/n{V}_{\mathrm{th}}}---\left(1\right)$

V in the formula _TBe threshold voltage, V _Th=KT/q, I _D0With constant n be technological parameter, its representative value is respectively I _D0≈ 20nA, n ≈ 1.5.In formula (1), work as V _DS3V _ThThe time,

Item can be ignored.Make V _BS=0, then formula (1) can be reduced to:

$I_D=I_{D0}\left(\frac{W}{L}\right)e^{(V_{\mathrm{GS}}-V_T)/n{V}_{\mathrm{th}}}---\left(2\right)$

According to formula (2) and Fig. 2 as can be known:

${\mathrm{<figure-callout\; id="1"\; label="I"\; filenames="A200710187961E00091.png"\; state="\{\{state\}\}">I</figure-callout>}}_1=I_{D01}\left(\frac{W_1}{L_1}\right)e^{((V_1-V_2)-V_{T1})/n{V}_{\mathrm{th}}}---\left(3\right)$

$I_2=I_{D02}\left(\frac{W_2}{L_2}\right)e^{((V_4-V_2)-V_{T2})/n{V}_{\mathrm{th}}}---\left(4\right)$

$I_3=I_{D03}\left(\frac{W_3}{L_3}\right)e^{((V_1-V_3)-V_{T3})/n{V}_{\mathrm{th}}}---\left(5\right)$

$I_4=I_{D04}\left(\frac{W_4}{L_4}\right)e^{((V_4-V_3)-V_{T4})/n{V}_{\mathrm{th}}}---\left(6\right)$

When design, make M ₁With M ₂, M ₃With M ₄Have identical technological parameter and breadth length ratio, that is:

I _D01＝I _D02，I _D03＝I _D04， $\frac{W_1}{{\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="A200710187961E00091.png"\; state="\{\{state\}\}">L</figure-callout>}}_1}=\frac{W_2}{L_2},$ $\frac{W_3}{L_3}=\frac{W_4}{L_4},$ V _T1=V _T2, V _T3=V _T4, then:

$\frac{I_1}{I_{x0}}=\frac{I_1}{{\mathrm{<figure-callout\; id="1"\; label="I"\; filenames="A200710187961E00091.png"\; state="\{\{state\}\}">I</figure-callout>}}_1+I_2}=\frac{e^{((V_1-V_2)-V_{T1})/n{V}_{\mathrm{th}}}}{e^{((V_1-V_2)-V_{T1})/n{V}_{\mathrm{th}}}+e^{((V_4-V_2)-V_{T2})/\mathrm{nVth}}}=\frac{{\mathrm{<figure-callout\; id="1"\; label="e\; V"\; filenames="A200710187961E00091.png"\; state="\{\{state\}\}">e</figure-callout>}}^{V_{}}}{e^{V_{}}}---\left(7\right)$

$\frac{I_{y0}}{I_{y0}+{\mathrm{<figure-callout\; id="1"\; label="I\; y"\; filenames="A200710187961E00091.png"\; state="\{\{state\}\}">I</figure-callout>}}_y}=\frac{e^{((V_1-0)-V_{T5})/n{V}_{\mathrm{th}}}}{e^{((V_1-0)-V_{T5})/n{V}_{\mathrm{th}}}+e^{((V_4-0)-V_{T6})/n{V}_{\mathrm{th}}}}=\frac{{\mathrm{<figure-callout\; id="1"\; label="e\; V"\; filenames="A200710187961E00091.png"\; state="\{\{state\}\}">e</figure-callout>}}^{V_{}}}{e^{V_{}}}---\left(8\right)$

Relatively (7), (8) are as can be known:

$\frac{I_1}{I_{x0}}=\frac{I_{y0}}{I_{y0}+I_{y1}}---\left(9\right)$

That is: $I_1=\frac{I_{x0}{I}_{y0}}{I_{y0}+I_{y1}}---\left(10\right)$

In like manner can get: $I_4=\frac{I_{x1}{I}_{y1}}{I_{y0}+I_{y1}}---\left(11\right)$

$I_{z0}=I_1=\frac{I_{x0}{I}_{y0}}{I_{y0}+I_{y1}}---\left(12\right)$

${\mathrm{<figure-callout\; id="1"\; label="I\; z"\; filenames="A200710187961E00091.png"\; state="\{\{state\}\}">I</figure-callout>}}_z=I_4=\frac{I_{x1}{I}_{y1}}{I_{y0}+I_{y1}}---\left(13\right)$

And as shown in Figure 2: I _Z0+ I _Z1=I _X0+ I _X1(14)

The both sides of (12) formula all divided by following formula, are obtained:

$\frac{I_{z0}}{I_{z0}+{\mathrm{<figure-callout\; id="1"\; label="I\; z"\; filenames="A200710187961E00091.png"\; state="\{\{state\}\}">I</figure-callout>}}_z}=\left(\frac{I_{x0}}{I_{x0}+I_{x1}}\right)\left(\frac{I_{y0}}{I_{y0}+I_{y1}}\right)---\left(15\right)$

If: I _z=I _Z0+ I _Z1, I _x=I _X0+ I _X1, I _y=I _Y0+ I _Y1I then _z=I _x, the substitution following formula:

$\frac{I_{z0}}{I_z}=\left(\frac{I_{x0}}{I_x}\right)\left(\frac{I_{y0}}{I_y}\right)---\left(16\right)$

According to the knowledge of probability theory, can establish: $p(z=0)=\frac{I_{z0}}{I_z}$ (probability of expression z=0), $p(x=0)=\frac{I_{x0}}{I_x},$

$p(y=0)=\frac{I_{y0}}{I_y},$ $p(x=1)=\frac{I_{x1}}{I_x},$ Substitution (17) Shi Kede:

p(z＝0)＝p(x＝0)p(y＝0) (17)

In like manner can from (13), draw: p (z=1)=p (x=1) p (y=1) (18)

Claim that (17), (18) formula are probability same-effect door formula, input and output are the probable values (being the nonnegative real number less than 1) with the current forms performance.Three NMOS pipes of M7-M9 and M10-M12, M13-M15, M16-M18 constitute four groups of wilson current mirror circuit respectively, constitute analog probability same-effect gate circuit in input.Employing wilson current mirror circuit not only is convenient to the cascade between the various probability gate circuits, and compares with simple two tube current mirrors, can improve the current replication precision of current mirror, has stronger circuit antijamming capability.

VCC is a positive supply, and voltage is 5V or 3V.

Claims (5)

1. one kind is called the analog probability same-effect gate circuit that utilizes CMOS (complementation-Metal-oxide-semicondutor) designs.Mainly form by electric current input, output circuit and analog multiplier circuit etc.Utilize the current value size representative input of input, output, the probable value of output, realize the Equivalent Calculation of probability by the different structure form of circuit.It is characterized in that: utilize the CMOS transistor device, designed the current input circuit of representing X road, Y road, represent the current output circuit on Z road, and utilize current value to carry out the analog circuit that probability same-effect calculates.The probable value that realizes output on function is the equivalent result of two-way input probability value.The logic that in form is similar in the digital circuit is imitated door together.But the two has the difference of essence, and the input/output signal of probability same-effect door is a current signal of representing probable value, and numeral is a voltage signal of representing logical value 0 or 1 with the input and output of imitating door.The probability same-effect door can be widely used in that electronic neuron network calculates and digital communicating field in channel-decoding calculate and other needs in the chip design of probability calculation, be modular circuit structure, be convenient to design and cascade.Utilize the characteristic of analog circuit to realize probability calculation,, can improve two orders of magnitude on the speed or on the power consumption than adopting digital circuit.

2. the analog probability same-effect gate circuit that utilizes the cmos device design according to claim 1 is characterized in that: imput output circuit adopts the wilson current mirror circuit, not only makes the accuracy of repetition height of electric current, has improved the antijamming capability of circuit simultaneously.

3. the analog probability same-effect gate circuit that utilizes the cmos device design according to claim 1, it is characterized in that: utilize the CMOS transistor to be operated in the characteristic of subthreshold value state, realized novel analog multiplier circuit, the CMOS transistor of employing is few, operating current is minimum, and circuit power consumption is little.

4. the analog probability same-effect gate circuit that utilizes cmos device design according to claim 1 is characterized in that: used additional calculation during the probability equivalent operation, adopt the mode of electric current line and addition, and not only reduced device, and circuit working is reliable and stable.

5. the analog probability same-effect gate circuit that utilizes the cmos device design according to claim 1, it is characterized in that: this circuit with other probability gate circuit cascade the time, adopts current mirror cascade mode as modularized circuit, simple and convenient, be convenient to the design of large scale integrated circuit.

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