CN101431328A - Not gate logic circuit and forming method thereof - Google Patents
Not gate logic circuit and forming method thereof Download PDFInfo
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- CN101431328A CN101431328A CNA200810227459XA CN200810227459A CN101431328A CN 101431328 A CN101431328 A CN 101431328A CN A200810227459X A CNA200810227459X A CN A200810227459XA CN 200810227459 A CN200810227459 A CN 200810227459A CN 101431328 A CN101431328 A CN 101431328A
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- 238000000034 method Methods 0.000 title claims abstract description 39
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims abstract description 187
- 230000005669 field effect Effects 0.000 claims abstract description 49
- 239000000463 material Substances 0.000 claims abstract description 14
- 238000005516 engineering process Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 26
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- 230000015572 biosynthetic process Effects 0.000 claims description 18
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- 239000002070 nanowire Substances 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 11
- NTIZESTWPVYFNL-UHFFFAOYSA-N Methyl isobutyl ketone Chemical compound CC(C)CC(C)=O NTIZESTWPVYFNL-UHFFFAOYSA-N 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 238000012546 transfer Methods 0.000 claims description 6
- 230000000737 periodic effect Effects 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
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- 230000003287 optical effect Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000008878 coupling Effects 0.000 abstract 1
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- 239000011787 zinc oxide Substances 0.000 description 66
- 239000007789 gas Substances 0.000 description 7
- 239000002086 nanomaterial Substances 0.000 description 7
- 238000011160 research Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000002708 enhancing effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
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- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005622 photoelectricity Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
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- 239000002071 nanotube Substances 0.000 description 1
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Abstract
The invention relates to a NOT gate logic circuit and a forming method thereof. The NOT gate logic circuit comprises: an input terminal for receiving an input voltage signal; the gate electrode of the enhanced back gate zinc oxide nanowire field effect transistor is coupled to the input end, and the source electrode of the enhanced back gate zinc oxide nanowire field effect transistor is coupled to the grounding point; and the drain electrode of the depletion type back gate zinc oxide nanowire field effect transistor is coupled to a voltage source, and the gate electrode, the source electrode and the drain electrode of the enhancement type back gate zinc oxide nanowire field effect transistor are coupled to one point, and the point is used as an output end for outputting a voltage signal. The invention realizes the NOT gate logic circuit of the direct coupling field effect logic based on the zinc oxide nanowire field effect transistor by utilizing the zinc oxide nanowire material, the zinc oxide nanowire field effect transistor manufacturing technology and the interconnection technology.
Description
Technical field
The present invention relates to compound semiconductor materials and devices field, especially relate to NOT gate logic circuit of the direct coupled field effect logic (Direct-coupled FET Logic is called for short DCFL) based on back gate zinc oxide nanowire field effect transistor and forming method thereof.
Background technology
ZnO is the Multifunction compound semiconductor materials of a kind of II-VI family direct band gap, is called as third generation semiconductor material with wide forbidden band.ZnO crystal is a wurtzite structure, and energy gap is about 3.37eV, and exciton bind energy is about 60meV.ZnO possesses characteristics such as semiconductor, photoelectricity, piezoelectricity, thermoelectricity, air-sensitive and electrically conducting transparent, at numerous areas such as sensing, sound, light, electricity wide potential using value is arranged.
In recent years, the research to ZnO material and device is subjected to extensive concern.Research range has contained growth and characteristic and ZnO transducer, transparency electrode, piezo-resistance, solar cell window, surface acoustic wave device, detector and the light-emitting diode preparation of devices and the research aspects such as (Light-emitting Diodes, abbreviation LED) of materials such as ZnO body monocrystalline, film, quantum wire, quantum dot.At present, form the growth that several different methods is used for the ZnO material, and developed the ZnO device and the transducer of some kinds, but the growth of P type ZnO material, and problems such as the preparation of ZnO nano-device and application still need deeply and systematic research.
ZnO has nanostructure and the abundantest material of characteristic at present, and the nanostructure that has realized comprises nano wire, nano belt, nano-rings, nano-comb, nanotube or the like.Wherein, one-dimensional nano line is owing to the granular of material, and specific area increases, and has the not available skin effect of conventional body material, small-size effect, quantum effect and macro quanta tunnel effect, and crystal mass is better, and the transport performance of charge carrier is more superior.One-dimensional nano line not only can be realized basic nanoscale components and parts (as laser, transducer, field-effect transistor, light-emitting diode, logic, spin electric device and quantum computer etc.), and can also be used for connecting various nano-devices, be expected on single nano wire, to realize having electronics, photon and the spin information processing device of sophisticated functions.
ZnO nano-wire field effect transistor (Nanowire Field-Effect Transistor, abbreviation NWFET) has become one of focus of international research.The ZnO one-dimensional nano line can form metal-oxide semiconductor fieldeffect transistor (Metal-Oxide-SemiconductorField-Effect Transistor, abbreviation MOSFET) as raceway groove with grid oxygen and grid metal.Because the electric property of ZnO nano wire changes with the change of forming gas in the surrounding atmosphere, such as unadulterated ZnO reproducibility, oxidizing gas is had superior sensitiveness, therefore can detect and quantitative test corresponding gas.This makes ZnO one-dimensional nano line field-effect transistor can be used for gas, humidity and chemical sensor, photoelectricity and ultraviolet detector, memory applications such as (Memory).Especially can survey toxic gas (as CO, NH3 etc.),, can detect the composition and the concentration of gas by the mutual conductance variation of field-effect transistor.Compare with conventional SnO2 gas sensor, it is little to have size based on the gas sensor of ZnO nano-wire field effect transistor, and cost is low, advantage such as can reuse.
In sum, the development of ZnO nano-wire field effect transistor has important research and using value aspect nanoelectronics and the novel nano transducer, will play important impetus to development and national economy.
The research that helps opening up nano-device and circuit and application thereof based on the logic unit circuit of nano material and device.But because intrinsic ZnO is N type semiconductor, and the ZnO NW FET that makes mostly is depletion device, restricted to utilize the ZnO nano-material to realize logic circuit application based on enhancing/depletion type FET.
Summary of the invention
Realizing based on the limitation aspect the logic circuit application of enhancings/depletion type FET in order to overcome the ZnO nano-material, the invention provides a kind of NOT gate logic circuit based on the direct coupled field effect logic of carrying on the back grid ZnO nano-wire field effect transistor and forming method thereof.
A kind of NOT gate logic circuit, comprising: an input is used to receive input voltage signal; One enhancement type back grid zinc oxide nano wire field effect transistor, its gate electrode is coupled to described input, and its source electrode is coupled to earth point; One depletion type back gate zinc oxide nanowire field effect transistor, its drain electrode is coupled to voltage source, the drain electrode of its gate electrode, its source electrode and described enhancement type back grid zinc oxide nano wire field effect transistor is coupled to a bit, as output, is used for output voltage signal with this point.
A kind of NOT gate logic circuit formation method, this NOT gate logic circuit comprise an enhancement type back grid zinc oxide nano wire field effect transistor and a depletion type back gate zinc oxide nanowire field effect transistor; Wherein, this formation method comprises: the gate electrode of described enhancement type back grid zinc oxide nano wire field effect transistor is used to receive input voltage signal as the input of this NOT gate logic circuit; The source electrode of described enhancement type back grid zinc oxide nano wire field effect transistor is coupled to earth point; The drain electrode of described depletion type back gate zinc oxide nanowire field effect transistor is coupled to voltage source; The drain electrode of the gate electrode of described depletion type back gate zinc oxide nanowire field effect transistor, source electrode and described enhancement type back grid zinc oxide nano wire field effect transistor is coupled to a bit, with the output of this point, be used for output voltage signal as this NOT gate logic circuit.
NOT gate logic circuit provided by the invention and forming method thereof, one enhancement type back grid ZnO NW FET and depletion type back of the body grid ZnO NW FET are effectively connected based on DCFL, overcome the ZnO nano-material and realized having realized purpose based on the DCFL not gate logical block of ZnO NW FET based on the limitation aspect the logic circuit application of enhancing/depletion type FET.
Description of drawings
Fig. 1 is the structural representation of a kind of NOT gate logic circuit of the present invention;
Fig. 2 is the structural representation of depletion type back of the body grid ZnO NW FET or enhancement type back grid ZnO NW FET in a kind of NOT gate logic circuit of the present invention;
Fig. 3 is a flow process schematic diagram of a kind of NOT gate logic circuit of the present invention formation method;
Fig. 4 is another schematic flow sheet of a kind of NOT gate logic circuit of the present invention formation method;
Fig. 5 is the flow chart that step 101 is made depletion type back of the body grid ZnO NW FET among Fig. 4;
Fig. 6 is the flow chart that step 102 is made enhancement type back grid ZnO NW FET among Fig. 4;
The transfer characteristic curve of the ZnO NW FET device among Fig. 7 Fig. 6 after the annealing in process.
Embodiment
Fig. 1 is the structural representation of a kind of NOT gate logic circuit of the present invention.This NOT gate logic circuit comprises an input, is used to receive input voltage signal Vin; One enhancement type back grid ZnO NW FET 100, its gate electrode G1 is coupled to input, and its source electrode S1 is coupled to earth point; And a depletion type back of the body grid ZnONW FET 200, its drain electrode D2 is coupled to voltage source, and (voltage source is DC power supply V among Fig. 1
DD), the drain electrode D1 of its gate electrode G2, its source electrode S2 and enhancement type back grid ZnO NW FET 100 is coupled to 1 A, as output, is used for output voltage signal Vout with this A.
Because the gate electrode G2 of depletion type back of the body grid ZnO NW FET 200 links to each other with source electrode S2, make that the gate voltage of depletion type back of the body grid ZnO NW FET 200 is zero volt, threshold voltage (threshold voltage of depletion type back of the body grid ZnO NW FET 200 is a negative voltage) greater than depletion type back of the body grid ZnO NW FET200, so depletion type back of the body grid ZnO NW FET 200 is in normally open, when the input voltage signal Vin of input is an electronegative potential, during promptly less than the threshold voltage (threshold voltage of enhancement type back grid ZnONW FET 100 is a positive voltage) of enhancement type back grid ZnO NW FET 100, enhancement type back grid ZnO NW FET 100 is in cut-off state, and this moment, the output terminals A point was in high potential.When input end signal Vin magnitude of voltage is a high potential, during promptly greater than the threshold voltage of enhancement type ZnO NW FET 100, enhancement type ZnO NW FET 100 is in opening, and this moment, the output terminals A point was in electronegative potential.As can be seen, the current potential of the current potential of input end signal Vin and output end signal Vout is in rp state, thereby forms DCFL not gate logic unit circuit.
Wherein depletion type is carried on the back grid ZnO NW FET or enhancement type back grid ZnO NW FET, comprises as shown in Figure 2:
Grid oxygen medium SiO
2, utilize PECVD (plasma enhanced chemical vapor deposition) to grow in the front of P+-Si substrate;
Back-gate electrode is formed at the back side of P+-Si substrate by evaporated metal;
The cross telltale mark of periodic arrangement of rule by photoetching telltale mark figure, evaporated metal, stripping metal successively, is formed at the front of P+-Si substrate;
Zinc oxide nanowire is positioned over the front of P+-Si substrate;
Source-drain electrode (being source electrode, drain electrode among Fig. 2) is by photolithographic source drain electrode figure, evaporated metal, stripping metal form successively.
Wherein enhancement type back grid ZnO NW FET carries out annealing in process again on above-mentioned technology basis, and under 600 ℃ of environment, annealing in process 2min makes script less than zero threshold voltage that lies prostrate, and positive excursion forms the enhancement mode threshold voltage that lies prostrate greater than zero.
Fig. 3 is a flow process schematic diagram of a kind of NOT gate logic circuit of the present invention formation method.This NOT gate logic circuit comprises an enhancement type back grid zinc oxide nano wire field effect transistor and a depletion type back gate zinc oxide nanowire field effect transistor.This formation method comprises:
The gate electrode of step 10, enhancement type back grid ZnO NW FET is used to receive input voltage signal as the input of this NOT gate logic circuit;
The source electrode of step 20, enhancement type back grid ZnO NW FET is coupled to earth point;
The drain electrode of step 30, depletion type back of the body grid ZnO NW FET is coupled to voltage source;
The drain electrode of gate electrode, source electrode and the described enhancement type back grid ZnO NW FET of step 40, depletion type back of the body grid ZnO NW FET is coupled to a bit, with the output of this point as this NOT gate logic circuit, is used for output voltage signal.
NOT gate logic circuit formation method of the present invention is not limited to the realization order of above-mentioned steps 10-40, and step 10-40 is the transposing order arbitrarily.
Fig. 4 is another schematic flow sheet of a kind of NOT gate logic circuit of the present invention formation method.The embodiment of Fig. 3 and Fig. 4 correspondence is also to comprise with respect to the difference of the embodiment of Fig. 3 and Fig. 3 correspondence:
NOT gate logic circuit formation method of the present invention is not limited to the realization order of above-mentioned steps 101, step 102, and step 101 and step 102 be the transposing order arbitrarily.
Fig. 5 is the flow chart that step 101 is made depletion type back of the body grid ZnO NW FET among Fig. 4.
The making of step 1, grid oxygen medium.Utilize PECVD at the front of P+-Si substrate growth grid oxygen medium SiO2, finish the making of the grid oxygen medium of back of the body grid ZnO nano-wire field effect transistor.
The making of step 2, back-gate electrode.At the back side of P+-Si substrate evaporated metal, form back-gate electrode.
The transfer of step 4, nano wire and deposition.The zinc-oxide nano wire material is soaked in the isopropyl acetone solution, adopts the ultrasonotomography technology, zinc oxide nanowire is come off from the growth substrates surface, be suspended in isopropyl acetone solution; And the isopropyl acetone drips of solution that will contain zinc oxide nanowire is finished the transfer and the deposit of zinc oxide nanowire in the front of P+-Si substrate.
The location of step 5, nano wire.Observe zinc oxide nanowire, utilize cross telltale mark, the accurate position of zinc oxide nanowire is provided for the subsequent optical carving technology.
The making of step 6, source-drain electrode.Photolithographic source drain electrode figure, evaporated metal, stripping metal form source-drain electrode in the front of P+-Si substrate successively.
Fig. 6 is the flow chart that step 102 is made enhancement type back grid ZnO NW FET among Fig. 4.The making flow process of enhancement type back grid ZnO NW FET is similar to the making flow process of depletion type back of the body grid ZnO NW FET, and difference is that source-drain electrode also need carry out annealing in process after making.Fig. 6 also comprises with respect to Fig. 5:
Step 7, annealing in process.Source-drain electrode also need carry out annealing in process after making, and promptly whole wafer (wafer) is annealed, and makes the threshold voltage of ZnO NW FET device move to forward, realizes the enhancement mode threshold voltage greater than zero volt, thereby obtains enhancement type back grid ZnO NW FET.Under 600 ℃ of environment, annealing in process 2min makes script less than zero threshold voltage that lies prostrate, and positive excursion forms the enhancement mode threshold voltage that lies prostrate greater than zero.
Fig. 7 is the transfer characteristic curve of the ZnO NW FET device after the annealing in process among Fig. 6, and it characterizes the source-drain current change curve of ZnO NW FET device under different gate voltage effects.Simultaneously, the threshold voltage of ZnO NWFET device also thus curve obtain, from this figure as can be seen, as gate voltage Vgs during less than 0V, source-drain current Ids is minimum, after gate voltage Vgs is greater than 0V, source-drain current Ids increases gradually, and the threshold voltage of device is an enhancement mode as can be known.
The present invention utilizes ZnO nano-material and ZnO NW FET element manufacturing technology and interconnection technique, realizes the DCFL NOT gate logic circuit based on ZnO NW FET.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (7)
1, a kind of NOT gate logic circuit is characterized in that, comprising:
One input is used to receive input voltage signal;
One enhancement type back grid zinc oxide nano wire field effect transistor, its gate electrode is coupled to described input, and its source electrode is coupled to earth point;
One depletion type back gate zinc oxide nanowire field effect transistor, its drain electrode is coupled to voltage source, the drain electrode of its gate electrode, its source electrode and described enhancement type back grid zinc oxide nano wire field effect transistor is coupled to a bit, as output, is used for output voltage signal with this point.
2, NOT gate logic circuit according to claim 1 is characterized in that, described depletion type back gate zinc oxide nanowire field effect transistor or enhancement type back grid zinc oxide nano wire field effect transistor comprise:
Grid oxygen medium SiO
2, utilize PECVD to grow in the front of P+-Si substrate;
Back-gate electrode is formed at the back side of P+-Si substrate by evaporated metal;
The cross telltale mark of periodic arrangement of rule by photoetching telltale mark figure, evaporated metal, stripping metal successively, is formed at the front of P+-Si substrate;
Zinc oxide nanowire is positioned over the front of P+-Si substrate;
Source-drain electrode is formed at the front of P+-Si substrate by photolithographic source drain electrode figure, evaporated metal, stripping metal successively;
Wherein said enhancement type back grid zinc oxide nano wire field effect transistor carries out annealing in process again on above-mentioned technology basis, under 600 ℃ of environment, annealing in process 2min, make script less than zero threshold voltage that lies prostrate, positive excursion forms the threshold voltage that lies prostrate greater than zero.
3, a kind of NOT gate logic circuit formation method, this NOT gate logic circuit comprise an enhancement type back grid zinc oxide nano wire field effect transistor and a depletion type back gate zinc oxide nanowire field effect transistor; It is characterized in that this formation method comprises:
The gate electrode of described enhancement type back grid zinc oxide nano wire field effect transistor is used to receive input voltage signal as the input of this NOT gate logic circuit;
The source electrode of described enhancement type back grid zinc oxide nano wire field effect transistor is coupled to earth point;
The drain electrode of described depletion type back gate zinc oxide nanowire field effect transistor is coupled to voltage source;
The drain electrode of the gate electrode of described depletion type back gate zinc oxide nanowire field effect transistor, source electrode and described enhancement type back grid zinc oxide nano wire field effect transistor is coupled to a bit, with the output of this point, be used for output voltage signal as this NOT gate logic circuit.
4, NOT gate logic circuit formation method according to claim 3 is characterized in that, also comprises:
Make the step of depletion type back gate zinc oxide nanowire field effect transistor.
5, NOT gate logic circuit formation method according to claim 4 is characterized in that, the step of described making depletion type back gate zinc oxide nanowire field effect transistor comprises:
Utilize PECVD at the front of P+-Si substrate growth grid oxygen medium SiO
2
At the back side of P+-Si substrate evaporated metal, form back-gate electrode;
Carry out photoetching telltale mark figure, evaporated metal, stripping metal in the front of P+-Si substrate successively, the cross telltale mark of the periodic arrangement of formation rule;
The zinc-oxide nano wire material is soaked in the isopropyl acetone solution, adopts the ultrasonotomography technology, nano wire is come off from the growth substrates surface, be suspended in isopropyl acetone solution; And the isopropyl acetone drips of solution that will contain zinc oxide nanowire is finished the transfer and the deposit of zinc oxide nanowire in the front of P+-Si substrate;
Observe zinc oxide nanowire, utilize cross telltale mark, the accurate position of zinc oxide nanowire is provided for the subsequent optical carving technology;
Photolithographic source drain electrode figure, evaporated metal, stripping metal form source-drain electrode in the front of P+-Si substrate successively.
6, NOT gate logic circuit formation method according to claim 3 is characterized in that, also comprises:
Make the step of enhancement type back grid zinc oxide nano wire field effect transistor.
7, NOT gate logic circuit formation method according to claim 6 is characterized in that, the step of described making enhancement type back grid zinc oxide nano wire field effect transistor comprises:
Utilize PECVD at the front of P+-Si substrate growth grid oxygen medium SiO
2
At the back side of P+-Si substrate evaporated metal, form back-gate electrode;
Carry out photoetching telltale mark figure, evaporated metal, stripping metal in the front of P+-Si substrate successively, the cross telltale mark of the periodic arrangement of formation rule;
The zinc-oxide nano wire material is soaked in the isopropyl acetone solution, adopts the ultrasonotomography technology, nano wire is come off from the growth substrates surface, be suspended in isopropyl acetone solution; And the isopropyl acetone drips of solution that will contain zinc oxide nanowire is finished the transfer and the deposit of zinc oxide nanowire in the front of P+-Si substrate;
Observe zinc oxide nanowire, utilize cross telltale mark, the accurate position of zinc oxide nanowire is provided for the subsequent optical carving technology;
Photolithographic source drain electrode figure, evaporated metal, stripping metal form source-drain electrode in the front of P+-Si substrate successively;
Annealing in process.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011014129A1 (en) * | 2009-07-31 | 2011-02-03 | Agency For Science, Technology And Research | A transistor arrangement and a method of forming a transistor arrangement |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011014129A1 (en) * | 2009-07-31 | 2011-02-03 | Agency For Science, Technology And Research | A transistor arrangement and a method of forming a transistor arrangement |
| US8963118B2 (en) | 2009-07-31 | 2015-02-24 | Agency For Science, Technology And Research | Transistor arrangement and a method of forming a transistor arrangement |
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