CN101425866A

CN101425866A - CPU visits and controls the device of a plurality of MSA300 optical modules

Info

Publication number: CN101425866A
Application number: CNA2007101659016A
Authority: CN
Inventors: 崔平
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2007-10-31
Filing date: 2007-10-31
Publication date: 2009-05-06

Abstract

The invention discloses the device that a kind of CPU visited and controlled a plurality of MSA300 optical modules, comprise: CPU and at least one MSA300 optical module, described CPU is connected with described MSA300 optical module respectively by data wire, also comprise programmable logic device, described CPU is connected with described programmable logic device with system bus by clock line, and described CPU connects the clock line of described MSA300 optical module by the system bus gating; Described programmable logic device is connected with described MSA300 optical module respectively by clock line.Among the present invention, can visit in a plurality of MSA300 optical modules any one exactly by CPU, control is simple; When the number of MSA300 optical module changes, by adjusting the logic of programmable logic device, just can meet the demands, design very flexible.

Description

CPU visits and controls the device of a plurality of MSA300 optical modules

Technical field

The present invention relates to a kind of optical communication technique, specifically, relate to the device that a kind of CPU visited and controlled a plurality of MSA300 optical modules.

Background technology

10Gb/s SDH (Synchronous Digital Hierarchy) (Synchronous Digital Hierarchy, SDH) and high density partial wave multiplex (MUX) (Dense Wavelength Division Multiplexing, DWDM) trunk project is also served in system's commercialization in a large number, both at home and abroad there has been More and more factories that the optical module product of 10Gb/s can be provided, and defer to 10Gb/s MSA agreement: MSA300 PIN agreement more.

The MSA300 agreement in the industry cycle is called the multi-source tunneling.Defined the definition of 300 pin of 10G transmission and receiver module respectively.Satisfy the optical module ZXOM64 10Gb/s transmitting-receiving unification optical module of such agreement, receiving unit is with the light signal process opto-electronic conversion and the timing regeneration of 9.953Gb/s, 10.66Gb/s, 10.3125Gb/s or 10.709Gb/s speed, through the low speed signal of telecommunication of tap output 16bit 622Mb/s or respective rate, interface level is LVDS again; Sending part is the 622Mb/s of LVDS or the low speed signal of telecommunication of respective rate with the 16bit interface level, be multiplexed to the signal of telecommunication of 9.953Gb/s, 10.66Gb/s, 10.3125Gb/s or 10.709Gb/s speed, through the electric light conversion, the light signal of index request is satisfied in output again.

Along with the increase of level of integrated system, the situation of a plurality of optical modules has appearred visiting simultaneously and controlling.MSA300 provides the I with the outer CPU communication ²C interface, but I ²C has only clock and data wire, lacks address wire, can not realize visit and control to a plurality of optical modules in system.

Summary of the invention

Technical problem solved by the invention provides a kind of CPU visit and controls the device of a plurality of MSA300 optical modules, can correctly visit the optical module of a plurality of MSA300 of satisfying agreements.

Technical scheme is as follows:

A kind of CPU visits and controls the device of a plurality of MSA300 optical modules, comprise: CPU and at least one MSA300 optical module, described CPU is connected with described MSA300 optical module respectively by data wire, also comprise programmable logic device, described CPU is connected with described programmable logic device with system bus by clock line, and described CPU connects the clock line of described MSA300 optical module by the system bus gating; Described programmable logic device is connected with described MSA300 optical module respectively by clock line.

Preferably, the clock line of the data wire of described CPU and MSA300 optical module and programmable logic device and described MSA300 optical module passes through I ²The C protocol interface is connected.

Preferably, described programmable logic device is a CPLD, and described CPLD is provided with at least one register, and described register is by corresponding with the described clock line respectively connection of switching logic; Described CPU carries out read-write operation by system bus to described register, controls the effective status of described clock line by described switching logic.

Preferably, when the content in the described register was logical zero, the clock line of described correspondence was in disarmed state; When the content in the described register was logical one, the clock line of described correspondence was in effective status; When the content in described a plurality of registers all was logical zero, all clock lines all were in closed condition.

Preferably, described data wire is I ²CSDA, described clock line are I ²CSCL.

Beneficial effect

1, by this method, can visit in a plurality of MSA300 optical modules any one exactly by CPU, control is simple; When the number of MSA300 optical module changes, by adjusting the logic of programmable logic device, just can meet the demands, design very flexible.

2, circuit is realized simple.

General CPU and programmable logic device all can be realized this circuit.If have I ²C interface can directly pass through I ²C interface visit MSA300 optical module; If there is not I ²C interface can be by the simulation of IO interface, so the resource that logic takies seldom, general programmable logic device can be realized.

3, flexible design.

When MSA300 optical module number changes, can meet the demands by the logic of adjusting programmable logic device.

Description of drawings

Fig. 1 visits and controls the structural representation of the device of a plurality of MSA300 optical modules for CPU in the embodiment of the invention;

Fig. 2 is the control logic schematic diagram of complex programmable device in the embodiment of the invention.

Embodiment

In the technical solution of the present invention, with the I of CPU ²The clock line of C interface is connected to a programmable logic device, makes this programmable logic device export a plurality of clock lines; A plurality of clock lines of output are connected one to one with above-mentioned a plurality of MSA300 optical modules to be visited.CPU controls this a plurality of clock lines by system bus (address/data/control bus), and making only has a clock lines effective at synchronization, thereby makes CPU at a time visit the MSA300 optical module that is connected with this efficient clock line.

A plurality of registers are arranged in the above-mentioned programmable logic device, these a plurality of registers are by the corresponding connection with a plurality of clock lines of switching logic, CPU carries out read-write operation by system bus to these a plurality of registers, by the effective status of described a plurality of clock lines of switching logic control.When the content in the register was logical zero, corresponding clock line was in disarmed state; When the content in the register was logical one, corresponding clock line was in effective status.When the content in a plurality of registers all was logical zero, all clock lines all were in closed condition, so that CPU conducts interviews to other devices.

By this said method, can visit any one of a plurality of MSA300 optical modules exactly by CPU; When the number of MSA300 optical module changes, just can meet the demands by the logic of adjusting programmable logic device.

With reference to the accompanying drawings, the preferred embodiments of the present invention are described in detail.

With reference to shown in Figure 1, in application example of the present invention, relate to device and comprise CPU, CPLD (CPLD), and a plurality of MSA300 optical module, CPU controls each MSA300 optical module by CPLD.

The I of CPU ²C interface provides data wire I ²CSDA, clock line I ²CSCL.Two-way I ²The CSDA line comes out from CPU, is connected to the I of each enhancement mode MSA300 optical module simultaneously ²C interface.Unidirectional I ²The CSCL line becomes many identical clock lines through behind the CPLD, from I ²CSCL1 distributes to each enhancement mode MSA300 optical module respectively to IICSCLN.Synchronization, under the control of CPU, I ²CSCL1 is to I ²Can only there be one in this N clock lines of CSCLN effectively.

Logic among the CPLD provides the access control function of enhancement mode MSA300 optical module.N register arranged among the CPLD, and REG1 has deposited each MSA300 optical module I respectively to the REGN (see figure 2) ²The on off state of C interface clock.When the content in the register is logical zero, corresponding MSA300 optical module I ²The C interface clock is closed; When the content in the register is logical one, corresponding MSA300 optical module I ²The C interface clock is opened; CPU visits these registers by system bus, and they are carried out read-write operation.In the access cycle to certain MSA300 optical module, CPU must guarantee in all N register to have only one value to be " 1 ".In system, also have other devices to need CPU to pass through I ²During the C interface visit, the value in this N register all is " 0 ", so that CPU is to the visit of other devices.

With reference to shown in Figure 2, N register is by a switching logic and I ²CSCL1 is to I ²The CSCLN clock lines is corresponding to be connected, " 0 " in a certain register or " 1 " value, and decision is invalid or effective to deserved clock line, and then whether the MSA300 optical module that decision is connected with this clock line is accessed.

Consider CPU in the situation that connects a plurality of MSA300 optical modules, need to adjust I ²If the driving force of CSDA is I ²CSDA is through other device drive, and then the MSA300 optical module number in the system can suitably increase.

Above-mentioned example only is preferred implementation of the present invention, and any variation that can expect and replacement all should be included within the protection range of this invention.

Claims

1, a kind of CPU visits and controls the device of a plurality of MSA300 optical modules, comprise: CPU and at least one MSA300 optical module, described CPU is connected with described MSA300 optical module respectively by data wire, it is characterized in that, also comprise programmable logic device, described CPU is connected with described programmable logic device with system bus by clock line, and described CPU connects the clock line of described MSA300 optical module by the system bus gating; Described programmable logic device is connected with described MSA300 optical module respectively by clock line.

2, CPU according to claim 1 visits and controls the device of a plurality of MSA300 optical modules, it is characterized in that the clock line of the data wire of described CPU and MSA300 optical module and programmable logic device and described MSA300 optical module passes through I ²The C protocol interface is connected.

3, CPU according to claim 1 visits and controls the device of a plurality of MSA300 optical modules, it is characterized in that, described programmable logic device is a CPLD, described CPLD is provided with at least one register, and described register is by corresponding with the described clock line respectively connection of switching logic; Described CPU carries out read-write operation by system bus to described register, controls the effective status of described clock line by described switching logic.

4, CPU according to claim 3 visits and controls the device of a plurality of MSA300 optical modules, it is characterized in that when the content in the described register was logical zero, the clock line of described correspondence was in disarmed state; When the content in the described register was logical one, the clock line of described correspondence was in effective status; When the content in described a plurality of registers all was logical zero, all clock lines all were in closed condition.

5, CPU according to claim 1 visits and controls the device of a plurality of MSA300 optical modules, it is characterized in that described data wire is I ²CSDA, described clock line are I ²CSCL.