CN101404133A - Multi-digit digital pipe control circuit and method thereof - Google Patents
Multi-digit digital pipe control circuit and method thereof Download PDFInfo
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- CN101404133A CN101404133A CNA2008100738833A CN200810073883A CN101404133A CN 101404133 A CN101404133 A CN 101404133A CN A2008100738833 A CNA2008100738833 A CN A2008100738833A CN 200810073883 A CN200810073883 A CN 200810073883A CN 101404133 A CN101404133 A CN 101404133A
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Abstract
The present invention discloses a multi-bit nixietube control circuit and a method thereof. The control circuit comprises a nixietube, the drive circuit of the nixietube, latch drive circuits, a microprocessor and a decoding circuit. The present invention is characterized in that an eight-bit nixietube is used as a control unit of a section or a bit; two latch circuits are respectively used for section drive and bit drive of the nixietube. The method (1) comprises: the data input terminals of section latches and bit latches are independent and separate and are connected with the data transmission permission terminals in parallel, the data transmission permission terminals are directly connected with the microprocessor or connected the microprocessor by the decoding circuit. The method (2) comprises: the data input terminals of the section latches and the bit latches are connected in parallel, and the data transmission permission terminals are independent and separate; the independent and separate data transmission permission terminals of the sections and the bits are respectively connected with the microprocessor; the data signals of the section latches and bit latches of each control unit respectively drive the corresponding nixietube by the drive circuit of the nixietube. The method solves the problem of high cost when the multi-bit nixietube is driven or a plurality of LEDs are used for imaging.
Description
Affiliated technical field
The present invention relates to the method that a kind of indication of variable information is controlled, more specifically, relate to a kind of multi-digit digital pipe control circuit and method thereof.
Background technology
At present, the display packing of control charactron is generally dynamic demonstration or static the demonstration; Driving method: what have directly drives with single-chip microcomputer, but takies a large amount of communication input/output interface I/O, and the figure place that drives is few; What have uses nixie decoder circuit in conjunction with Micro Controller Unit (MCU) driving, but the figure place that drives also seldom; Also having more advanced control method is exactly to drive with the charactron special chip with serial communication interface, it is few that this method takies interface I/O, a this chip generally can drive 4-8 position charactron, as model is the special chip of SAA1064 or MAX7219, but this chip price is expensive, occasion needing multidigit nixie tube to drive just needs cascade, and cost is just higher.When needs when more the charactron of multidigit drives, above method must have been considered from cost, hardware resource.
Summary of the invention
The object of the present invention is to provide a kind of multi-digit digital pipe control circuit and method thereof, the problem of cost, hardware resource in the time of solving multidigit nixie tube that above-mentioned prior art exists and drive.
Technical scheme of the present invention is:
By software programming, with 8 charactrons is a control module, two latch integrated circuit are respectively section, the position driving of the charactron of a control module, section, position latch integrated circuit output is the section of connecing, bit driver circuit respectively, be connected to after section, the bit driver circuit output on the section, position of charactron, and section, latch integrated circuit input end:
Control method 1:
A), the position of all control module latchs or section input driving data lines are connected in parallel one by one, section, position datawire respectively account for 8 microprocessor I/O, data transmission of drawing two latchs of each unit simultaneously in parallel allow end CP OEn, data transmission as this unit of control allows control port, promptly the control port CP of two latch data gatings OEn, a control module takies a data transmission and allows I/O, N unit takies N data transmission and allows I/O, hence one can see that, and (16+N) individual interface I/O can drive 8N position charactron; Because one digit number sign indicating number pipe is made up of 8 light emitting diodes, so (16+N) 64N LED light emitting diode of individual interface I/O may command;
B), owing to selected the M-n translation code convertor for use, as the 2-4 translation code convertor 74LS139 is arranged, the 3-8 translation code convertor has 74LS138, the 4-16 translation code convertor has 74LS154 or the like, promptly the M-n translation code convertor has n=2 after decoding
MIndividual output terminal, this output terminal can be used as the I/O that control data transmission allows end, and translation code convertor only takies M microprocessor I/O, and therefore, M microprocessor I/O end is through having n=2 after the conversion of M-n translation code convertor
MIndividual output port can be used for allowing as data transmission the control I/O of end, just N=n=2
MSo, be used to control the microprocessor I/O that M control module data transmission allows end originally, after the conversion of M-n translation code convertor, may command 8*2
MPosition charactron or 64*2
MIndividual LED light emitting diode that is to say, after data transmission allows end CP OEn through the conversion of M-n translation code convertor, push away by " 8N charactron of 16+N I/O may command or 64N LED light emitting diode ": 16+M I/O may command 8*2
MIndividual charactron or 64*2
MIndividual LED light emitting diode.
Control method 2: the position of all latchs and section driving data lines are connected in parallel one by one, section after the parallel connection, position datawire only account for 8 microprocessor I/O, the data transmission of two latchs allow end CP OEn then draw separately, and be connected respectively on the microprocessor, section, bit data transmission allow end respectively to account for 1 microprocessor I/O respectively, so a control module takies 8+2 I/O.Because a control module has 8 charactrons, a control module takies 8+2 I/O, so, 8+2N microprocessor I/O may command 8N position charactron.Wherein, the natural number of M 〉=2, n=2
M, N=1,2,3...... are natural number.
Be specially:
A kind of multi-digit digital pipe control circuit and method thereof, it draws together bag charactron (1), charactron driving circuit (2), latch driving circuit (3), transmitting-receiving interface circuit (5), microprocessor (6), house dog (7), storer (8), decoding scheme (9), it is characterized in that:
With 8 charactrons (1) is the control module of a section, position, two latchs (Un, Un+1) drive as section, the position of a unit charactron respectively, the outputting data signals of each control module section, position latch (Un, Un+1), respectively drive section, the position of pairing charactron, and the method for attachment of the input of two latchs (Un, Un+1) is by a section, figure place sign indicating number tube drive circuit (Qn, Qn+1):
A), the data input pin of section, position latch independently separately and data transmission allows end charactron driving in parallel, method is:
The section of a plurality of control modules, position latch (Un, Un+1) 8 ((the individual driving data signal input pin of COM8~COM1) one is received the 8 corresponding ((COM8~COM1) individual section of SC8~SC1)+8 of described microprocessor (6) respectively in regular turn in the lump for SC8~SC1)+8, on the bit data signal output I/O, the section of each control module, two the latch (Un in position, Un+1) data transmission allows end position CP/OESCn, the common data transmission of section CP/OECOMn after being connected in parallel allows end (CP OEn) to allow end as the data transmission of a unit of control, the transmission of the common data of each unit allows end (CP OEn) directly or by a M-n decoding scheme control output end Kn corresponding with described microprocessor (6) to connect, and this control output end Kn holds (CP OEn) as the common data transmission permission of a control module; Described microprocessor (6) output show 8 ((COM8~COM1) individual section, bit data signal must allow end (CP OEn) synchronous transmission with the common data transmission of the section of corresponding output, two latchs in position (Un, Un+1) for SC8~SC1)+8.
B), section, the position data input pin parallel connection of latch and data transmission allows the independent separately charactron of end to drive, method is:
The section of a plurality of control modules, position latch (Un, Un+1) 8 (((SC8 meets COM8 to the individual driving data signal input pin of COM8~COM1) in regular turn respectively for SC8~SC1)+8, SC7 meets COM7...SC1 and meets COM1) in parallel one by one, 8 ports after the parallel connection (SCCOM8~SCCOM1) be connected in regular turn respectively described microprocessor (6) corresponding 8 (on the individual data-signal output pin of SC8~SC1), as section, position driving data output control pin, and the section of each control module, two the latch (Un in position, Un+1) data transmission allows end (position CP/OE SCn, section CP/OE COMn) then separately independent, the section after independent separating, the bit data transmission allows end section CP/OE SCn, position CP/OE COMn receives microprocessor section Kn respectively, on the Kn+1 of position; ((the data-signal output of COM8~COM1) must allow end section CP/OE SCn or position CP/OE COMn synchronous transmission with the section (Un) of corresponding output or the latch data transmission of position (Un+1) for SC8~SC1) or 8 sections in 8 positions that described microprocessor (6) output shows.
Described microprocessor (6) also is connected with transmitting-receiving interface circuit (5), house dog (7), storer (8) respectively, wherein, the signal output part of transmitting-receiving interface circuit (5) is connected with the serial communication Data Receiving pin RX of microprocessor, the signal input part of receiving interface circuit is connected with the serial communication data transmission pin TX of microprocessor, and clock line SCL, the data line SDA of storer are connected on the microprocessor by iic bus.
Signal input part L1, the L2 of described code translator, L3...Ln allow end K1, K2, K3...Kn to link to each other with the data transmission of microprocessor respectively, signal output part D1, the D2 of code translator, D3 ... Dn respectively with section, two the driving latchs in the position institute of charactron and the common data transmission that connects allow to hold CP/OE1, CP/OE2, CP/OE3 ... the CP/OEn connection.
The multidigit nixie tube display controller of said structure is to be one to show wholely with multidigit nixie tube, or claims a chastity.Be received as high interrupt with local information, the information microprocessor is with certain periodic refreshing video data break period, whole charactron is as a chastity, bits per inch sign indicating number pipe is counted a little as a picture, has scanned loyal data with the unit interval 1, every the next pixel of unit interval 2 scannings, waiting for simultaneously receiving by this diji provides the relevant communication protocol Data Receiving to interrupt, have Data Receiving to interrupt, receive data, finishing shows the charactron data.With 8 charactrons is a unit, is driven by two latchs;
A) data input pin when section, position latch (Un, Un+1) independently separately respectively accounts for 8 I/O, and separately with described microprocessor (6) when being connected, their data transmission allows end to be connected in parallel, the data transmission of a unit allows end with an I/O control, allows end CP/OEn as cell data transmission of control; Because the data input pin of section, position latch respectively takies 8 I/O, be total to 8+8=16 I/O, and a control module takies a data transmission permission I/O, so the needed I/O number of the charactron of a driving N unit is: 16+N, (16+N) individual I/O can drive 8N position charactron or 64N LED light emitting diode; Data transmission allow end CP OEn by the conversion of M-n code translator, (16+M) individual I/O end can drive 8*2
MPosition charactron or 64*2
MIndividual LED light emitting diode, the method is called: the data input pin of section, position latch (Un, Un+1) independently separates and data transmission permission end CP/OEn multiple process.
B) section of working as, position latch (Un, Un+1) data input pin is connected in parallel, when taking 8 I/O, their data transmission allows end independently to be separately connected on the microprocessor (6), the data transmission of a control module allows the end section, the position respectively accounts for 1 I/O, shared 2 I/O, section as a unit of control, the bit data transmission allows end section CP/OE SCn and position CP/OE COMn, because section, position latch (Un, Un+1) data input pin is connected in parallel, so take 8 data transmission I/O, and a control module section, the position respectively takies a data transmission and allows I/O, so the needed I/O number of the charactron of a driving N unit is: 8+2N, 8+2N I/O may command 8N position charactron or 64N LED light emitting diode.The method is called: the data input pin parallel connection of section, position latch (Un, Un+1) and data transmission allows the independent separately method of end.
Whole charactron is as a chastity, and bits per inch sign indicating number pipe is counted a little as a picture, if design 100Hz (10ms) has shown loyal data, each shows 50us as several points, also just changes one digit number sign indicating number pipe every 50us and shows, can show:
10ms/50us=10000us/50us=200 (position)
Charactron; One digit number sign indicating number pipe has 8 sections, or has:
200*8=1600 (individual)
Can drive and show 1600 LED light emitting diodes.200 charactrons have 25 unit, data input pin with section, position latch independently separates and data transmission permission end multiple process, by (16+N) but individual interface I/O display driver 8N position charactron get, the charactron that drives 200 only needs 16+25=41 interface I/O just can or to select the 4-16 code translator for use, by (16+M) but individual interface I/O end display driver 8*2
MAs long as the position charactron gets, promptly 16+25/4=16+7=23 interface I/O; Data transmission allows the independent separately method of end with the data input pin parallel connection of section, position latch, is got by 8+2N control I/O may command 8N position charactron, and the charactron that drives 200 needs 8+2*25=58 control I/O.
Relatively N is different when severals, and (16+N) with (8+2N) value, wherein, N is natural number 1,2,3......, use respectively identical natural number substitution (16+N) and (8+2N) must, when N<8, (16+N)>(8+2N); When N=8, (16+N)=8+2N; When N>8, (16+N)<(8+2N).As seen, when N=8, (16+N)=(8+2N), because a control module is 8 charactrons, thus when the charactron of 8 unit of driving, code translator not, the I/O number that any two kinds of driving methods take is identical; When N less than 8 the time, data transmission allows the independent separately method of end to drive charactron and relatively economizes the I/O resource with the data input pin parallel connection of section, position latch; When N greater than 8 the time, independently separately and data transmission allows end multiple process driving charactron relatively to economize the I/O resource with the data input pin of section, position latch.
Local microprocessor provides interface communications protocol, and upper single-chip microcomputer user only need send video data, just can conveniently realize the driving of multidigit nixie tube or many LED light emitting diode.
Advantage of the present invention is:
1, the local information processor provides the communication protocol of hommization the most, and binary-coded decimal transformat, a 8Bit RAM are the display message content of double figures sign indicating number pipe, the priority that on behalf of charactron, the data that host computer sends successively show.
2, as long as control corresponding positions display message data just can be operated the demonstration of corresponding positions arbitrarily, only need a spot of I/O, show that the position can reach the charactron more than 200.
3, on the charactron display mode, introduced the scan method of chastity and pixel, the data input pin of having used section, position latch simultaneously independently separately and data transmission allows the data input pin parallel connection of end multiple process and section, position latch and data transmission allows the independent method of separating of end, control section, position latch, and then save the I/O resource.
Description of drawings
Fig. 1 is that the data input pin of section of the present invention, position latch independently separates and the circuit reason figure of data transmission permission end charactron driving in parallel.
Fig. 2 is that M-n code translator of the present invention is realized the circuit theory diagrams that charactron shows.
Fig. 3 is section of the present invention, the position data input pin parallel connection of latch and circuit theory diagrams that data transmission allows the independent separately charactron of end to drive.
Fig. 4 is the software flow pattern that the present invention is solidificated in microprocessor.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further described.
Shown in Figure 1, be that the data input pin of section, latch of the present invention independently separates and the circuit reason figure of data transmission permission end charactron driving in parallel.It draws together bag charactron (1), charactron driving circuit (2), latch driving circuit (3), communication interface (4), transmitting-receiving interface circuit (5), microprocessor (6), watchdog circuit (7), storer (8); Charactron driving circuit (2) comprises segment drive circuit Q1 and bit driver circuit Q2, and it can be made up of triode or other power integrated circuit.Latch driving circuit (3) adopts two latch integrated circuit U1 and U2, as section, the position driving interface of a control module, shown in the dotted line circle becomes; Latch U1 drives input interface as the section of charactron, and latch U2 is as the driving input interface of charactron position.Latch U1, U2 can select the latch that has latch function as 74LS374 or 74LS574 etc. for use.Two latch integrated circuit U1, U2 and driving circuit Q1, Q2 form the driver module of a control module.The annexation of circuit is:
(1), the section input pin a of control module charactron (1), b, c, d, e, f, g, h, respectively in regular turn with the corresponding connection of the pairing output terminal of input end IN1-IN8 of segment drive circuit Q1, signal output pin 12~19 corresponding in regular turn connections respectively of the input end IN1~IN8 of segment drive circuit Q1 and section latch integrated circuit U1, the signal input pin 2~9 of section latch integrated circuit U1 is received respectively on SC8~SC1 pin of 6 sections drivings of microprocessor I/O.
(2), position input pin C1~C8 of control module charactron (1) respectively in regular turn with the corresponding connection of the pairing output terminal of input end IN1~IN8 of bit driver circuit Q2, input end IN1~the IN8 of bit driver circuit Q2 and the signal output pin of latch integrated circuit U2 12~19 a corresponding in regular turn connection respectively, the signal input pin 2 of position latch integrated circuit U2,3,4,5,6,7,8,9 receive 6 COM8 that drive I/O of microprocessor, COM7 respectively, COM6, COM5, COM4, COM3, COM2 is on the COM1 pin.
(3), the data transmission of the section latch integrated circuit U1 of same control module allows the data transmission of end CP/OE SC1 and position latch integrated circuit U2 to allow end CP/OE COM1 to connect to form the transmission of section common data to allow end CP/OE1 and be connected on the K1 end of microprocessor 6.
Above-mentioned (1) (2) (3) have constituted the connected mode of a unit charactron, in like manner, the charactron of N unit is identical with above-mentioned basic connected mode, and the signal input pin 2~9 of the section latch integrated circuit Un of all unit is all received respectively on SC8~SC1 pin of 6 sections drivings of microprocessor I/O; The signal input pin 2,3,4 of all latch integrated circuit Un+1,5,6,7,8,9 receive 6 COM8 that drive I/O of microprocessor, COM7 respectively, COM6, COM5, COM4, COM3, COM2 is on the COM1 pin, different is, the data transmission of each unit allows end CP/OE1~n to be connected in regular turn respectively on the K1~Kn of I/O correspondence of microprocessor (6).
From annexation as can be known, the present invention is a control module with 8 charactrons, and two latch circuit U1, U2 and corresponding two sections, bit driver circuit Q1, Q2 form one 8 figure place sign indicating number management and control system unit.N digital management and control system unit constitutes the whole display of one side, the input driving data lines one of the latch Un of N control module and section latch Un+1 connects in the lump, section, position datawire respectively account for 8 interface I/O, the data transmission of each control module allows end CP/OEn to interconnect, and link to each other with the control output end Kn of microprocessor 6, be subjected to the control of microprocessor (6), make control information and data presented synchronous.
Communication interface (4) is the control signal input/output terminal, and its pin 2 connects public ground, and pin 1 is signal emission output terminal, and pin 3 receives input end for signal.Received signal enters from the pin 3 of communication interface (4), amplify through transmitting-receiving interface circuit (5), directly deliver to the serial communication receiving end RX of microprocessor (6), microprocessor receives data after classification is handled, the relevant information that needs to store is given eeprom memory (8), data presented is sent to respective display unit, microprocessor (6) receives data processing and finishes, send an answer signal, this Data Receiving success is described, the signal transmitting terminal TX of the treated device of answer signal (6) launches, and goes out through transmitting-receiving interface circuit (5) amplifying emission again, receives for host computer.It is the integrated circuit of MAX232 or other serial communication that transmitting-receiving interface circuit (5) can adopt model.Microprocessor (6), watchdog circuit (7), storer (8) integrated circuit adopt existing ripe chip in the modern technologies, are the microprocessor chip of EV2-SP92416 as model, also can select other microprocessor of built-in EEPROM for use; The MAX705 house dog integrated circuit that model is, model are the eeprom memory integrated circuit of AT24CXX.
The resetting pin of described watchdog circuit (7), signal pins by with being connected of microprocessor (6), after the energising, watchdog circuit (7) is the working condition of monitor microprocessors (6) constantly, if it is unusual that microprocessor (6) work occurs, surpassing the unit interval stops to send feeding-dog signal to watchdog circuit (7), watchdog circuit (7) will be sent reset signal, make microprocessor (6) recover operate as normal.
Storer (8) integrated circuit is connected on the microprocessor (6) by iic bus.Microprocessor (6) is gone up current potential and is resetted, and reads the relevant information of the required initialization of microprocessor (6) electrification reset and user's setting from storer (8) integrated circuit by iic bus; And microprocessor needs canned data to store storer (8) integrated circuit into by iic bus, the preservation after the power down of realization data.
Among Fig. 1, microprocessor (6) electrification reset initialization, microprocessor (6) reads the relevant information of power-up initializing data and user's setting from storer (8), enters timer and shows interrupt latency and receive interrupt latency.Interrupt if receive, data are sent into the serial interface RX of microprocessor (6) from transmitting-receiving interface circuit (5), microprocessor (6) enters the data qualification processing after receiving data, need the data of storage to be stored in the storer (8), and need data presented to give the display buffer by iic bus; Interrupt if timer shows, microprocessor (6) is read the video data of corresponding units from the display buffer, and segment data is by the data output pin SC8 of microprocessor (6), SC7, SC6, SC5, SC4, SC3, SC2, SC1 be the pin 2,3,4 among the section of the delivering to latch Un respectively, 5,6,7,8,9; Bit data is passed through the data output pin COM8 of microprocessor (6), COM7, and COM6, COM5, COM4, COM3, COM2, COM1 deliver to the pin 2,3,4,5,6,7,8,9 among the latch Un+1.Section, bit data are sent and are finished, the common data transmission of section, position allows the control output end Kn of the microprocessor (6) that end CP/OEn links to each other to allow signal for this section, position common data transmission allow an end CP/OEn to send data transmission at once therewith, the section of making, bit data allow signal with data transmission: segment data is latched among the Un, and bit data latchs among the Un+1; After section, bit data were latched among Un, the Un+1 respectively, segment data was by segment drive circuit Qn, after bit data is carried out the electric current amplification by bit driver circuit Qn+1, so that enough big current drives charactron to be arranged, wherein, segment data SC8, SC7, SC6, SC5, SC4, SC3, SC2, the pairing driving circuit Qn of SC1 exports segment encode, delivers to section a, b, c, d, e, f, g, the h of charactron (1) respectively through driving circuit Qn; Bit data COM8, COM7, COM6, COM5, COM4, COM3, COM2, the pairing driving circuit Qn+1 of COM1 export bit code and deliver to respectively among position C8, the C7 of charactron, C6, C5, C4, C3, C2, the C1, have finished the scanning of a pixel.In like manner, carry out the scanning of next pixel, up to the scanning of finishing a frame.
Fig. 2 is that M-n code translator of the present invention is realized the circuit theory diagrams that charactron shows.
As shown in the figure, its principle of work is on the basis of Fig. 1, the data transmission of microprocessor 6 allows K1~Kn to connect the input end L1~Ln of M-n code translator, and the decoded signal output terminal D1~Dn of M-n code translator (9) respectively the section of being connected to, position common data transmission in regular turn allow to hold on CP/OE1~n.This is under the few situation of the big microprocessor I/O of quantity of control module, revises the data of the CP/OE1~n software module of data transmission permission slightly, just can realize driving more multiunit charactron.If there is the charactron of a plurality of control modules to drive, input end L1~the Ln of M-n code translator (9) connects the control output K1~n end of microprocessor (6) respectively in regular turn, section, position latch common data transmission allows end CP/OE1 to be connected to first output terminal D1 of code translator (9), section, position latch common data transmission allows end CP/OE2 to be connected to second output terminal D2 of code translator (9), section, position latch common data transmission allows end CP/OE3 to be connected to the 3rd output terminal D3 of code translator (9), ... the rest may be inferred, the CP/OEn of a plurality of control modules is connected on the Dn successively.The fan-in factor of M-n code translator is M, and behind code translator, fan-out factor is n, and by binary relation as can be known, the pass of M and n is: n=2
MSelect 4~16 code translators such as system, as long as 4 code translator input I/O, the single-chip processor i/o of K1~K4 just, just there are 16 output terminals to be connected with CP/OE1~CP/OE16, like this, 16+4=20 I/O just can drive 8*16=128 position charactron or 8*8*16=1024 LED light emitting diode.
Among Fig. 2: the control output end K1~Kn of microprocessor (6) is connected respectively in regular turn with the decoded signal input end L1~Ln of code translator (9), if M=3, then N=n=2
M=8.Corresponding 3-8 code translator (9) output terminal has D1~D8, CP/OE1 meets D1, CP/OE2 meets D2, and the rest may be inferred, and CP/OE8 meets D8, data strobe is effective if CP/OEn is the low level negative edge, when L1L2L3=000, D8D7D6D5D4D3D2D1=11111110 then, the data of CP/OE1 unit are by gating, section, bit data arrive U1 to data latching respectively with gating signal, among the U2; When L1L2L3=001, D8D7D6D5D4D3D2D1=11111101 then, the data of CP/OE2 unit are by gating, section, bit data arrives U3 to data latching respectively with gating signal, among the U4 ..., when L1L2L3=111, D8D7D6D5D4D3D2D1=01111111 then, section, bit data arrives U15 to data latching respectively with gating signal, among the U16, finished from microprocessor (6), arrived the connection that the common data transmission allows CP/OEn again to code translator (9), by revising the data that data transmission allows CP/OE1~n software module, send the charactron shows signal by the working method of Fig. 1, can realize using microprocessor I/O resource still less, drive more charactron.
Fig. 3 is section of the present invention, the position data input pin parallel connection of latch and circuit theory diagrams that data transmission allows the independent separately charactron of end to drive.
As shown in the figure: the electronic devices and components at circuit do not increase, be based upon on the basis of Fig. 1, the data transmission that has just changed the data input of section, position latch and section, position latch allows the method for attachment of end, can realize the driving of multidigit nixie tube under the different situation of I/O number.Among the figure, data input pin 2~9 pin of section latch U1 and data input pin 2~9 pin of position latch U2 are connected to respectively on the data output pin SC1~SC8 end of microprocessor in regular turn, promptly data input pin 2 pin of data input pin 2 pin of section latch U1 and position latch U2 are connected to form SCCOM1, SCCOM1 is to the data output pin SC1 of microprocessor, data input pin 3 pin of section latch U1 and data input pin 3 pin of position latch U2 are connected to form SCCOM2, SCCOM2 is to the data output pin SC2 of microprocessor, data input pin 4 pin of section latch U1 and data input pin 4 pin of position latch U2 are connected to form SCCOM3, SCCOM3 is to the data output pin SC3 of microprocessor, the rest may be inferred, data input pin 9 pin of section latch U1 and data input pin 9 pin of position latch U2 are connected to form SCCOM8, SCCOM8 is to the data output pin SC8 of microprocessor, and the data transmission of section latch U1 allows CP/OE SC1, the data transmission of position latch U2 allows CP/OE COM1 then independently to separate CP/OE SC1, CP/OE COM1 receives the K1 of microprocessor (6) respectively, on the K2.
The above-mentioned data input pin parallel connection that has constituted a section, position latch and data transmission allow a control module of the charactron driving circuit that end independently separates, 8 charactrons of a control module may command.Because section, 8 data input ends of position latch are connected in parallel one by one, take 8 microprocessor I/O, and section, the data transmission of position latch allows end separately, take 2 microprocessor I/O, so a control module takies 8+2 microprocessor I/O, when a plurality of control module, the section of a plurality of control modules, the data input pin of position latch is by above-mentioned method of attachment, be connected in regular turn one by one respectively after the parallel connection on the data output pin SC1~SC8 end of microprocessor, so no matter what control modules are arranged, section, the data input pin of position latch is connected the I/O number that takies with microprocessor all be 8 I/O, and the section of a described N control module, the data transmission of position latch allows end separately independent, the data transmission of the section latch of first unit allows end CP/OE SC1 to receive on the K1 of microprocessor, the data transmission of the position latch of first unit allows end CP/OE COM1 to receive on the K2 of microprocessor, the data transmission of the section latch of second unit allows end CP/OE SC2 to receive on the K3 of microprocessor, the data transmission of the position latch of second unit allows end CP/OE COM2 to receive on the K4 of microprocessor, the rest may be inferred, the data transmission of the section latch of n unit allows end CP/OE SCn to receive on the Kn of microprocessor, and the data transmission of the position latch of n unit allows end CP/OE COMn to receive on the Kn+1 of microprocessor.Section, the position data input pin parallel connection of latch and method of attachment that data transmission allows the independent separately charactron of end to drive, N digital management and control system unit constitutes the whole display of one side, the input driving data lines one of the position latch Un of N control module and section latch Un+1 connects in the lump, section, position datawire account for 8 microprocessor I/O, the data transmission of each control module allows the independent separately connection of end, and link to each other with control output end Kn, the Kn+1 of microprocessor (6) respectively, be subjected to the control of microprocessor (6), make control information and data presented synchronous.Section, the position data input pin parallel connection of latch and method of attachment that data transmission allows the independent separately charactron of end to drive, under the driving of microprocessor (6) Control Software program, microprocessor (6) is sent the bit data signal to a unit, and the data transmission of sending this simultaneously allows signal, finish, microprocessor (6) is sent the segment data signal to this element again, and the data transmission of the section of sending allows signal simultaneously, after finishing the scanning of a pixel, enter the scanning of next pixel, up to the scanning of finishing a frame.
Shown in Figure 4, be the software flow pattern that the present invention is solidificated in microprocessor.
The software flow step that is solidificated in microprocessor (6) is: " system initialization " (10) enter " waiting timer interrupts, waits for receiving and interrupt " (11);
(1) if receive when interrupting, enter " receiving the data subroutine " (12), finishing enters " data qualification processing " (13), enters " interruption is returned " (14);
(2) if timer interrupts, enter " data of judging the N unit allow transmission signals scanning to be over? " (20), if not, enter " send corresponding section video data; and point to the CP/OE handling procedure of next unit " (15), finish and enter " interruption is returned " (16), if, enter " changing a position video data subroutine " (19), enter " judging that 8 bit scans are over? " (18), if not, enter " send corresponding section video data; and point to the CP/OE handling procedure of next unit " (15), finish and enter " interruption is returned " (16), if, enter " reset section; position; CP/OE scan-data " (17), enter " interruption is returned " (16).
The present invention controls the following mode of reception data layout of charactron or light emitting diode:
Begin to receive Data Labels | DataL1 | DataH2 | DataL3 | DataH4 | DataL5 | DataH6 | DataL7 | DataH8 | ... | ?DataLn | DataHn+1 | Stop |
When system receive begin to receive Data Labels and authentication success after, begin to receive the binary-coded decimal data, one 8 received bit data Data is divided into two, low four control datas that DataL1 is first charactron; High four control datas that DataH2 is a second order digit sign indicating number pipe, the rest may be inferred, and data DataLn is the control data of n position charactron, and data DataH n+1 is the control data of n+1 position charactron, stops to receive data when receiving position of rest STOP.
The present invention is specially adapted to industrial numerically-controlled machine, digital clock, the digital interest rate indicator gauge of bank etc. needs multidigit number to show the occasion use.The present invention is very easy to realize that software is successfully by test, and all electronic devices and components all can be buied on the market.Because wide application of the present invention, easy to use flexible, the expection economic benefit is considerable.
Though the present invention describes with the above embodiments, but those of ordinary skill in the art, what should be understood that recognizes, above embodiment only is the excellent example of explanation of the present invention, should understand wherein can do each and change and revise and do not break away from the present invention on Fang Yi.So, be not as qualification of the present invention, as long as in connotation scope of the present invention, to the variation distortion of the above enforcement or revise the protection domain that all will fall into claim of the present invention.
Claims (6)
1, a kind of multi-digit digital pipe control circuit, it draws together bag charactron (1), charactron driving circuit (2), latch driving circuit (3), transmitting-receiving interface circuit (5), microprocessor (6), house dog (7), storer (8), decoding scheme (9), it is characterized in that:
With 8 charactrons (1) is the control module of a section, position, two latchs (Un, Un+1) drive as section, the position of a unit charactron respectively, the outputting data signals of each control module section, position latch (Un, Un+1), respectively drive section, the position of pairing charactron, and the method for attachment of the input of two latchs (Un, Un+1) is by a section, figure place sign indicating number tube drive circuit (Qn, Qn+1):
A) data input pin of section, latch independently separates and the charactron driving in parallel of data transmission permission end;
B) section, the position data input pin parallel connection of latch and data transmission allows the independent separately charactron of end to drive.
2, a kind of multi-digit digital pipe control circuit according to claim 1, its special card is:
Described microprocessor (6) also is connected with transmitting-receiving interface circuit (5), house dog (7), storer (8) respectively, wherein, the signal output part of transmitting-receiving interface circuit (5) is connected with the serial communication Data Receiving pin RX of microprocessor, the signal input part of receiving interface circuit is connected with the serial communication data transmission pin TX of microprocessor, and clock line SCL, the data line SDA of storer are connected on the microprocessor by iic bus.
3, a kind of multi-digit digital pipe control circuit according to claim 1, its special card is:
Signal input part L1, the L2 of described code translator (as 74LS138 or 74L154 etc.), L3...Ln allow end K1, K2, K3...Kn to link to each other with the data transmission of microprocessor respectively, signal output part D1, the D2 of code translator, D3 ... Dn respectively with section, two the driving latchs in the position institute of charactron and the common data transmission that connects allow to hold CP/OE1, CP/OE2, CP/OE3 ... the CP/OEn connection.
4, a kind of multidigit nixie tube control method according to claim 1, its special card is:
The section of a plurality of control modules, position latch (Un, Un+1) 8 ((the individual driving data signal input pin of COM8~COM1) one is received the 8 corresponding ((COM8~COM1) individual section of SC8~SC1)+8 of described microprocessor (6) respectively in regular turn in the lump for SC8~SC1)+8, on the bit data signal output I/O, the section of each control module, two the latch (Un in position, Un+1) data transmission allows end position CP/OESCn, the common data transmission of section CP/OECOMn after being connected in parallel allows end (CP OEn) to allow end as the data transmission of a unit of control, the transmission of the common data of each unit allows end (CP OEn) directly or by the control output end Kn connection corresponding with described microprocessor (6) of M-n decoding scheme, transmission allows end (CP OEn) to this control output end Kn as the common data of a control module, the 8 ((COM8~COM1) individual section of SC8~SC1)+8 that described microprocessor (6) output shows, the bit data signal must with the section of corresponding output, two the latch (Un in position, Un+1) transmission of common data allows end (CP OEn) synchronous transmission.
5, a kind of multidigit nixie tube control method according to claim 1, its special card is:
The section of a plurality of control modules, position latch (Un, Un+1) 8 (((SC8 meets COM8 to the individual driving data signal input pin of COM8~COM1) in regular turn respectively for SC8~SC1)+8, SC7 meets COM7...SC1 and meets COM1) in parallel one by one, 8 ports after the parallel connection (SCCOM8~SCCOM1) be connected in regular turn respectively described microprocessor (6) corresponding 8 (on the individual data-signal output pin of SC8~SC1), as section, position driving data output control pin, and the section of each control module, two the latch (Un in position, Un+1) data transmission allows end (position CP/OE SCn, section CP/OE COMn) then separately independent, section after independent separating, the bit data transmission allows end section CP/OE SCn, position CP/OE COMn receives microprocessor section Kn respectively, on the Kn+1 of position, ((the data-signal output of COM8~COM1) must allow end section CP/OE SCn or position CP/OE COMn synchronous transmission with the section (Un) of corresponding output or the latch data transmission of position (Un+1) for SC8~SC1) or 8 sections in 8 positions that described microprocessor (6) output shows.
6, a kind of multi-digit digital pipe control circuit according to claim 1 and method thereof, its special card is:
The software flow step that is solidificated in microprocessor (6) is: " system initialization " (10) enter " waiting timer interrupts, waits for receiving and interrupt " (11);
(1) if receive when interrupting, enter " receiving the data subroutine " (12), finishing enters " data qualification processing " (13), enters " interruption is returned " (14);
(2) if timer interrupts, enter " data of judging the N unit allow transmission signals scanning to be over? " (20), if not, enter " send corresponding section video data; and point to the CP/OE handling procedure of next unit " (15), finish and enter " interruption is returned " (16), if, enter " changing a position video data subroutine " (19), enter " judging that 8 bit scans are over? " (18), if not, enter " send corresponding section video data; and point to the CP/OE handling procedure of next unit " (15), finish and enter " interruption is returned " (16), if, enter " reset section; position; CP/OE scan-data " (17), enter " interruption is returned " (16).
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