CN101373950B - Frequency-mixing apparatus and correlation method - Google Patents

Abstract

The invention relates to a frequency mixing device, which can design harmonic item times to be filtered according to the needs so as to promote the representation of the circuit characteristics. In addition, the harmonic interference phenomenon can be improved greatly through the frequency mixing device no matter which type of frequency mixing circuits is adopted by the frequency mixing device.

Description

Frequency mixing apparatus and related method

Technical Field

The present invention relates to a mixer, and more particularly to a mixer for harmonic rejection.

Background

In many data communication circuits, a mixer is an important component. The mixer mixes a received signal with a clock signal LO. The above processing method, in addition to generating the desired mixing Signal, also generates undesired harmonic terms, which further interfere with the data to be transmitted, greatly reduces the Signal-to-Noise Ratio (SNR), and causes the performance of the receiver to be degraded.

Fig. 1 shows a functional block diagram of a known technique to overcome the harmonic problem. The block diagram 100 of the prior art includes an Antenna (Antenna)102, a Low Noise Amplifier (LNA) 104, a Mixer (Mixer)105, a filter 106, a filter 107, and a Frequency Synthesizer (Frequency Synthesizer)108, wherein the Frequency Synthesizer 108 provides a clock signal LO. The signal processing method of fig. 1 is to use a filter 107 to filter out unwanted harmonics; finally, an Intermediate Frequency signal I (Intermediate Frequency/IF) or a base Frequency signal B (Baseband Frequency) without harmonics is generated.

Conventionally, the filter 107 is mostly used as follows: LC Filter (LC Filter), transductive Filter (Gm-C Filter) and OP-RC Filter (OP-RC Filter). If the LC filter is adopted; because the value of L is very large, if the filter 107 is fabricated inside the chip, the chip area will be increased and the chip cost will be increased; additional cost is also required to fabricate L outside the chip. If the Gm-C filter or the OP-RC filter is used, the Noise Figure (Noise Figure) increases and the Linearity decreases, so that the performance of the overall circuit characteristic is greatly deteriorated. However, no matter how good a filter is used, the area of the chip is still increased, and the cost is increased.

As is apparent from the above description, the circuit characteristics of the prior art cannot meet the standard of harmonic interference to be solved by those skilled in the art, except for the relatively high cost. Accordingly, there is a need for a novel invention that addresses the long-standing problems in the art described above.

Disclosure of Invention

It is an object of the present invention to provide a mixer for harmonic rejection to solve the above problems.

It is an object of the present invention to provide a mixer for harmonic rejection that can resolve the interference of various harmonics of different frequencies as desired.

The invention provides an equivalent function block structure of a wave mixing device, which can also design a harmonic wave item to be filtered according to self requirements, thereby improving the performance of circuit characteristics. In addition, no matter what kind and type of mixer circuit is used in the mixer, the phenomenon of harmonic interference can be greatly improved by the present invention. In addition, a chip designer can design a circuit according to the harmonic term to be filtered, and the circuit design is more flexible.

Drawings

Fig. 1 is a functional block diagram of a conventional technique for overcoming harmonic interference.

Fig. 2 is a functional block diagram of a frequency mixing device according to an embodiment of the present invention.

Fig. 3(a) is a functional block diagram of an embodiment of a frequency mixing device according to the present invention.

Fig. 3(b) is a functional block diagram of an embodiment of a frequency mixing device according to the present invention.

Fig. 3(c) is a functional block diagram of an embodiment of a frequency mixing apparatus according to the present invention.

FIG. 3(d) is a functional block diagram of an embodiment of a frequency mixing apparatus according to the present invention.

Fig. 4 is a circuit implementation diagram of an embodiment of fig. 2, 3(a) and 3 (b).

Fig. 5 is a circuit implementation diagram of another embodiment of fig. 2, fig. 3(a) and fig. 3 (b).

Fig. 6 is a circuit implementation diagram of an embodiment of fig. 2, 3(c) and 3 (d).

Description of the figures

100 functional block diagram of a conventional technique for overcoming harmonic interference

102 antenna 104 low noise amplifier

105 mixer 106 filter

107 filter 108 frequency synthesizer

200 frequency mixing device

201 mixer circuit 202 first circuit

203 second circuit 204 third circuit

205 summing unit

2021. 2031 and 2041 gain unit

2012. 2022, 2032, 2042 mixing unit

300 frequency mixing device

301 first gain unit 302 second gain unit

303 third gain unit 304 fourth gain unit

305 first mixing unit 306 second mixing unit

307 third mixing unit 408 fourth mixing unit

309 summing unit

310 frequency mixing device

311 first mixing unit 312 second mixing unit

313 third mixing unit 314 fourth mixing unit

315 first gain unit 316 second gain unit

317 third gain unit 318 fourth gain unit

319 summing unit

320 frequency mixing device

321 first gain unit 322 and second gain unit

323 third gain unit 324 fourth gain unit

325 first mixer unit 326 second mixer unit

327 third mixing unit 328 fourth mixing unit

329 summing unit

330 functional block diagram of an embodiment of a mixer of the present invention

331 first mixing unit 332 second mixing unit

333 third mixing unit 334 fourth mixing unit

335 first gain unit 336 second gain unit

337 third gain unit 338 fourth gain unit

339 summing unit

400A circuit implementation diagram of one embodiment of FIGS. 2, 3(a) and 3(b)

500 Circuit implementation diagrams of another embodiment of FIG. 2, FIG. 3(a), and FIG. 3(b)

600 Circuit implementation diagrams of alternative embodiments of FIG. 2, FIG. 3(c), and FIG. 3(d)

v_in(+)、v_in(-) input signal

V_O(+)、V_O(-) output signal

LO1(+)、LO2(+)、LO3(+)、LO4(+)、

LO1(-), LO2(-), LO3(-), LO4(-) local oscillator signals

Detailed Description

Certain terms are used throughout the description and following claims to refer to particular components. It should be understood by those skilled in the art that the present specification and claims do not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Furthermore, the term "coupled" is intended to encompass any direct or indirect electrical connection.

In the past, the harmonic wave which causes the interference must be filtered by a filter; the present invention provides a mixer, in which at least one harmonic term of the output mixed output signal is eliminated in the mixer, so that the operation of filtering harmonic by at least one filter can be omitted. Therefore, the area of the chip is reduced, the cost is relatively reduced, and the price competitiveness is improved. In addition, it is also possible to determine which harmonic terms to filter out according to the design purpose, so that the design is very flexible. Compared with the prior art, the method is a great improvement not only in chip area, but also in price and design flexibility.

The principles of the present invention may be illustrated by Fourier Series (Fourier Series) to facilitate an understanding of the present invention. As can be derived from the fourier series, the signal lo (t) is actually composed of one, three, five, seven, etc. sine waves, as shown in the following equation:

$\mathrm{LO}\left(t\right)=\sin \left(w_{0}t\right)+\frac{\sin \left(3w_{0}t\right)}{3}+\frac{\sin \left(5w_{0}t\right)}{5}+\frac{\sin \left(7w_{0}t\right)}{7}+\frac{\sin \left(9w_{0}t\right)}{9}+\frac{\sin \left(11w_{0}t\right)}{11}+.....$

wherein,

etc. belonging to the part of the harmonic terms that will cause interference to the signal. Therefore, by eliminating the harmonic terms causing interference, the SNR value can be improved and a good circuit characteristic performance can be obtained. Therefore, the invention utilizes the principle to achieve the purpose of harmonic rejection; the harmonic term is eliminated from the equation, which can be implemented using the following equation:

$V_{\mathrm{out}}\left(t\right)$

<math><mrow><mo>=</mo><mi>R</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>&times;</mo><mrow><mo>(</mo><mi>sin</mi><mrow><mo>(</mo><msub><mi>w</mi><mn>0</mn></msub><mi>t</mi><mo>)</mo></mrow><mo>+</mo><mfrac><mrow><mi>sin</mi><mrow><mo>(</mo><mn>3</mn><msub><mi>w</mi><mn>0</mn></msub><mi>t</mi><mo>)</mo></mrow></mrow><mn>3</mn></mfrac><mo>+</mo><mfrac><mrow><mi>sin</mi><mrow><mo>(</mo><mn>5</mn><msub><mi>w</mi><mn>0</mn></msub><mi>t</mi><mo>)</mo></mrow></mrow><mn>5</mn></mfrac><mo>+</mo><mo>.</mo><mo>.</mo><mo>.</mo><mo>)</mo></mrow><mo>-</mo><mfrac><mn>1</mn><mn>3</mn></mfrac><mi>R</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>&times;</mo><mrow><mo>(</mo><mi>sin</mi><mrow><mo>(</mo><mn>3</mn><msub><mi>w</mi><mn>0</mn></msub><mi>t</mi><mo>)</mo></mrow><mo>+</mo><mfrac><mrow><mi>sin</mi><mrow><mo>(</mo><mn>9</mn><msub><mi>w</mi><mn>0</mn></msub><mi>t</mi><mo>)</mo></mrow></mrow><mn>3</mn></mfrac><mo>+</mo><mfrac><mrow><mi>sin</mi><mrow><mo>(</mo><mn>15</mn><msub><mi>w</mi><mn>0</mn></msub><mi>t</mi><mo>)</mo></mrow></mrow><mn>5</mn></mfrac><mo>+</mo><mo>.</mo><mo>.</mo><mo>.</mo><mo>)</mo></mrow></mrow></math>

<math><mrow><mo>=</mo><mi>R</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>&times;</mo><mrow><mo>(</mo><mi>sin</mi><mrow><mo>(</mo><msub><mi>w</mi><mn>0</mn></msub><mi>t</mi><mo>)</mo></mrow><mo>+</mo><mfrac><mrow><mi>sin</mi><mrow><mo>(</mo><mn>5</mn><msub><mi>w</mi><mn>0</mn></msub><mi>t</mi><mo>)</mo></mrow></mrow><mn>5</mn></mfrac><mo>+</mo><mo>.</mo><mo>.</mo><mo>.</mo><mo>)</mo></mrow></mrow></math>

the above equation completely filters out the third harmonic term. In the same way, the third harmonic term, the fifth harmonic term, the seventh harmonic term, etc. can be filtered out by the same method.

Please refer to fig. 2, which is a block diagram of a mixing apparatus for harmonic rejection according to an embodiment of the present invention.

As shown in fig. 2, the mixing apparatus 200 for harmonic rejection includes a mixing circuit 201, a first circuit 202, a second circuit 203, a third circuit 204 and a summing unit 205. The mixer circuit 201 further includes a mixer unit 2012 for receiving a signal s and f_oAnd the signals s and f are mixed by the mixing unit 2012_oMixing to generate a signal s₁(ii) a The first circuit 202 further comprises a gain unit 2021 and a frequency mixing unit 2022, and is configured to receive the signals s and 3f_oAnd the signals s and 3f are coupled by the gain 2021 and the frequency mixing unit 2022_oMixing to generate a signal s₂(ii) a The second circuit 203 further comprises a gain unit 2031 and a mixer 2032 for receiving the signals s and 5f_oAnd the signals s and 5f are processed by the gain 2031 and the mixing unit 2032_oMixing to generate a signal s₃(ii) a The third circuit 204 further comprises a gain unit 2041 and a mixing unit 2042,and which is used to receive a signal s and 7f_oAnd the signals s and 7f are processed by the gain unit 2041 and the frequency mixing unit 2042_oMixing to generate a signal s₄(ii) a The gain units 2021, 2031 and 2041 are used to convert the signal into a signal with its gain value, and the frequency mixing units 2022, 2032 and 2042 are used to mix the two signals to generate a harmonic signal to be eliminated. Finally, the signal s is summed by the summing unit 205₁、s₂、s₃And s₄Then sum up and output s'.

The first circuit (i.e., the gain unit 2021 and the frequency mixing unit 2022) can be regarded as a third harmonic elimination circuit; the second circuit (i.e., gain unit 2031 and mixing unit 2032) may be considered a fifth harmonic cancellation circuit; the third circuit (i.e., gain unit 2041 and mixing unit 2042) may be considered a seventh harmonic cancellation circuit. In addition, since the third harmonic elimination circuit generates a signal including harmonic terms such as the third harmonic term, the ninth harmonic term, and the fifteenth harmonic term, the ninth harmonic elimination circuit may not be used in the present embodiment. In addition, as shown in fig. 2, one embodiment of the harmonic cancellation circuit is also a mixer, and the difference is that the frequency of the clock signal is N times of the clock signal of the mixer circuit 201, and the gain value is 1/N times of the mixer circuit 201. Furthermore, f_o、3f_o、5f_o、7f_oGenerated by a clock signal generator, embodiments of which may be: frequency synthesizers, Phase Locked Loops (PLLs), etc.

Please refer to fig. 3(a), fig. 3(b), fig. 3(c) and fig. 3 (d). Fig. 3(a), 3(b), 3(c) and 3(d) are functional block diagrams of various embodiments of a mixing apparatus for harmonic rejection of fig. 2 according to the present invention. The operation principle of fig. 3(a), 3(b), 3(c) and 3(d) is similar to that of fig. 2, and thus, a detailed description thereof will be omitted.

Please refer to fig. 4. Fig. 4 is a circuit implementation diagram of an embodiment of the invention. In this embodiment, a Gilbert Mixer (Gilbert Mixer) is used for implementation, although it is not limited theretoOther types of mixers may also be suitable for use with the present invention. The LO1(+) ═ f can be set_o、LO1(-)＝-f_o、LO2(+)＝3f_o、LO2(-)＝-3f_o、LO3(+)＝5f_o、LO3(-)＝-5f_o、LO4(+)＝7f_oAnd LO4(-) -7f_oThe functions shown in fig. 2, 3(a) and 3(b) are realized. Since the Gilbert mixer is a technique well known to those skilled in the art, a description thereof is omitted.

Please refer to fig. 5. FIG. 5 is a circuit implementation diagram of another embodiment of FIGS. 2, 3(a) and 3(b), which is implemented by a Single-ended Mixer (Single-ended Mixer); the LO1(+) ═ f can be set_o、LO1(-)＝-f_o、LO2(+)＝3f_o、LO2(-)＝-3f_o、LO3(+)＝5f_o、LO3(-)＝-5f_o、LO4(+)＝7f_oAnd LO4(-) -7f_oTo realize the functions shown in fig. 2, 3(a) and 3 (b). Since the single-ended mixer is a technique well known to those skilled in the art, a description thereof will be omitted.

Please refer to fig. 6. FIG. 6 is a circuit implementation of one embodiment of FIGS. 2, 3(c) and 3(d), which is also implemented using Gilbert mixers; the LO1(+) ═ f can be set_o、LO1(-)＝-f_o、LO2(+)＝3f_o、LO2(-)＝-3f_o、LO3(+)＝5f_o、LO3(-)＝-5f_o、LO4(+)＝7f_oAnd LO4(-) -7f_oThe functions shown in fig. 2, 3(c) and 3(d) are realized.

In addition, as shown in fig. 4, 5 and 6, one embodiment of the summing unit of fig. 2 and fig. 3(a) -3(d) may be a node.

In practical applications, if the signal strength of the harmonic term is small, the corresponding harmonic cancellation circuit (gain unit and mixer unit) can be omitted; for example: because the signal intensity of the harmonic term of higher order is very small, the harmonic elimination circuit of the harmonic term of fifth order and above harmonic term can be omitted, in other words, only the harmonic elimination circuit of the harmonic term of third order is reserved; of course, if a more accurate signal is required for the subsequent circuit processing, the harmonic elimination circuit of the third harmonic term and the fifth harmonic term can be reserved.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, which is defined by the appended claims.

Claims (8)

1. A frequency mixing apparatus for performing frequency mixing, the frequency mixing apparatus comprising:

a first mixer circuit for receiving an input signal and a first clock signal and outputting a mixing signal, wherein the mixing signal includes an nth harmonic signal, and N is a positive integer;

a harmonic cancellation circuit for receiving a second clock signal and outputting a harmonic cancellation signal, wherein the harmonic cancellation signal corresponds to at least one of the nth harmonic signals; and

a summing circuit for receiving the mixing signal and the harmonic cancellation signal, summing the mixing signal and the harmonic cancellation signal, and generating an output signal,

when the harmonic elimination signal corresponds to the N-th harmonic signal, a gain value of the harmonic elimination circuit is 1/N of a gain value of the first mixing circuit, and the second clock signal is N-times of the first clock signal.

2. The mixing apparatus of claim 1, wherein the harmonic cancellation circuit comprises:

a gain unit for converting the gain of the input signal according to a gain value to output a gain signal; and

a frequency mixing unit for mixing the gain signal and the second clock signal to output the harmonic elimination signal.

3. The mixing apparatus of claim 1, wherein the harmonic cancellation circuit comprises:

a frequency mixing unit for mixing the input signal with the second clock signal to output a second frequency mixing signal; and

a gain unit for converting the gain of the second mixing signal according to a gain value to output the harmonic elimination signal.

4. The mixing apparatus of claim 2 or 3, wherein the summing circuit is a node.

5. A method of mixing, comprising:

receiving an input signal and a first clock signal;

mixing frequency according to the input signal and the first clock signal to output a mixing frequency signal, wherein the mixing frequency signal comprises an N-th harmonic signal, and N is a positive integer;

generating a harmonic cancellation signal, wherein the harmonic cancellation signal corresponds to at least one of the nth harmonic signals; and

summing the mixing signal and the harmonic cancellation signal and generating an output signal,

when the harmonic elimination signal corresponds to the N-th harmonic signal, a gain value corresponding to the harmonic elimination signal is 1/N of a gain value corresponding to the N-th harmonic signal, and the second clock signal is N-times of the first clock signal.

6. The method of claim 5, wherein the step of generating a harmonic cancellation signal further comprises:

and mixing the input signal with a second clock signal to output the harmonic elimination signal.

7. The method of claim 5, wherein the step of generating a harmonic cancellation signal further comprises:

converting the gain of the input signal according to a gain value to output a gain signal; and

the gain signal is mixed with a second clock signal to output the harmonic elimination signal.

8. The method of claim 5, wherein the step of generating a harmonic cancellation signal further comprises:

mixing the input signal with a second clock signal to output a second mixed signal; and

and converting the gain of the second mixing signal according to a gain value to output the harmonic elimination signal.

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