CN101295985B - Multiplication digital-to-analog conversion circuit - Google Patents
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Abstract
The invention relates to the technical field of digital signal processing, and discloses a multiplication digital-analog conversion circuit shared by an operational amplifier adopting a two-phase unbalanced clock scheme, which comprises a first-stage multiplication digital-analog conversion (MDAC) circuit and a second-stage MDAC circuit, wherein the first-stage MDAC circuit and the second-stage MDAC circuit adopt the same effective digits and redundant digits; the sampling capacitance in the second-stage MDAC circuit is smaller than that in the first-stage MDAC circuit, and the feedback capacitance in the second-stage MDAC circuit is smaller than that in the first-stage MDAC circuit; the residual difference amplification phase time of the first stage MDAC circuit is longer than that of the second stage MDAC circuit. The invention also discloses a pipeline analog-to-digital converter (ADC) of the shared MDAC circuit by applying the two-phase unbalanced clock scheme operational amplifier. The invention makes full use of the power consumption of the operational amplifier in each phase and reduces the waste of the power consumption.
Description
Technical field
The present invention relates to digital signal processing technique field, relate in particular to a kind of multiplication D/A conversion circuit (Multiplying Digital to Analog Circuit, MDAC), and use the low-power consumption of this MDAC circuit production line analog-digital converter (Analog to Digital Circuit, ADC).
Background technology
At present, along with the extensive use of Digital Signal Processing in the communications field, high speed modem, broadband cabled and wireless telecommunication system is increasing to the demand of medium accuracy, high-speed AD converter.In the ADC of various structures, pipeline ADC is widely adopted in distinctive compromise advantage aspect speed, power consumption and the area with it.
As shown in Figure 1, Fig. 1 is the structural representation of traditional pipeline ADC.It by front-end sampling holding circuit, several sub levels (STAGE1, STAGE2 ..., STAGE k-1, FLASH), time-delay SYN register array and digital correction module form.In Fig. 1, except that the low level flash type ADC (being FLASH) of front end S/H circuit and afterbody, all the other are at different levels (STAGE 1, STAGE2 ..., STAGE k-1) all comprise S/H circuit, subnumber weighted-voltage D/A converter (SubDAC), sub-adc converter (SubADC), subtracter and surplus poor amplifier.As shown in Figure 2, Fig. 2 is the structural representation of each sub level in the traditional pipeline ADC structure.
In Fig. 2, ph1 and ph2 are the two-phase clocks that do not overlap, and odd level is controlled sampling with ph1, and even level and front end S/H circuit are controlled sampling with ph2, and promptly the control clock of adjacent two-stage is opposite mutually.Generally the S/H circuit in the sub level shown in Figure 2, subnumber weighted-voltage D/A converter, subtracter and surplus poor amplifier are combined into MDAC.
Pipeline ADC is under two-phase does not overlap clock control, make front end S/H circuit in the pipeline ADC and each streamline sub level sampling mutually and between amplifying mutually alternation finish conversion.Input signal is at first sampled by front end S/H circuit, and in the maintenance stage, the signal that is kept is handled by the sub-adc converter among the STAGE1, produces B
1+ r
1Digit numeric code, the subnumber weighted-voltage D/A converter of sending among the STAGE1 when this digital code is admitted to time-delay SYN register array is converted to analog signal again, and in subtracter, subtract each other with original input signal, the result who subtracts each other is called as surplus poor, and this surplus difference signal multiply by 2 in surplus poor amplifier
R1, being admitted to STAGE2 again and handling, this process repeats up to STAGE k-1 level, and afterbody only carries out analog-to-digital conversion, produces B
kDigit numeric code is sent into time-delay SYN register array, does not carry out surplus difference and amplifies.The digital codes that produce at different levels are exported final digital code then through time-delay SYN register arrays alignings of delaying time after digital correction module is carried out correction process.
High-speed high-precision flow line ADC needs the surplus poor amplifier of high-speed, high precision, this has proposed higher requirement to the amplifier of carrying out surplus difference amplification, and it is high more to the precision and the rate request of amplifier, the power consumption of amplifier is big more, therefore under the certain condition of amplifier power consumption, the number that reduces operational amplifier is very effective for the power consumption that reduces whole ADC.
Fig. 3 is the structural representation that traditional 1.5 bits/level amplifier is shared the MDAC circuit, comprises first order MDAC and second level MDAC.Fig. 4 is the clock scheme that traditional 1.5 bits/level amplifier is shared the MDAC circuit, and ph1 and ph2 are the two-phase clock that do not overlap, and the high level time of ph1 and ph2 is equal substantially, and clock signal ph1e and ph2e represent to shift to an earlier date a little than ph1 and ph2 trailing edge respectively.
In Fig. 3, Cs1 and Cs2 are the sampling capacitance of first order MDAC, and Cf1 and Cf2 are the feedback capacity of first order MDAC; Cs3 and Cs3 are the sampling capacitance of second level MDAC, and Cf3 and Cf4 are the feedback capacity of second level MDAC.In the ph1 phase, first order MDAC samples, and the top crown of Cs1, Cf1 connects common mode, and the sole plate meets input signal in1, and the top crown of Cs2, Cf2 connects common mode, and the sole plate meets input signal in2; Simultaneously, second level MDAC is carrying out surplus difference amplification, and the top crown of Cs3 and Cs4 connects the amplifier differential input end, and the sole plate connects the output of second level subnumber weighted-voltage D/A converter (DAC), the top crown of Cf3 and Cf4 connects the amplifier differential input end, and the sole plate meets difference output out1 and out2.In the ph2 phase, first order MDAC carries out surplus difference and amplifies, and the top crown of Cs1, Cf1 connects the amplifier differential input end, and the sole plate connects the output of first order subnumber weighted-voltage D/A converter (DAC), and Cs2, Cf2 connect the amplifier differential input end, and the sole plate meets difference output out1 and out2; Simultaneously, second level MDAC samples, and the top crown of Cs3 and Cf3 connects common mode, and the sole plate meets the output out1 of first order MDAC, and the top crown of Cs4 and Cf4 connects common mode, and the sole plate meets the output out2 of first order MDAC.
Can see that first order MDAC carries out surplus the difference when amplifying, the sampling capacitance of second level MDAC and feedback capacity are the loads of first order MDAC, and in like manner, the sampling capacitance of third level MDAC and feedback capacity are the loads of second level MDAC.Because the difference of required precision, electric capacity can successively decrease step by step.The sampling capacitance of second level MDAC and feedback capacity are littler than the sampling capacitance and the feedback capacity of the first order, and the load of second level MDAC is also little than the load of first order MDAC.In the amplifier common circuit, the same amplifier of two-stage MDAC circuit, because feedback capacity and the load capacitance of first order MDAC are bigger, so shared amplifier must satisfy the foundation of first order MDAC, like this, when second level MDAC sets up, the nargin that amplifier is set up is bigger, and the second level is lower than the first order to the requirement of setting up precision, adopts clock scheme shown in Figure 4, because the two-phase time is equal substantially, so have certain waste in the partial phase power consumption of setting up.
Summary of the invention
(1) technical problem that will solve
In view of this, the object of the present invention is to provide a kind of MDAC circuit,, reduce the waste of power consumption to make full use of the power consumption of amplifier in each phase.
(2) technical scheme
For achieving the above object, the invention provides a kind of multiplication D/A conversion circuit, this circuit comprises:
First order multiplication D/A conversion circuit is used for carrying out surplus difference amplification to being received from outside differential signal in1 and in2, and differential signal out1_1 and the out2_1 that obtains exported to second level multiplication D/A conversion circuit;
Second level multiplication D/A conversion circuit, be used for the differential signal out1_1 and the out2_1 that are received from first order multiplication D/A conversion circuit are carried out surplus difference amplification, and the differential signal that obtains exported with a pair of difference node out1 and out2 at the another one clock;
Described first order multiplication D/A conversion circuit adopts identical number of significant digit and redundant figure place with second level multiplication D/A conversion circuit; Sampling capacitance is less than sampling capacitance in the first order multiplication D/A conversion circuit in the multiplication D/A conversion circuit of the second level, and feedback capacity is less than feedback capacity in the first order multiplication D/A conversion circuit in the multiplication D/A conversion circuit of the second level; The surplus difference of first order multiplication D/A conversion circuit is amplified the phase time and is amplified the phase time greater than the surplus difference of second level multiplication D/A conversion circuit; Wherein:
Described first order multiplication D/A conversion circuit comprises the first differential switch capacitor cell 2 and the amplifier 1 that connects successively, is used for realizing jointly sampling and the surplus difference amplification of differential signal in1 and in2; The described first differential switch capacitor cell 2 comprises the first feedback capacity Cf1, the first sampling capacitance Cs1, the second feedback capacity Cf2 and the second sampling capacitance Cs2, wherein the first feedback capacity Cf1 is in parallel with the first sampling capacitance Cs1, and is connected in the negative input end opin1 of described amplifier 1; The second feedback capacity Cf2 is in parallel with the second sampling capacitance Cs2, and is connected in the positive input terminal opin2 of described amplifier 1;
Described second level multiplication D/A conversion circuit comprises second switch capacitor cell 3 and the 3rd switching capacity unit 4 that is connected in described amplifier 1 jointly, be used for realizing jointly sampling and the surplus difference amplification of differential signal out1_1 and out2_1, and described first order multiplication D/A conversion circuit and the shared amplifier 1 of described second level multiplication D/A conversion circuit; Described second switch capacitor cell 3 comprises the 3rd feedback capacity Cf3 and the 3rd sampling capacitance Cs3, the 3rd feedback capacity Cf3 and the 3rd sampling capacitance Cs3 parallel connection, and be connected in the negative input end opin1 of described amplifier 1; Described the 3rd switching capacity unit 4 comprises the 4th feedback capacity Cf4 and the 4th sampling capacitance Cs4, the 4th feedback capacity Cf4 and the 4th sampling capacitance Cs4 parallel connection, and be connected in the positive input terminal opin2 of described amplifier 1;
Phs mutually represents the two-phase clock that do not overlap mutually with ph1, and the high level time of phs is less than the high level time of ph1; In the phs phase, first order multiplication D/A conversion circuit is sampled, and the top crown of the first sampling capacitance Cs1, the first feedback capacity Cf1 connects common mode, and the sole plate meets input in1, the top crown of the second sampling capacitance Cs2, the second feedback capacity Cf2 connects common mode, and the sole plate meets input in2; Second level multiplication D/A conversion circuit carries out surplus difference and amplifies, the top crown of the 3rd feedback capacity Cf3 meets the negative input end opin1 of amplifier, the sole plate meets the output out1 of amplifier, the top crown of the 3rd sampling capacitance Cs3 meets the negative input end opin1 of amplifier, the sole plate meets the output DAC2_out1 of digital to analog converter at the corresponding levels respectively, the top crown of the 4th feedback capacity Cf4 meets the positive input terminal opin2 of amplifier, the sole plate meets the output out2 of amplifier, the top crown of the 4th sampling capacitance Cs4 meets the positive input terminal opin2 of amplifier, and the sole plate meets the output DAC2_out2 of digital to analog converter at the corresponding levels;
In the ph1 phase, first order multiplication D/A conversion circuit carries out surplus difference and amplifies, the top crown of the first feedback capacity Cf1 meets the negative input end opin1 of amplifier, the sole plate meets the output out1 of amplifier, the top crown of the first sampling capacitance Cs1 connects common mode, the sole plate meets the output DAC1_out1 of digital to analog converter at the corresponding levels, the top crown of the second feedback capacity Cf2 meets the positive input terminal opin2 of amplifier, the sole plate meets the output out2 of amplifier, the top crown of the second sampling capacitance Cs2 connects common mode, and the sole plate meets the output DAC1_out2 of digital to analog converter at the corresponding levels; Second level multiplication D/A conversion circuit is sampled, the top crown of the 3rd feedback capacity Cf3, the 3rd sampling capacitance Cs3 meets the negative input end opin1 of amplifier, the sole plate meets the output out1 of amplifier, the top crown of the 4th feedback capacity Cf4, the 4th sampling capacitance Cs4 meets the positive input terminal opin2 of amplifier, and the sole plate meets the output out2 of amplifier.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
Utilize the present invention, because the surplus difference of first order MDAC is amplified the phase time and is increased, so under identical sample rate, application is shared the littler amplifier of the used amplifier unity gain bandwidth of MDAC circuit than traditional amplifier can reach the identical requirement of setting up, reduced requirement, thereby reduced power consumption amplifier.Though the surplus difference of second level MDAC is amplified the phase time and is reduced, but the equivalent load capacitance of amplifier was smaller when second level MDAC amplified in surplus difference, when identical number of significant digit and redundant figure place being arranged with first order MDAC, second level MDAC carry out surplus difference when amplifying unity gain bandwidth bigger, and the second level is lower than the first order to the requirement of setting up precision, so by adopting novel clock scheme, balance the set up requirement of two-stage to amplifier, carry out having made full use of when surplus difference is amplified the power consumption of amplifier at second level MDAC.
Description of drawings
Fig. 1 is the structural representation of traditional pipeline ADC;
Fig. 2 is the structural representation of each sub level in the traditional pipeline ADC structure;
Fig. 3 is the structural representation that traditional amplifier is shared the MDAC circuit;
Fig. 4 is the clock scheme that traditional amplifier is shared the MDAC circuit.
Fig. 5 shares the structural representation of MDAC circuit for the two-phase provided by the invention clock scheme amplifier that do not overlap;
Fig. 6 is the used clock scheme of Fig. 5;
Fig. 7 shares the structural representation of the pipeline ADC of MDAC circuit for the application two-phase provided by the invention clock scheme amplifier that do not overlap.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 5, Fig. 5 shares the structural representation of MDAC circuit for the two-phase provided by the invention clock scheme amplifier that do not overlap.This amplifier is shared MDAC and is comprised first order MDAC circuit and second level MDAC circuit.Wherein, first order MDAC circuit is used for carrying out surplus difference amplification to being received from outside differential signal in1 and in2, and differential signal out1_1 and the out2_1 that obtains exported to second level MDAC.Second level MDAC circuit is used for differential signal out1_1 that is received from first order MDAC and out2_1 are carried out surplus difference amplification, and at the another one clock differential signal that obtains is being exported with a pair of difference node out1 and out2.First order MDAC circuit adopts identical number of significant digit and redundant figure place with second level MDAC circuit.Sampling capacitance is less than sampling capacitance in the first order MDAC circuit in the MDAC circuit of the second level, and feedback capacity is less than feedback capacity in the first order MDAC circuit in the MDAC circuit of the second level.The surplus difference of first order MDAC circuit is amplified the phase time and is amplified the phase time greater than the surplus difference of second level MDAC circuit.
Fig. 6 is the used clock scheme of Fig. 5, and wherein, phs, ph1 represent the two-phase clock that do not overlap, and phse, phle represent respectively to shift to an earlier date a little than the trailing edge of phs, ph1, and the high level time of phs is less than the high level time of ph1.Among Fig. 5, the institute's target clock signal above the switch is illustrated in clock signal switch closure when being high.Cs1 and Cs2 are the sampling capacitance of first order MDAC, and Cf1 and Cf2 are the feedback capacity of first order MDAC; Cs3, Cs4 are the sampling capacitance of second level MDAC, and Cf3 and Cf4 are the feedback capacity of second level MDAC.
As shown in Figure 5, opin1 and opin2 represent two inputs of amplifier respectively.In the phs phase, first order MDAC samples, and the top crown of capacitor C s1, Cf1 connects common mode, and the sole plate meets input in1, and the top crown of capacitor C s2, Cf2 connects common mode, and the sole plate meets input in2; Second level MDAC carries out surplus difference and amplifies, the top crown of capacitor C f3 meets the negative input end opin1 of amplifier, the sole plate meets the output out1 of amplifier, the top crown of capacitor C s3 meets the negative input end opin1 of amplifier, the sole plate meets the output DAC2_out1 of digital to analog converter at the corresponding levels respectively, the top crown of capacitor C f4 meets the positive input terminal opin2 of amplifier, the sole plate meets the output out2 of amplifier, the top crown of capacitor C s4 meets the positive input terminal opin2 of amplifier, and the sole plate meets the output DAC2_out2 of digital to analog converter at the corresponding levels.
In the ph1 phase, first order MDAC carries out surplus difference and amplifies, the top crown of capacitor C fi meets the negative input end opin1 of amplifier, the sole plate meets the output out1 of amplifier, and the top crown of capacitor C s1 connects common mode, and the sole plate meets the output DAC1_out1 of digital to analog converter at the corresponding levels, the top crown of capacitor C f2 meets the positive input terminal opin2 of amplifier, the sole plate meets the output out2 of amplifier, and the top crown of capacitor C s2 connects common mode, and the sole plate meets the output DAC1_out2 of digital to analog converter at the corresponding levels; Second level MDAC samples, and the top crown of capacitor C f3, Cs3 meets the negative input end opin1 of amplifier, and the sole plate meets the output out1 of amplifier, and the top crown of capacitor C f4, Cs4 meets the positive input terminal opin2 of amplifier, and the sole plate meets the output out2 of amplifier.
The employing two-phase that provides based on the invention described above clock scheme amplifier that do not overlap is shared the MDAC circuit, the present invention also provides a kind of two-phase clock scheme amplifier that do not overlap of using to share the pipeline ADC of MDAC circuit, and this pipeline ADC comprises flowing water sub level, time-delay SYN register array and digital correction module.
Wherein, the flowing water sub level is used for the analog signal of Vin signal that is received from the ADC input or upper level flowing water sub level is carried out analog-to-digital conversion and surplus difference amplification, the digital signal that obtains is exported to time-delay SYN register array, and analog signal is exported to next stage flowing water sub level.First order flowing water sub level is used for the Vin signal that is received from the ADC input is carried out analog-to-digital conversion and surplus difference amplification in the flowing water sub level, and the numeral that obtains is exported to time-delay SYN register array, and second level flowing water sub level is exported in simulation; Other flowing water sub level is used for the analog signal that receives upper level flowing water sub level is carried out analog-to-digital conversion and surplus difference amplification, and the numeral that obtains is exported to time-delay SYN register array, and next stage flowing water sub level is exported in simulation.Time-delay SYN register array is used for the digital signal that is received from each the flowing water sub level aligning of delaying time is exported to digital correction module with the numeral that obtains.The numeral correction module is used for the digital signal that is received from time-delay SYN register array is carried out shifter-adder, obtains the numeral output of ADC.
As shown in Figure 7, Fig. 7 shares the structural representation of the pipeline ADC of MDAC circuit for the application two-phase provided by the invention clock scheme amplifier that do not overlap.This pipeline ADC is one 10 bit stream waterline ADC, is made up of 9 flowing water sub levels (being STAGE1, STAGE2, STAGE3, STAGE4, STAGE5, STAGE6, STAGE7, STAGE8 and FLASH), time-delay SYN register array and digital correction module.
In Fig. 7, phs and ph1 control each flowing water sub level, and the sequential relationship of phs and ph1 as shown in Figure 6.Odd level STAGE1, STAGE3, STAGE5, STAGE7 and FLASH sample at phs, and even level STAGE2, STAGE4, STAGE6 and STAGE8 sample at ph1.STAGE1, STAGE2 ..., STAGE8 all comprises a sub-adc converter and a MDAC circuit, 2 of every grade of outputs, 1 effectively, redundant digit is used for carrying out digital error correction.Afterbody (FLASH) is the ADC of 2 bit flash structures, exports 2 effectively.
This pipeline ADC comprises 4 amplifiers, wherein, and the shared amplifier of STAGE1 and STAGE2, the shared amplifier of STAGE3 and STAGE4, the shared amplifier of STAGE5 and STAGE6, the shared amplifier of STAGE7 and STAGE8.
Input signal is at first sampled by STAGE1, and handle by the sub-adc converter among the STAGE1, produce 2 digit numeric codes, the MDAC circuit of sending into STAGE1 when this digital code is admitted to time-delay SYN register sequence produces the surplus difference signal that amplifies and sends into STAGE2 and handle, this process repeats until the 8th grade, afterbody only carries out analog-to-digital conversion, produces 2 digit numeric codes and sends into time-delay SYN register sequence, does not carry out surplus difference and amplifies.All that produce 18 digit numeric codes at different levels are handled through digital correction module then and are exported 10 final digit numeric codes through time-delay SYN register sequences alignings of delaying time.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (1)
1. a multiplication D/A conversion circuit is characterized in that, this circuit comprises:
First order multiplication D/A conversion circuit is used for carrying out surplus difference amplification to being received from outside differential signal in1 and in2, and differential signal out1_1 and the out2_1 that obtains exported to second level multiplication D/A conversion circuit;
Second level multiplication D/A conversion circuit, be used for the differential signal out1_1 and the out2_1 that are received from first order multiplication D/A conversion circuit are carried out surplus difference amplification, and the differential signal that obtains exported with a pair of difference node out1 and out2 at the another one clock;
Described first order multiplication D/A conversion circuit adopts identical number of significant digit and redundant figure place with second level multiplication D/A conversion circuit; Sampling capacitance is less than sampling capacitance in the first order multiplication D/A conversion circuit in the multiplication D/A conversion circuit of the second level, and feedback capacity is less than feedback capacity in the first order multiplication D/A conversion circuit in the multiplication D/A conversion circuit of the second level; The surplus difference of first order multiplication D/A conversion circuit is amplified the phase time and is amplified the phase time greater than the surplus difference of second level multiplication D/A conversion circuit; Wherein:
Described first order multiplication D/A conversion circuit comprises the first differential switch capacitor cell (2) and the amplifier (1) that connects successively, is used for realizing jointly sampling and the surplus difference amplification of differential signal in1 and in2; The described first differential switch capacitor cell (2) comprises the first feedback capacity Cf1, the first sampling capacitance Cs1, the second feedback capacity Cf2 and the second sampling capacitance Cs2, wherein the first feedback capacity Cf1 is in parallel with the first sampling capacitance Cs1, and is connected in the negative input end opin1 of described amplifier (1); The second feedback capacity Cf2 is in parallel with the second sampling capacitance Cs2, and is connected in the positive input terminal opin2 of described amplifier (1);
Described second level multiplication D/A conversion circuit comprises second switch capacitor cell (3) and the 3rd switching capacity unit (4) that is connected in described amplifier (1) jointly, be used for realizing jointly sampling and the surplus difference amplification of differential signal out1_1 and out2_1, and described first order multiplication D/A conversion circuit and the shared amplifier (1) of described second level multiplication D/A conversion circuit; Described second switch capacitor cell (3) comprises the 3rd feedback capacity Cf3 and the 3rd sampling capacitance Cs3, the 3rd feedback capacity Cf3 and the 3rd sampling capacitance Cs3 parallel connection, and be connected in the negative input end opin1 of described amplifier (1); Described the 3rd switching capacity unit (4) comprises the 4th feedback capacity Cf4 and the 4th sampling capacitance Cs4, the 4th feedback capacity Cf4 and the 4th sampling capacitance Cs4 parallel connection, and be connected in the positive input terminal opin2 of described amplifier (1);
Phs mutually represents the two-phase clock that do not overlap mutually with phl, and the high level time of phs is less than the high level time of phl; In the phs phase, first order multiplication D/A conversion circuit is sampled, and the top crown of the first sampling capacitance Cs1, the first feedback capacity Cf1 connects common mode, and the sole plate meets input in1, the top crown of the second sampling capacitance Cs2, the second feedback capacity Cf2 connects common mode, and the sole plate meets input in2; Second level multiplication D/A conversion circuit carries out surplus difference and amplifies, the top crown of the 3rd feedback capacity Cf3 meets the negative input end opin1 of amplifier, the sole plate meets the output out1 of amplifier, the top crown of the 3rd sampling capacitance Cs3 meets the negative input end opin1 of amplifier, the sole plate meets the output DAC2_out1 of digital to analog converter at the corresponding levels respectively, the top crown of the 4th feedback capacity Cf4 meets the positive input terminal opin2 of amplifier, the sole plate meets the output out2 of amplifier, the top crown of the 4th sampling capacitance Cs4 meets the positive input terminal opin2 of amplifier, and the sole plate meets the output DAC2_out2 of digital to analog converter at the corresponding levels;
In the phl phase, first order multiplication D/A conversion circuit carries out surplus difference and amplifies, the top crown of the first feedback capacity Cf1 meets the negative input end opin1 of amplifier, the sole plate meets the output out1 of amplifier, the top crown of the first sampling capacitance Cs1 connects common mode, the sole plate meets the output DAC1_out1 of digital to analog converter at the corresponding levels, the top crown of the second feedback capacity Cf2 meets the positive input terminal opin2 of amplifier, the sole plate meets the output out2 of amplifier, the top crown of the second sampling capacitance Cs2 connects common mode, and the sole plate meets the output DAC1_out2 of digital to analog converter at the corresponding levels; Second level multiplication D/A conversion circuit is sampled, the top crown of the 3rd feedback capacity Cf3, the 3rd sampling capacitance Cs3 meets the negative input end opin1 of amplifier, the sole plate meets the output out1 of amplifier, the top crown of the 4th feedback capacity Cf4, the 4th sampling capacitance Cs4 meets the positive input terminal opin2 of amplifier, and the sole plate meets the output out2 of amplifier.
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| US8643432B1 (en) * | 2012-07-27 | 2014-02-04 | Hong Kong Applied Science & Technology Research Institute Company Ltd. | Op-Amp sharing by swapping trans-conductance cells |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6653961B1 (en) * | 2002-05-08 | 2003-11-25 | Analog Devices, Inc. | Multiplying digital-to-analog converter structures that reduce signal distortion |
| CN1794588A (en) * | 2005-12-20 | 2006-06-28 | 威盛电子股份有限公司 | Circulation flow line type analog digital converter |
| US20060187108A1 (en) * | 2005-02-21 | 2006-08-24 | Lg Electronics Inc. | Reference voltage driving circuit and pipelined analog to digital converter including same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6653961B1 (en) * | 2002-05-08 | 2003-11-25 | Analog Devices, Inc. | Multiplying digital-to-analog converter structures that reduce signal distortion |
| US20060187108A1 (en) * | 2005-02-21 | 2006-08-24 | Lg Electronics Inc. | Reference voltage driving circuit and pipelined analog to digital converter including same |
| CN1794588A (en) * | 2005-12-20 | 2006-06-28 | 威盛电子股份有限公司 | Circulation flow line type analog digital converter |
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