CN101286530A - polysilicon thin film transistor - Google Patents

Abstract

The invention discloses a polysilicon thin film transistor. It mainly solves the problems of poor performance and high saturation voltage of current polysilicon thin film devices. The whole device includes a glass substrate, a gate electrode, a drain electrode and a source electrode, wherein the gate electrode is located above the glass substrate, and the length of the gate electrode covers the channel length between the source electrode and the source and drain to simultaneously control the source electrode and the channel length. road area. A Si ₃ N ₄ dielectric layer is deposited on the gate electrode, and the length of the Si ₃ N ₄ dielectric layer covers the entire gate electrode and the drain electrode. Intrinsic polysilicon film is deposited on the Si ₃ N ₄ dielectric layer, the source and the drain are respectively set at both ends, and the source is made of Schottky metal, and the height of the Schottky barrier of the source electrode is controlled by the gate voltage. And then control the size of the current in the device. The invention is 10 times lower than the saturation voltage of the conventional polysilicon thin film device, under the same bias condition, the on-state current of the conventional polysilicon thin film transistor is increased by more than 50%, and can be used for the switch of the active matrix array liquid crystal display.

Description

polysilicon thin film transistor

technical field

The invention belongs to the field of electronic components, and relates to semiconductor devices, in particular to a polysilicon thin film structure.

Background technique

In the late 1980s, the combination of microelectronics technology and liquid crystal display formed an active matrix liquid crystal display AMLCD. Since the definition and color quality of AMLCD can be compared with the traditional picture tube CRT, and it has the advantages of small size, light weight, low power consumption, and no X-ray radiation, it has become a replacement product of display technology and is developing very rapidly. AMLCD requires a switching element for each pixel unit, such as 480×640 pixel units, within a larger area, such as 3 inches to 9 inches, and the array of switching elements must be made on a light-transmitting substrate Therefore, conventional transistor MOS integrated circuit technology is difficult to do. In order to meet the needs of AMLCD, people have studied many types of switching element arrays, but currently only the two-terminal device metal-insulator-metal diode MIM array, the three-terminal device amorphous silicon thin film transistor a-Si TFT array and polysilicon Thin film transistor Poly-Si TFT array. In terms of high-quality video display, only thin-film transistor-driven AMLCD can compete with CRT.

The world's first thin-film transistor AMLCD TV display is made of amorphous silicon. Amorphous silicon thin films can be deposited at lower temperatures, such as 300-400°C. The substrate material can be ordinary glass, and the process cost is low. In addition, the switching performance of a-Si TFT is better than that of the two-terminal device MIM array. The a-Si TFT array has become the mainstream technology adopted by the current AMLCD, and has been used in large-screen projection TVs, pocket TVs, portable computers and other fields. However, due to the low mobility and poor stability of carriers in amorphous silicon TFT devices under voltage stress and light conditions, it has become a technical bottleneck for the development of displays. Since the mobility of polysilicon TFT devices is higher than that of amorphous silicon TFTs, and the parasitic effect is small, polysilicon TFTs have shown great advantages in the case of large-screen and small-screen displays that are difficult for amorphous silicon TFTs to meet. .

The typical structure of a polysilicon TFT is shown in Figure 1: an intrinsic polysilicon film is deposited on an insulating material substrate, such as glass, and the source and drain regions are formed by ion implantation, followed by a gate insulating layer, such as _SiO2 and gate , such as heavily doped polysilicon. The structure of polysilicon TFT is similar to that of MOS field effect transistor, especially the structure of fully depleted SOI MOS transistor. The main difference is the substrate material. Polysilicon thin film transistors are not based on single crystal silicon, but use low-cost transparent Light glass as the substrate. In MOS transistors, thermally oxidized SiO ₂ gate dielectric layers are generally used. However, a large number of experiments have proved that Si ₃ N ₄ deposited by low-temperature PECVD method has many advantages as the gate dielectric of polysilicon thin film transistors, such as better radiation resistance, A higher barrier height can suppress impurity punch-through, better anti-breakdown characteristics, etc. Similar to the field effect transistor of the crystal, when a voltage is applied to the gate, a conductive channel will be induced to form, and the current between the source and drain can be controlled by adjusting the gate voltage. When the applied drain voltage depletes the channel carriers at the drain, the channel is pinched off and the drain current reaches saturation. After the channel is pinched off, the drain voltage continues to be applied. The output impedance of the field effect transistor is determined by the effective channel length from the source to the pinch-off point. As the drain voltage increases, the electric field in the channel increases, thereby increasing the channel conductance. As the channel length of the polysilicon TFT shrinks, the electric field at the drain increases sharply. Since there are a large number of grain boundaries in the polysilicon film, the high electric field at the drain end emits field through the trap state, and the leakage current increases sharply, which becomes an important factor affecting the performance improvement of the field effect transistor. An effective measure to reduce the off-state current of polysilicon TFT devices is to reduce the high electric field at the drain. For this reason, many improved devices have been proposed, such as compensation gate structure, LDD structure, field-induced drain junction structure and so on. When the polysilicon TFT is in the off state, compared with the traditional polysilicon TFT device, the electric field at the drain end of these devices is reduced, so the leakage current is reduced, which effectively improves the performance of the polysilicon TFT. However, when the polysilicon thin film transistor is in the on state, the parasitic series resistance of these devices is too high, which inhibits the improvement of the on state current. Polysilicon TFT devices are used as switching devices in AMLCD, and their performance is characterized by the ratio of on-state current to off-state current. Therefore, only the reduction of the off-state current or only the increase of the on-state current cannot be said to be an ideal device structure. Therefore, it is urgent to find a more effective TFT device structure, by increasing the ratio of on-state current to off-state current, to improve device performance and promote the further development of AMLCD.

content of the invention

The purpose of the present invention is to overcome the deficiencies of polysilicon thin film devices, to provide a polysilicon thin film transistor structure and preparation method with a large ratio of on-state current to off-state current, so as to improve the performance of polysilicon thin film transistors

The technical idea of the present invention is to refer to the structure of silicon-based devices. Schottky barrier MOS devices have been successfully prepared in silicon-based devices. The source and drain of this device do not use heavily doped regions, but silicided The source and drain are separated by two back-to-back Schottky barriers, and the drain current depends on the tunneling of electrons through the entire barrier. A large number of experiments have proved that the Schottky contact effectively reduces the short-channel effect and parasitic bipolar effects that plague conventional field effect transistors when the device size is greatly reduced, such as parasitic series resistance and capacitance. In the on state, the thickness of the barrier near the source region under the gate is thinned, and the tunneling current rises sharply with the decrease of the barrier thickness, so that the source and drain flow a significant current; in the off state, the Schott of the source reverse bias The space charge region of the base junction is thicker, the tunneling current through the potential barrier is very small, and the current flowing through the source and drain is even smaller. Therefore, the ratio of the on-state current to the off-state current is greatly increased, and the performance of the device is improved. In addition, its process is much simpler than the ion implantation process, and will not affect the crystal lattice of the material, which is conducive to improving the characteristics of the device. Inspired by the silicon-based Schottky barrier MOS device, we consider whether the Schottky barrier can also be applied in polysilicon TFT to improve the performance of the device. In this way, the high electric field at the drain terminal can be reduced without adding an additional process, the parasitic high series resistance can be eliminated, the on-state current can be increased and the leakage current can be reduced. However, a factor that has to be considered is that polysilicon is easy to recrystallize at the interface between the Schottky source and drain and polysilicon, so that grain boundaries may still appear in the entire active region, making the film quality worse. In addition, from the influence of source and drain parasitic series resistance on the performance of devices and circuits, it can be known that the series resistance of the source region has a more serious impact on devices and circuits. Starting from these two factors, the present invention considers to modify the device structure on the basis of the original Schottky source-drain structure, so that the negative impact is smaller and the advantages are more prominent.

According to the above ideas, the device structure of the present invention includes: a glass substrate, a gate electrode, a drain electrode and a source electrode, wherein the gate electrode is located above the glass substrate, and a Si ₃ N ₄ dielectric layer is deposited on the gate electrode, An intrinsic polysilicon film is deposited on the Si ₃ N ₄ dielectric layer; the source electrode adopts a Schottky metal electrode and is located above the intrinsic polysilicon film.

In the above polysilicon thin film transistor, the length of the gate electrode covers the length of the channel between the source electrode and the source-drain, so as to control the source electrode and the channel region at the same time.

In the above polysilicon thin film transistor, the thickness of the Si ₃ N ₄ dielectric layer is 50-300 nm, and the length covers the entire gate electrode and drain electrode.

In the above polysilicon thin film transistor, a Si ₃ N ₄ dielectric layer is simultaneously deposited on the glass substrate at one end of the gate electrode.

The present invention makes the method for polysilicon thin film transistor, comprises following process:

(1) Sputter a layer of chromium metal on the glass substrate, etch the metal grid and form the gate electrode;

(2) On the gate metal electrode and the substrate at one end of the gate metal electrode, deposit a 50-300 nm thick Si ₃ N ₄ gate dielectric layer at 200-350° C. by plasma enhanced chemical vapor deposition method PECVD;

(3) On the Si ₃ N ₄ gate dielectric layer, first use the PECVD method to deposit the active region of the intrinsic amorphous silicon film at 200-350 ° C, and then scan and anneal to recrystallize the amorphous silicon into polysilicon, and Use 10KeV, 1×10 ¹⁴ cm ^-2 phosphorus on the surface of polysilicon for barrier adjustment doping;

(4) Phosphorus ion implantation is first performed on the surface of one end of phosphorus-doped polysilicon to form an n ⁺ polysilicon drain contact region, and aluminum is deposited as a drain ohmic contact electrode; then chromium is deposited to form a Schottky source contact electrode;

(5) Perform compensatory doping with 12KeV, 2×10 ¹³ cm ^-2 BF ₂ between the source and drain metal electrodes to adjust the phosphorus ions formed in the channel region during doping due to barrier adjustment;

(6) A polysilicon thin film transistor is formed by annealing and passivating with nitrogen at a temperature of 250°C.

In the present invention, due to the use of the bottom gate structure process, that is, the gate electrode and the Si ₃ N ₄ gate dielectric layer are located below the active region of the intrinsic polysilicon film, the characteristics of the interface between Si ₃ N ₄ and the polysilicon film are better, and the interface state trap density lower; at the same time because the present invention uses the length of the gate electrode to cover the channel length between the source electrode and the source drain, it can control the source electrode and the channel region at the same time; in addition, because the source electrode uses Schottky metal, it can pass The gate voltage applied to the gate electrode is used to control the height of the Schottky barrier of the source electrode. When the drain depletion layer expands to the polysilicon/gate dielectric layer interface with the increase of the drain voltage, the current is saturated, and the corresponding drain voltage To saturate the drain voltage V _SAT , the drain voltage further increases, and the drain depletion layer expands toward the drain electrode, but it has little effect on the height of the Schottky barrier, and the short channel effect of the device is greatly improved; in addition, due to After the polysilicon thin film transistor reaches a saturated state, the height of the reverse-biased Schottky barrier can be controlled by the gate voltage, which can increase the on-state current and reduce the off-state current, that is, the ratio of the on-state current to the off-state current increases, thereby improving the performance of the device. performance.

Simulation results show that the polysilicon thin film transistor of the present invention has lower saturation voltage and higher output impedance, and its saturation voltage is 10 times lower than that of conventional polysilicon thin film transistors. Under the same bias condition, the on-state current of the conventional polysilicon thin film transistor is increased by more than 50%, and the ratio of the on-state current to the off-state current is greater than 10 ^-9 .

Description of drawings

Fig. 1 is a schematic diagram of the structure of a conventional polysilicon TFT device;

Fig. 2 is a schematic diagram of the device structure of the present invention;

Fig. 3 is a schematic diagram of the main process steps for preparing the device of the present invention;

Fig. 4 is the simulation diagram of the threshold voltage of the device of the present invention under different gate dielectric Si ₃ N ₄ thickness T _ins ;

Fig. 5 is the IV characteristic simulation diagram of the device of the present invention under different gate dielectric Si ₃ N ₄ thickness T _ins ;

Fig. 6 (a) is the simulation diagram of the output characteristics of the device of the present invention under different gate voltages _Vgs ;

Figure 6(b) is a simulation diagram of the output characteristics of conventional polysilicon thin film transistors under different gate voltages V _gs

Fig. 7 (a) is under different grid voltage V _gs to the electronic distribution simulation figure of device of the present invention;

Figure 7(b) is a simulation diagram of the electron distribution of a conventional polysilicon thin film transistor under different gate voltages V _gs ;

Fig. 8 (a) is the simulation diagram of the output characteristics of the device of the present invention under different channel lengths d;

Figure 8(b) is a simulation diagram of the output characteristics of a conventional polysilicon thin film transistor under different channel lengths d;

Fig. 9 is a simulation diagram of the transfer characteristics of the device of the present invention under different potential barrier heights Φ _b .

Detailed ways

With reference to Fig. 2, the device of the present invention is mainly made of glass substrate, gate electrode, drain electrode and source electrode, wherein on the glass substrate is deposited with thickness be 100-200nm gate electrode, the length of gate electrode covers source electrode and source drain The channel length between to control the potential of the source electrode and the channel region simultaneously. A Si ₃ N ₄ dielectric layer with a thickness of 50-300nm is deposited on the upper surface of the gate electrode, and a Si ₃ N ₄ dielectric layer with a thickness of 150-500nm is also deposited on the glass substrate at one end of the gate electrode. The Si ₃ N ₄ dielectric layer The length covers the entire gate electrode and drain electrode. The intrinsic polysilicon thin film Poly-Si with a thickness of 100-300 nm is deposited on the Si ₃ N ₄ dielectric layer. One end of the polysilicon film is a heavily doped drain region with a phosphorus ion concentration greater than 10 ¹⁹ cm ^-3 , on which is a 100-200nm aluminum ohmic contact electrode. The other end of the polysilicon film is a Schottky source electrode formed of chromium metal with a thickness of 100-200nm. The channel length d between the source and drain is 0.5-2 μm, the length s of the source electrode is 4 μm, the length of the drain electrode is the same as that of the source electrode, and the length L of the gate electrode is the sum of the channel length d and the source electrode length s.

The working principle of the device of the present invention is to control the Schottky barrier height of the source end by the reverse bias voltage applied to the gate electrode. When the drain voltage reaches saturation, the depletion layer at the drain end reaches the interface between the Si ₃ N ₄ dielectric layer and the polysilicon film, further increasing the drain voltage, and the depletion layer expands toward the drain electrode, which has little effect on the Schottky barrier at the source end. At this time, the height of the Schottky barrier at the source is changed by applying a gate voltage, and the carriers passing through the Schottky barrier are controlled to change the current of the device.

With reference to Fig. 3, the preparation process of device of the present invention is as follows:

Example 1

(1) Sputter a layer of chromium metal with a thickness of 100 nm on the glass substrate, etch a metal grid with a length of 4.5 μm, and form a grid electrode;

(2) On the gate metal electrode and the glass substrate at one end of the gate metal electrode, use the plasma enhanced chemical vapor deposition method PECVD to deposit the Si ₃ N ₄ gate dielectric layer, the deposition temperature is 200 ° C, deposit on the gate metal electrode The deposited Si ₃ N ₄ has a thickness of 50nm, and the Si ₃ N ₄ deposited at one end of the gate metal electrode has a thickness of 150nm;

(3) On the Si ₃ N ₄ gate dielectric layer, the active region of the intrinsic amorphous silicon film was deposited at 200°C by PECVD method, and then the surface of the film was scanned by XeCl excimer pulse laser, and then at room temperature and in an inert gas atmosphere. Lower annealing to recrystallize amorphous silicon into polysilicon, then dry etch the polysilicon, and carve small islands in Si ₃ N ₄ to form contact holes for gate electrodes;

(4) Use 10KeV phosphorus at a dose of 1×10 ¹⁴ cm ^-2 on the polysilicon surface for barrier adjustment doping, and perform phosphorus ion implantation on the surface of one end of the phosphorus doped polysilicon to form an ion concentration greater than 10 ¹⁹ cm ^-3 The n ⁺ polysilicon drain contact region, and then deposit aluminum and chromium with a thickness of 100nm, respectively, as the drain ohmic contact electrode and the Schottky source contact electrode;

(5) Perform compensatory doping with 12KeV, 2×10 ¹³ cm ^-2 BF ₂ between the source and drain metal electrodes to adjust the phosphorus ions formed in the channel region during doping due to barrier adjustment;

(6) Perform annealing and passivation with nitrogen gas at a pressure of 2 Torr and a temperature of 250° C., and drill holes to lead out electrode solder joints to form polysilicon thin film transistors.

Example 2

(1) Sputter a layer of molybdenum metal with a thickness of 150 nm on the glass substrate, etch a metal grid with a length of 5 μm, and form a grid electrode;

(2) On the gate metal electrode and the substrate at one end of the gate metal electrode, use the plasma enhanced chemical vapor deposition method PECVD to deposit the Si ₃ N ₄ gate dielectric layer, the deposition temperature is 250 ° C, and deposit on the gate metal electrode The thickness of Si ₃ N ₄ is 100nm, and the thickness of Si ₃ N ₄ deposited at one end of the gate metal electrode is 250nm;

(3) On the Si ₃ N ₄ gate dielectric layer, first use the PECVD method to deposit the active region of the intrinsic amorphous silicon film at 250 ° C, and then recrystallize the amorphous silicon into polysilicon by scanning and annealing, and then use dry Etch polysilicon by etching, and carve small islands in Si ₃ N ₄ to form contact holes for gate electrodes;

(4) Use 10KeV phosphorus at a dose of 1×10 ¹⁴ cm ^-2 on the polysilicon surface for barrier adjustment doping, and perform phosphorus ion implantation on the surface of one end of the phosphorus doped polysilicon to form an ion concentration greater than 10 ¹⁹ cm ^-3 The n ⁺ polysilicon drain contact region, and then deposit aluminum and chromium with a thickness of 150nm, respectively, as the drain ohmic contact electrode and the Schottky source contact electrode;

(5) Perform compensatory doping with 12KeV, 2×10 ¹³ cm ^-2 BF ₂ between the source and drain metal electrodes to adjust the phosphorus ions formed in the channel region during doping due to barrier adjustment;

(6) Perform annealing and passivation with nitrogen gas at a pressure of 2 Torr and a temperature of 250° C., and drill holes to lead out electrode solder joints to form polysilicon thin film transistors.

Example 3

(1) Sputter a layer of chromium metal with a thickness of 200nm on the glass substrate, etch a metal grid with a length of 6 μm, and form a grid electrode;

(2) On the gate metal electrode and the glass substrate at one end of the gate metal electrode, use the plasma enhanced chemical vapor deposition method PECVD to deposit the Si ₃ N ₄ gate dielectric layer, the deposition temperature is 350 ° C, and deposit on the gate metal electrode The deposited Si ₃ N ₄ has a thickness of 300nm, and the Si ₃ N ₄ deposited at one end of the gate metal electrode has a thickness of 500nm;

(3) On the Si ₃ N ₄ gate dielectric layer, the active region of the intrinsic amorphous silicon film was deposited at 350°C by PECVD method, and then the surface of the film was scanned by XeCl excimer pulse laser, and then at room temperature and in an inert gas atmosphere. Lower annealing to recrystallize amorphous silicon into polysilicon, then dry etch the polysilicon, and carve small islands in Si ₃ N ₄ to form contact holes for gate electrodes;

(4) Use 10KeV phosphorus at a dose of 1×10 ¹⁴ cm ^-2 on the polysilicon surface for barrier adjustment doping, and perform phosphorus ion implantation on the surface of one end of the phosphorus doped polysilicon to form an ion concentration greater than 10 ¹⁹ cm ^-3 The n ⁺ polysilicon drain contact region, and then deposit aluminum and chromium with a thickness of 200nm, respectively, as the drain ohmic contact electrode and the Schottky source contact electrode;

(5) Perform compensatory doping with 12KeV, 2×10 ¹³ cm ^-2 BF ₂ between the source and drain metal electrodes to adjust the phosphorus ions formed in the channel region during doping due to barrier adjustment;

(6) Perform annealing and passivation with nitrogen gas at a pressure of 2 Torr and a temperature of 250° C., and drill holes to lead out electrode solder joints to form polysilicon thin film transistors.

Effect of the present invention can be further illustrated by following simulation:

Simulation conditions:

A. change the device channel length d of the present invention, Si ₃ N ₄ dielectric layer thickness T _ins , grain size Lg and Schottky barrier height Φ _b to obtain the electrical characteristics of the device of the present invention;

B. Change the channel length d of the conventional polysilicon device to obtain the electrical characteristics of the conventional device;

C. The drift-diffusion transport model, the band-band tunneling model starting from the tail of the state density and the carrier mobility model are used in the simulation process, and the carrier mobility model is selected to be related to channel doping, high Field saturation effect, interface mobility degradation parameters between polysilicon and insulating medium;

D: In the simulation process, the interface between the source electrode of the device of the present invention and the polysilicon is defined as a Schottky barrier.

Simulation 1

Assuming that the gate electrode length s=4 μm, the channel length d=2 μm, and the Schottky barrier height Φ _b =0.3 eV, a simulated device is generated by the device description tool MDRAW of the two-dimensional device numerical simulator ISE.

A gate voltage V _gs of 0-1V is applied to the device in the device simulation tool DESSIS, and the transfer characteristic simulation curve and threshold voltage of the device of the present invention are obtained through the visualization tool INSPECT, as shown in FIG. 4 . Fig. 4 shows the effect on the threshold voltage of the device of the present invention when the thickness of the gate dielectric Si ₃ N ₄ is 50nm, 100nm, 200nm, 300nm, and the grain size Lg is 0.1-0.6μm. It can be seen from FIG. 4 that when the thickness of the gate dielectric layer is 100nm, the grain boundary has little influence on the threshold voltage. When the thickness of the gate dielectric layer is 50nm, since the Si ₃ N ₄ is too thin, the poor quality Si ₃ N ₄ initially grown has a great influence on the polysilicon film, so the threshold voltage drifts greatly.

A gate voltage V _gs of 0-8V is applied to the device in DESSIS, and the transfer characteristic simulation curve of the device of the present invention is obtained through INSPECT, as shown in FIG. 5 . Fig. 5 has provided gate dielectric Si ₃ N ₄ when the thickness is 100nm, 200nm, 300nm respectively, when grain size is respectively 0.1 μm, 0.3 μm and 0.6 μm, influence on device IV characteristic of the present invention, as can be seen from Fig. 5, when Si When the thickness of ₃ N ₄ is 100nm, the transfer characteristic curve is the best.

Simulation 2

In the device of the present invention, the gate length s=4μm, the channel length d=2μm, the Schottky barrier height _Φb =0.3eV, and 2V, 4V, 6V and 8V are respectively applied by using the two-dimensional device numerical simulator ISE The output characteristic curve of the gate voltage V _gs is shown in Figure 6(a), and the distribution of electrons along the channel is shown in Figure 7(a)

In a conventional polysilicon thin film transistor, if the length of the source and drain electrodes is 4 μm, and the channel length d=2 μm, the output characteristic curve is shown in Figure 6(b), and the distribution of electrons along the channel is shown in Figure 7(b) shown.

From Fig. 6 (a) and Fig. 6 (b) comparative result shows: the device of the present invention has lower saturation voltage, about 0.3V, 10 times lower than the saturation voltage of conventional polysilicon thin film device, this is based on organic light-emitting diode The access display has important significance; the on-state current of the device of the invention is very large, and under the same bias condition, the on-state current of the conventional polysilicon thin film transistor is increased by more than 50%.

The comparison results from Fig. 7(a) and Fig. 7(b) show that the electron concentration at the source end of the device of the present invention is low, and the excess carrier concentration decreases as the drain voltage increases. Therefore, the electron concentration is lower not only at the source but also throughout the channel. The lower the excess carrier concentration in the device, the less likely defects will form.

In summary, it can be seen that the performance of the device of the present invention is much more stable than that of conventional devices.

Simulation 3

In the device of the present invention, the source electrode length s=4μm, the Schottky barrier height _Φb =0.3eV, the channel lengths d are 0.5μm, 1μm and 2μm respectively, and the gate voltage V _gs is 2V, 4V and 6V respectively and 8V, when the drain voltage V _ds is 0-8V, the simulation of the output characteristics of the device of the present invention is shown in Figure 8(a).

In a conventional device, when the channel length L is set to be 0.5 μm, 1 μm and 2 μm, the gate voltage V _gs is 2 V, 4 V, 6 V and 8 V, and the drain voltage V _ds is 0-8 V, the output of the conventional polysilicon thin film device The characteristic simulation is shown in Fig. 8(b).

The comparison results of Fig. 8(a) and Fig. 8(b) show that in the device of the present invention, as the channel length d shortens, the magnitude of the leakage current under the same gate voltage is almost the same, and the range of the saturation voltage is very small, even if the channel length d is shortened. The channel length d is reduced to 0.5 μm, and the device still has good performance, indicating that the device of the present invention is less sensitive to the short channel effect and is hardly affected by it; while in conventional polysilicon thin film devices, as the channel length L shortening, the current and the conductance in the channel increase rapidly. When the gate voltage Vgs is 6V, the output curve of the channel length L=0.5μm device has obvious warping phenomenon, showing a serious short channel effect.

In summary, even if the channel is reduced to a submicron scale, the device of the present invention can still maintain high performance and high output impedance.

Simulation 4

In the device of the present invention, assuming that the source electrode length s=4 μm, the channel length d=0.5 μm, and the Schottky barrier height Φ _b are respectively 0.1eV, 0.2eV, 0.3eV and 0.4eV, the transfer characteristic curve is shown in Figure 9 .

It can be seen from Figure 9 that the source-drain current increases rapidly as the Schottky barrier height Φ _b decreases. The off-state current is almost the same for all barrier heights, but the ratio of on-state current I _on to off-state current I _off is higher for devices with lower barrier heights.

From the above results, it can be seen that the performance of the device can be improved by optimizing the Schottky barrier height Φ _b in practice.

Claims (6)

1. a polycrystalline SiTFT comprises glass substrate, gate electrode, drain electrode and source electrode, it is characterized in that:

Described gate electrode is positioned at the glass substrate top, and this is deposited with Si above gate electrode ₃N ₄Dielectric layer, Si ₃N ₄Be deposited with the intrinsic polysilicon film on the dielectric layer;

Described source electrode adopts the schottky metal electrode, is positioned at the top of intrinsic polysilicon film.

2. polycrystalline SiTFT according to claim 1 is characterized in that the length covering source electrode of gate electrode and the channel length between the leakage of source, with while Controlling Source electrode and channel region.

3. polycrystalline SiTFT according to claim 1 and 2 is characterized in that Si ₃N ₄Dielectric layer covers whole gate electrode and drain electrode.

4. polycrystalline SiTFT according to claim 1 is characterized in that being deposited with Si simultaneously on the glass substrate of gate electrode one end ₃N ₄Dielectric layer.

5. method for preparing polycrystalline SiTFT comprises following process:

(1) sputter one layer thickness is chromium or the molybdenum of 100-200nm on glass substrate, and etching length is 4.5-6 μ m metal gate and forms gate electrode;

(2) on the substrate of grid metal electrode and grid metal electrode one end, utilize plasma-reinforced chemical vapor deposition method PECVD deposition thickness to be respectively the Si of 50-300nm and 150-500nm ₃N ₄Gate dielectric layer, deposition temperature are 200-350 ℃;

(3) at Si ₃N ₄Utilize PECVD method deposition of intrinsic amorphous silicon membrane active area under 200-350 ℃ temperature on the gate dielectric layer earlier, by scanning, annealing, making the amorphous silicon recrystallization is polysilicon again, and at polysilicon surface 10KeV, dosage 1 * 10 ¹⁴Cm ^-2Phosphorus carry out the potential barrier adjustment and mix;

(4) carry out phosphonium ion earlier on the surface of phosphor doped polysilicon one end and inject, form phosphate ion concentration greater than 10 ¹⁹Cm ^-3N ⁺Polysilicon drain contact district, and deposition thickness is that the aluminium of 100-200nm is as leaking Ohm contact electrode; Deposition thickness is the chromium formation Schottky source contact electrode of 100-200nm again;

(5) between source leakage metal electrode, use 12KeV, 2 * 10 ¹³Em ^-2BF ₂Compensate doping, the phosphonium ion that forms at channel region when mixing because of the potential barrier adjustment with adjustment;

(6) usefulness nitrogen by annealing, passivation, punching extraction electrode solder joint, forms polycrystalline SiTFT under 250 ℃ of temperature.

6. the method for preparing polycrystalline SiTFT according to claim 5, wherein the preferred parameter of step (2) and step (3) is:

The Si of deposit on the grid metal electrode ₃N ₄Gate dielectric layer thickness is 100nm;

At Si ₃N ₄The temperature of deposit assertive evidence polysilicon membrane is 250 ℃ on the gate dielectric layer.

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