CN101271923B

CN101271923B - Thin-film transistor

Info

Publication number: CN101271923B
Application number: CN2007100897498A
Authority: CN
Inventors: 赖钦诠; 吴泉毅; 蔡依芸
Original assignee: Chunghwa Picture Tubes Ltd
Current assignee: Chunghwa Picture Tubes Ltd
Priority date: 2007-03-23
Filing date: 2007-03-23
Publication date: 2010-12-08
Anticipated expiration: 2027-03-23
Also published as: CN101271923A

Abstract

The invention discloses a film transistor, which comprises a baseplate, a grid, a grid isolation layer, a semiconductor layer, an ohm contact layer, a source electrode and a brain electrode, wherein, the grid is arranged on the baseplate, and the grid isolation layer is arranged on the baseplate and covers the grid. The semiconductor layer is arranged on the grid isolation layer and located over the grid. The semiconductor layer consists of a non-doping amorphous silicon layer and a first non-doping microcrystalline silicon layer, wherein, the first non-doping microcrystalline silicon layer is arranged on the non-doping amorphous silicon layer. Additionally, the ohm contact layer is arranged on partial semiconductor layer, and the source electrode and the drain electrode are arranged on the ohm contact layer. Therefore, the film transistor of the invention has the advantages of better quality control and electric property.

Description

Thin-film transistor

Technical field

The invention relates to a kind of semiconductor element, and particularly relevant for a kind of thin-film transistor (ThinFilm Transistor, TFT).

Background technology

In recent years, because the maturation of photoelectric technology and semiconductor fabrication, driven the flourish of flat-panel screens (FlatPanel Display), Thin Film Transistor-LCD (Thin Film TransistorLiquid Crystal Display wherein, TFT-LCD) the applied film transistor is with the control liquid crystal layer, advantage such as it has that operating voltage is low, reaction speed is fast, in light weight and volume is little, and become the main flow of display product gradually.

Fig. 1 is the generalized section of existing thin-film transistor.Please refer to Fig. 1, this existing thin-film transistor 100 comprises a substrate 110, a grid 120, a gate insulation layer 130, semi-conductor layer 140, an ohmic contact layer 150, one source pole 160 and a drain electrode 170.Wherein, grid 120 is disposed on the substrate 110, and gate insulation layer 130 is disposed on the substrate 110, and cover gate 120.Semiconductor layer 140 is disposed on the gate insulation layer 130, and is positioned at grid 120 tops.Ohmic contact layer 150 is disposed on the part semiconductor layer 140, and source electrode 160 is disposed on the ohmic contact layer 150 with drain electrode 170.When cut-in voltage inputed to grid 120, semiconductor layer 140 just had the characteristic of conduction, but so just conducting between source electrode 160 and the drain electrode 170.In brief, semiconductor layer 140 can be said so and be controlled the key of existing thin-film transistor 100 runnings.

Yet in the existing thin-film transistor 100, semiconductor layer 140 is respectively undoped amorphous silicon and doped amorphous silicon with the material of ohmic contact layer 150.Generally speaking, the etching selectivity of undoped amorphous silicon and doped amorphous silicon is less.Therefore, carry on the back passage etching (Back channel etching, BCE) in the process, the part zone of semiconductor layer 140 may be subjected to etching and produce 180 (as shown in Figure 1) of depression or form irregular surface, and the incomplete situation of etching also may take place the part ohmic contact layer of desiring to remove 150.Thus, the fraction defective of thin-film transistor 100 just significantly improves.

In order to improve the process rate of thin-film transistor 100, the thickness that can increase semiconductor layer 140 is to avoid said circumstances.Yet, semiconductor layer 140 in fact only with 40 nanometers (nm) of gate insulation layer 130 contact-making surfaces within just have the character in conduction electron or hole.Therefore, the more thick meeting of the thickness of semiconductor layer 140 causes the electrically poor more of thin-film transistor 100.In sum, existing thin-film transistor 100 has improved necessity in fact.

Summary of the invention

The present invention provides a kind of thin-film transistor for the problems referred to above that solve the prior art existence, makes yield to improve.

For reaching above-mentioned purpose, the present invention proposes a kind of thin-film transistor, and it comprises substrate, grid, gate insulation layer, semiconductor layer, ohmic contact layer, source electrode and drain electrode.Wherein, gate configuration is on substrate, and gate insulation layer is disposed on the substrate, and cover gate.Semiconductor layer is disposed on the gate insulation layer, and is positioned at the grid top.Semiconductor layer comprises not doped microcrystalline silicon layer (undopedmicrocrystalline silicon layer, undoped μ c-Si layer) of a undoped amorphous silicon layer and one first, wherein first not the doped microcrystalline silicon layer then be disposed on the undoped amorphous silicon layer.In addition, doped microcrystalline silicon is disposed on the part semiconductor layer as ohmic contact layer, and source electrode and drain electrode then are disposed on the ohmic contact layer.

In above-mentioned thin-film transistor of the present invention, above-mentioned first not the thickness of doped microcrystalline silicon layer for example be between the 20-90 nanometer (nanometer, nm) between.Wherein, this first not the thickness of doped microcrystalline silicon layer preferable for example be between the 30-80 nanometer, and better for example be between the 40-70 nanometer.

In above-mentioned thin-film transistor of the present invention, thin-film transistor also comprises the second doped microcrystalline silicon layer not, is disposed between undoped amorphous silicon layer and the gate insulation layer.Wherein, second not the thickness of doped microcrystalline silicon layer for example be between the 5-70 nanometer, preferable for example is between the 5-50 nanometer, and better for example be between the 10-40 nanometer.

In above-mentioned thin-film transistor of the present invention, the material of above-mentioned ohmic contact layer for example is doped amorphous silicon or doped microcrystalline silicon.

The present invention forms the first doped microcrystalline silicon layer not on the undoped amorphous silicon layer, make the undoped amorphous silicon layer be subjected to its protection and be difficult for being damaged in etch process, therefore can improve the process rate of thin-film transistor.In addition, the present invention more can between undoped amorphous silicon layer and gate insulation layer, form second not the doped microcrystalline silicon layer with the electric characteristics of further lifting thin-film transistor.

Description of drawings

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:

Fig. 1 is the generalized section of existing a kind of thin-film transistor.

Fig. 2 A is the generalized section according to the thin-film transistor of one embodiment of the invention.

Fig. 2 B is the generalized section according to the thin-film transistor of another embodiment of the present invention.

Embodiment

Fig. 2 A is the generalized section according to the thin-film transistor of one embodiment of the invention.Please refer to Fig. 2 A, thin-film transistor 200 comprises substrate 210, grid 220, gate insulation layer 230, semiconductor layer 240, ohmic contact layer 250, source electrode 262 and drain electrode 264.Wherein, grid 220 all is disposed on the substrate 210 with gate insulation layer 230, and gate insulation layer 230 cover gate 220.Semiconductor layer 240 is disposed on the gate insulation layer 230, and is positioned at grid 220 tops.Semiconductor layer 240 comprises not doped microcrystalline silicon layer 244 of a undoped amorphous silicon layer 242 and one first, wherein first not 244 of doped microcrystalline silicon layers be disposed on the undoped amorphous silicon layer 242.In addition, ohmic contact layer 250 is disposed at first not on the doped microcrystalline silicon layer 244 of part semiconductor layer 240, and source electrode 262 then is disposed on the ohmic contact layer 250 with drain electrode 264.In the present embodiment, the material of ohmic contact layer 250 for example is doped amorphous silicon or doped microcrystalline silicon.

In the present embodiment, first not the thickness of doped microcrystalline silicon layer 244 for example be between the 20-90 nanometer.Wherein, this first not the thickness of doped microcrystalline silicon layer 244 preferable for example be between the 30-80 nanometer, and better for example be between the 40-70 nanometer.

Since present embodiment with first not doped microcrystalline silicon layer 244 be disposed on the undoped amorphous silicon layer 242, and microcrystal silicon layer has that defect concentration is little, structure is fine and close and have preferable advantages such as anti-etching ability.Therefore, be etched with when removing part ohmic contact layer 250 carrying on the back passage, first not doped microcrystalline silicon layer 244 can protect undoped amorphous silicon layer 242, influence electric characteristics to avoid undoped amorphous silicon layer 242 to be subjected to etch damage.Say further, first not doped microcrystalline silicon layer 244 can improve the making yield of thin-film transistor 200.

First not the production method of doped microcrystalline silicon layer 244 for example be H ₂: SiH ₄Ratio during greater than 20:1, the microcrystal silicon of can successfully growing (Microsrystalline silicon, μ c-Si) film.

Secondly, owing to have the more irregular and more high defective of defect concentration of atomic arrangement by the undoped amorphous silicon layer 242 that amorphous silicon material constituted, therefore when this by undoped amorphous silicon layer 242 that amorphous silicon material constituted when making thin-film transistor 200, in undoped amorphous silicon layer 242, produce the electric characteristics of hanging key (dangling bonds) and influencing thin-film transistor 200 easily.Therefore, the present invention proposes a kind of thin-film transistor 200 ' of sandwich structure in addition, to improve electric characteristics.

Fig. 2 B is the generalized section according to the thin-film transistor of another embodiment of the present invention.Please refer to Fig. 2 B, the thin-film transistor 200 ' of present embodiment is similar to above-mentioned thin-film transistor 200, its difference is: the thin-film transistor 200 ' of present embodiment also comprises the second doped microcrystalline silicon layer 246 not, and it is configured between undoped amorphous silicon layer 242 and the gate insulation layer 230.In addition, second not the production method of doped microcrystalline silicon layer 246 as above-mentioned.

In the present embodiment, second not the thickness of doped microcrystalline silicon layer 246 for example be between the 5-70 nanometer, preferable for example is between the 5-50 nanometer, and better for example be between the 10-40 nanometer.

Owing to the second not comparatively densification of structure of doped microcrystalline silicon layer 246, therefore can increase the mobility (mobility) in thin-film transistor 200 ' middle electronics or hole.In addition, first not doped microcrystalline silicon layer 244 and second the defective of doped microcrystalline silicon layer 246 is not less, so this thin-film transistor 200 ' has lower leakage current (off-current).In brief, thin-film transistor 200 ' has the excellent electrical property characteristic.

In sum, thin-film transistor of the present invention has following advantage at least:

One, first not the doped microcrystalline silicon layer can avoid the undoped amorphous silicon layer when back of the body passage etch process, to be subjected to etching, and improve etch uniformity.

Two, first and second not the doped microcrystalline silicon layer can reduce leakage current to promote its electric characteristics.In other words, thin-film transistor of the present invention has the excellent electrical property characteristic and makes yield higher.

Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when defining with claims.

Claims

1. a thin-film transistor is characterized in that, comprising:

One substrate;

One grid is disposed on the described substrate;

One gate insulation layer is disposed on the described substrate, and covers described grid;

Semi-conductor layer is disposed on the described gate insulation layer, and is positioned at described grid top, and described semiconductor layer comprises:

One undoped amorphous silicon layer;

One first doped microcrystalline silicon layer not is disposed on the described undoped amorphous silicon layer;

One doped microcrystalline silicon is disposed on the described semiconductor layer of part as ohmic contact layer; And

An one source pole and a drain electrode are disposed on the described ohmic contact layer.

2. thin-film transistor as claimed in claim 1 is characterized in that, described first not the thickness of doped microcrystalline silicon layer be between the 20-90 nanometer.

3. thin-film transistor as claimed in claim 2 is characterized in that, described first not the thickness of doped microcrystalline silicon layer be between the 30-80 nanometer.

4. thin-film transistor as claimed in claim 3 is characterized in that, described first not the thickness of doped microcrystalline silicon layer be between the 40-70 nanometer.

5. thin-film transistor as claimed in claim 1 is characterized in that, described semiconductor layer also comprises one second doped microcrystalline silicon layer not, is disposed between described undoped amorphous silicon layer and the described gate insulation layer.

6. thin-film transistor as claimed in claim 5 is characterized in that, described second not the thickness of doped microcrystalline silicon layer be between the 5-70 nanometer.

7. thin-film transistor as claimed in claim 6 is characterized in that, described second not the thickness of doped microcrystalline silicon layer be between the 5-50 nanometer.

8. thin-film transistor as claimed in claim 7 is characterized in that, described second not the thickness of doped microcrystalline silicon layer be between the 10-40 nanometer.