CN101267244A - Timing tracking method - Google Patents

Abstract

The present invention discloses a timing tracking method which is used for correcting the timing drifting generated after synchronization by a digital mobile communication system. The continuous maintaining timing synchronization of the system is guaranteed. The method comprises the procedures of selecting a length of know data a<n> from the frequency domain signal, setting the length as N; executing complex multiplication to the frequency domain data a<n> and the conjugation of the local known frequency spectrum sequence An for obtaining a now sequence bn=a<n>A<*>n; executing low-pass filtering to the sequence bn for obtaining a novel sequence cn; executing zero crossing detection to the sequence cn, to all i=1, 2, ..., N-1, if the relationship cici-1<=0 is satisfied, recording as a zero point, and detecting to obtain a total number x of the zero points; calculating a synchronous offset m=x/2 according to the number of the zero point; and executing synchronous correction according to the synchronous offset obtained from calculation. The timing tracking method has the advantages of small complexity, small calculating amount, simple procedure, little resource requirement, simple structure of the hardware realizing circuit, short calculating time and low power consumption.

Description

Timing tracking method

Technical field

The present invention relates to a kind of method of communication technical field, particularly a kind of timing tracking method of digital mobile communication system.

Background technology

In digital mobile communication system, portable terminal needs to search for and catch synchronous training sequence, the position of specified data frame at the beginning.Because still there is timing wander in the variation that receiving terminal and transmitting terminal sampling clock frequency do not match and propagate multipath after finishing synchronously, need regularly tracing process this moment, continue to keep regularly synchronously to guarantee system.

Timing tracking method of the prior art is to utilize digital phase-locked loop to follow the tracks of or by channel frequency domain response being carried out inverse fast fourier transform (IFFT) to obtain the time domain impulse response.Digital phase-locked loop systematic comparison complexity; The IFFT computation complexity is Nlog ₂N, operand is bigger.Therefore, these method complexities are than higher, and operand is bigger, and the expense of hardware resource is bigger.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of timing tracking method, and its algorithm complex is little, and amount of calculation is little, and resource requirement is few.

For solving the problems of the technologies described above, timing tracking method of the present invention may further comprise the steps:

Step 1, choose the known one piece of data of frequency spectrum in frequency-region signal, establishing its length is N, is designated as a _n, n=0,1 ..., N-1;

Step 2, with frequency domain data a _nWith local known frequency spectrum sequence A _nConjugation do complex multiplication operation, obtain new sequence, $b_n=a_n{A}_N^{*};$

Step 3, to sequence b _nLow-pass filtering obtains new sequence c _n

Step 4, to sequence c _nCarry out zero passage detection, for all i=1,2 ..., N-1 is if satisfy c _ic _I-1≤ 0, just be designated as a zero point, detect the total number x that obtains zero point;

Step 5, calculating simultaneous bias calculate synchronisation offset m, m=x/2 according to the number at zero point;

The synchronisation offset that step 6, basis calculate is carried out synchronous correction.

Timing tracking method of the present invention is done complex multiplication operation with the conjugation of frequency domain data and local known frequency spectrum sequence, to the new sequence low-pass filtering that obtains and carry out zero passage detection, calculate synchronisation offset to carry out synchronous correction according to the number at zero point, only need carry out simple complex multiplication operation and zero passage detection, thereby algorithm complex is little, amount of calculation is little, step is simple, and resource requirement is few, and hardware circuit implementation is simple in structure, computing time is short, consumes low in energy consumption.

Description of drawings

Fig. 1 is a step block diagram of the present invention;

Fig. 2 is the low-pass filter circuit block diagram;

Fig. 3 is regularly the tracking circuit block diagram.

Embodiment

The present invention is further detailed explanation below in conjunction with accompanying drawing.

Suppose that the time-domain signal that receives does not have simultaneous bias, be designated as x (n), it is DFT (Discrete Fourier Transfer, discrete Fourier transform (DFT)), can obtain its corresponding frequency domain signal X (k), promptly $x\left(n\right)\stackrel{\mathrm{DFT}}{\&RightArrow;}X\left(k\right);$ The periodic extension sequence of note x (n) is

Promptly

In the formula ((n)) _NExpression (n mould N), so, when the timing slip of m chip was arranged on time-domain signal, the time-domain signal that receives can be designated as x ((n+m)) _NR _N(n), i.e. the circular shifting of x (n); X in the formula ((n+m)) _NThe periodic extension sequence of expression x (n)

Displacement, promptly $x{\left((n+m)\right)}_N=\tilde{x}(n+m),$ R _N(n) be the rectangle symbol sebolic addressing,

According to DFT character, to x ((n+m)) _NR _N(n) be DFT and can obtain its corresponding frequency-region signal, $x{\left((n+m)\right)}_N{R}_N\left(n\right)\stackrel{\mathrm{DFT}}{\&RightArrow;}{W}_N^{-\mathrm{mk}}X\left(k\right);$ If X (k) is known, with resulting frequency-region signal W _N ^-mkX (k) does complex multiplication operation with the conjugation of known array X (k), can obtain $W_N^{-\mathrm{mk}}X\left(k\right)X^{*}\left(k\right)=W_N^{-\mathrm{mk}}{\left|X\left(k\right)\right|}^2=\cos \left(\frac{2\mathrm{\&pi;mk}}{N}\right){\left|X\left(k\right)\right|}^2+j\sin \left(\frac{2\mathrm{\&pi;mk}}{N}\right){\left|X\left(k\right)\right|}^2,$ This formula is designated as R (k); If in the following formula | X (k) |＞0, then zero point of the real part sequence Re of R (k) (R (k)) or imaginary part Im (R (k)) then by

Perhaps

Decision; 0≤k＜N, so $0\&le;\frac{2\mathrm{\&pi;mk}}{N}<2\mathrm{\&pi;m},$ So in the scope of 0≤k＜N,

Or

Function has m cycle, that is to say, sequence Re (R (k)) or Im (R (k)) have 2m zero point.It should be noted that 2m zero point for

Only some establishment in m ≠ 0, and for When m=0, also set up.As long as obtain the number x at zero point of real part sequence Re (R (k)) or imaginary part sequence Im (R (k)), just can calculate simultaneous bias (chip number) is m=x/2.In multi-path environment, calculating skew chip number by this method is m=x/2, has reflected the most powerful path position, can effectively tackle the environment that has multidiameter fading channel, after obtaining being offset the chip number, and then carry out synchronous correction according to this, guarantee regularly synchronously.

According to above theory analysis, timing tracking method of the present invention as shown in Figure 1:

Step 1, choose the known one piece of data of frequency spectrum in frequency-region signal, establishing its length is N, is designated as a _n, n=0,1 ..., N-1;

Step 2, with frequency domain data a _nWith local known frequency spectrum sequence A _nConjugation do complex multiplication operation, obtain new sequence, $b_n=a_n{A}_N^{*};$

Step 3, to sequence b _nLow-pass filtering obtains new sequence c _n, Filtering Processing can reduce The noise, increases to judge reliability, and the mode that adopts fixed length to add up is usually carried out filtering;

Step 4, to sequence c _nCarry out zero passage detection, for all i=1,2 ..., N-1 is if satisfy c _ic _I-1≤ 0, just be designated as a zero point, detection can obtain the total number x at zero point;

Step 5, calculating simultaneous bias calculate synchronisation offset, m=x/2 according to the number at zero point;

The synchronisation offset that step 6, basis calculate is carried out synchronous correction.

Wherein step 4 can add suitable correction algorithm according to system performance.For example, because noise effect, data sequence is shaken up and down in null value near zero point, will detect the zero point more than actual quantity.By the maximum cheap synchronously amount of system, can calculate minimum range at adjacent zero point, by judging the relation of adjacent two zero distances and minimum range, can remove how detected zero point.

Provide a concrete example below, set forth performing step of the present invention, circuit block diagram as shown in Figure 3.It is pointed out that this example does not influence generality of the present invention.

T-DMB (Terrestrial Digital Multimedia Broadcasting, T-DMB) standard adopts the OFDM modulation.Under pattern I, sub-carrier number is 2048, and effectively sub-carrier number is 1536, system bandwidth 2.048MHz, sub-carrier separation 1kHz.T-DMB system first symbol of every frame is PRS (Phase Reference Symbol, a phase reference symbol) sequence.Remove in the PRS symbol after the virtual subnet carrier wave, obtain length and be 1536 one piece of data, wherein all data are all non-vanishing, meet the algorithm requirement.

The first step is chosen the PRS data and is designated as P in the frequency-region signal that receives _i, i=0,1 ..., 1535;

Second step is with local PRS sequence p _iWith the PRS sequence p that receives _iComputing obtains C _i=P _ip _i ^*, i=0,1 ..., 1535.Because in the PRS sequence, all data are 1 ,-1, j ,-among the j one, therefore in computing, do not have real multiplying, do not need the multiplying unit in the realization, hardware resource is few, algorithm complex is low;

The 3rd step is to Re (C _i) low-pass filtering, employing length is 16 accumulator, obtains $b_i=\underset{j=i}{\overset{i+16}{\mathrm{\&Sigma;}}}{C}_j,$ i＝0，1，...，1520。Because accumulator, resulting sequence length is 1536-15=1521.To calculate simultaneous bias convenient for last, and intercepting length is 1024 one section in resulting sequence, is designated as B _i, i=0,1 ..., 1023.Low-pass filter circuit figure as shown in Figure 2.

The 4th step, zero passage detection.From i=1, investigate B _iB _I-1, each i increases progressively.Work as B _iB _I-1≤ 0 o'clock, with zero point counter add one.In order to eliminate The noise, can preestablish a threshold T, the establishing method of threshold T will be according to the characteristic of system.The synchronisation offset of supposing this system's maximum is M, and the number at the zero point in a symbol mostly is 2M most so.Because between adjacent two zero points is equidistant, thus the minimum spacing between two zero points should for

In the formula

Be floor function, promptly round downwards.Minimum spacing just can be set to threshold value.When detecting a zero point, skip over for T data point after current zero point and not carry out zero passage detection, avoid near the shake zero point to be credited to the number at zero point with this.Promptly after obtaining a zero point, make i=i+T.Use the threshold value method, can effectively solve because near the problem of shaking zero point that noise causes reduces probability of miscarriage of justice.This step obtains counting zero point x.

In the 5th step, calculate simultaneous bias.Because it is 1024 that zero passage detection is investigated sequence length, is half of whole symbol lengths 2048, so zero point, number was 2x in whole symbol.Can calculate simultaneous bias is 2x/2, i.e. x.

In above-mentioned steps, computation complexity is N, and negate computing and symbol is only arranged relatively, and operand is little.

The present invention has the following advantages: circuit realizes that resource is few, area is little, low in energy consumption; Have very High reliability; Can effectively tackle the environment that has multidiameter fading channel; Computational speed is fast.

Claims (4)

1. a timing tracking method is characterized in that, may further comprise the steps:

Step 1, choose the known one piece of data of frequency spectrum in frequency-region signal, establishing its length is N, is designated as a _n, n=0,1 ..., N-1;

Step 2, with frequency domain data a _nWith local known frequency spectrum sequence A _nConjugation do complex multiplication operation, obtain new sequence, $b_n=a_n{A}_N^{*};$

Step 3, to sequence b _nLow-pass filtering obtains new sequence c _n

Step 4, to sequence c _nCarry out zero passage detection, for all i=1,2 ..., N-1 is if satisfy c _ic _I-1≤ 0, just be designated as a zero point, detect the total number x that obtains zero point;

Step 5, calculating simultaneous bias calculate synchronisation offset m, m=x/2 according to the number at zero point;

The synchronisation offset that step 6, basis calculate is carried out synchronous correction.

2. timing tracking method according to claim 1 is characterized in that, the mode that step 3 adopts fixed length to add up is carried out low-pass filtering.

3. timing tracking method according to claim 1 and 2 is characterized in that, step 4 adds correction algorithm according to system performance.

4. timing tracking method according to claim 3 is characterized in that, correction algorithm is, sets a lowest distance value, by judging the relation of adjacent two zero distances and minimum range, removes how detected zero point.

Images