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CN101266957A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN101266957A
CN101266957A CNA2008100837627A CN200810083762A CN101266957A CN 101266957 A CN101266957 A CN 101266957A CN A2008100837627 A CNA2008100837627 A CN A2008100837627A CN 200810083762 A CN200810083762 A CN 200810083762A CN 101266957 A CN101266957 A CN 101266957A
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CN
China
Prior art keywords
layer
metal level
metal
thickness
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2008100837627A
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English (en)
Inventor
宫田拓司
吉田哲哉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
System Solutions Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Sanyo Semiconductor Co Ltd
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Filing date
Publication date
Application filed by Sanyo Electric Co Ltd, Sanyo Semiconductor Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN101266957A publication Critical patent/CN101266957A/zh
Pending legal-status Critical Current

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Abstract

本发明提供一种半导体装置及其制造方法。在无接合线结构的半导体装置中，由于在将作为连接件的金属板与半导体芯片的电极层进行电连接时采用预成型材料，因此，需要在预成型材料与第一电极层的结合部上设置多层金属层。但是，在多层金属层中，会产生电气特性波动、温度循环试验等中的特性变动的问题。在本发明中，作为多层金属层的最下层(与半导体芯片的电极层相接的第一金属层)，利用电子冲击加热蒸镀法形成以钛为主要材料的金属层，其膜厚为1000。由此，与现有的结构相比，本发明的Ti层的膜质良好，可以使多层金属层的电气特性波动、特性变动极小化。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种半导体装置及其制造方法，特别是涉及无接合线结构中使半导体芯片与预成型材料的结合部的可靠性提高的半导体装置及其制造方法。
背景技术
公知有如下的半导体装置，即、作为将半导体芯片的电极向外部导出的连接件、不使用金属细线(接合线)的所谓的无接合线结构的半导体装置(例如参照专利文献1)。
图11表示现有技术的无接合线结构(下面称为无接合线结构)的半导体装置的一例。图11(A)是立体图，图11(B)是图11(A)的b-b线的剖面图，图11(C)是电极部分的剖面放大图。其中，在图11(A)、图11(C)中省略树脂层。
参照图11(A)、图11(B)，半导体芯片201例如是MOSFET(Metal OxideSemiconductor Field Effect Transistor：金属氧化物半导体场效应晶体管)、二极管或双极晶体管等，在此，表示以MOSFET为例的情况。在半导体芯片201的一主面侧通过铝合金等设置表面电极202。引线框220是以铜为原料冲压的框，半导体芯片201通过例如焊料或Ag膏构成的预成型材料204固定在该框的前端板221上。半导体芯片201的其他主面通过衬板金属层形成背面电极205。与前端板221连接的引线225作为漏极端子向外部导出。
在表面电极202上为了降低其与预成型材料(例如焊料)204之间的阻抗、且提高粘接性，设置有Ti-Ni-Cu-Au的多层金属层203，利用预成型材料204固定金属板227。金属板227作为源极端子向外部导出。另外，同样地，在一主面侧，金属板226固定并作为栅极端子向外部导出。
半导体芯片201、引线框220及金属板226、227通过模具及传递模进行树脂封固，树脂层208构成封装外形。
参照图11(C)，多层金属层203形成在表面电极(Al层)202上。多层金属层203是从下层(表面电极202)侧连续堆积钛(Ti)层203a、镍(Ni)层203b、铜(Cu)层203c、金(Au)层203d的结构层。利用电子冲击加热蒸镀法，Ti层203a例如形成膜厚为100
Figure A20081008376200041
，利用电子冲击加热蒸镀法，Ni层203b例如形成膜厚为200
Figure A20081008376200042
，利用阻抗加热蒸镀法，Cu层203c例如形成膜厚为1500
Figure A20081008376200043
，利用阻抗加热蒸镀法，Au层203d例如形成膜厚为625。
专利文献1：(日本)特开2003-229460号公报
在上述的无引线结构的半导体装置中，无论半导体芯片的种类(MOSFET、双极晶体管、二极管、IGBT(Insulated Gate Bipolar Transistor：隔离栅型双极晶体管)等)，电气特性(例如正向电压特性、接通阻抗不良、正向电流)波动、温度循环试验前后的特性变动等故障多有发生。
由试验的结果可知，电气特性的波动起因于作为半导体芯片201与预成型材料204(焊料)的结合部的多层金属层203的阻抗值的波动，另外，特性变动起因于在温度循环试验的前后、多层金属层203的应力的变动。
起因于阻抗值波动的特性波动会引起成品率的下降。另外，起因于应力的特性变动也产生结合强度的下降，而且，也会产生例如正向电压特性等的初期特性的变动，引起可靠性降低的问题。
发明内容
本发明是鉴于上述课题而提出的，第一方面，本发明的半导体装置具有：半导体芯片，其在半导体基板的一主面设置电极层；多层金属层，其设置在所述电极层上；连接件，其由金属板构成，通过预成型材料固定在所述多层金属层上，所述多层金属层依照第一金属层、第二金属层、第三金属层的顺序进行层积，该第一金属层膜厚为400
Figure A20081008376200045
～2000
Figure A20081008376200046
、以钛作为主要材料，该第二金属层膜厚为100
Figure A20081008376200047
～1000
Figure A20081008376200048
、以镍作为主要材料，该第三金属层膜厚为500
Figure A20081008376200049
～2000、由铜或铬构成。
第二方面，本发明的半导体装置的制造方法具有：形成电极层的工序，在作为半导体芯片的半导体基板的第一主面形成电极层；形成第一金属层的工序，利用电子冲击加热蒸镀法，在该电极层上形成膜厚为400
Figure A200810083762000411
～2000
Figure A200810083762000412
的以钛作为主要材料的第一金属层；形成第二金属层的工序，利用电子冲击加热蒸镀法，在该第一金属层上形成膜厚为100
Figure A200810083762000413
～1000
Figure A200810083762000414
的以镍作为主要材料的第二金属层；形成第三金属层的工序，利用阻抗加热蒸镀法，在该第二金属层上形成膜厚为500
Figure A20081008376200051
～2000
Figure A20081008376200052
的以铜或铬构成的第三金属层；形成第四金属层的工序，利用阻抗加热蒸镀法，在该第三金属层上形成膜厚为600
Figure A20081008376200053
～2000
Figure A20081008376200054
的以金或钯或白金构成的第四金属层；形成其他电极层的工序，在所述半导体基板的第二主面形成其他电极层；固定连接件的工序，在所述第四金属层上涂敷预成型材料固定由金属板构成的连接件。
根据本实施方式，第一方面，在无引线结构的半导体装置中，可以实现电气特性波动、温度循环试验等特性变动的极小化，并能提高可靠性。
作为电气特性波动的极小化，例如，在耐压为15V的肖特基势垒二极管的正向电压VF值在2.0A时与现有的结构相比的情况下，波动的标准偏差(σ)的三倍(3σ)降低90％(降低到10％)。即、通过电气特性波动的极小化，可以大幅度地改善成品率。
另外，作为特性变动的极小化，例如在温度循环试验中，没有产生在现有的结构中产生的特性变动，可以大幅度地提高可靠性。
附图说明
图1(A)是说明本发明的实施方式的半导体装置的立体图，图1(B)是其剖面图，图1(C)是其剖面图；
图2是说明本发明的实施方式的半导体装置的主要原因的效果图；
图3是说明本发明的实施方式的半导体装置的特性图；
图4是说明本发明的实施方式的半导体装置的特性图；
图5是说明本发明的实施方式的半导体装置的特性图；
图6(A)～(C)是表示本发明的实施方式的半导体装置的俄歇分析结果的图；
图7是说明本发明的实施方式的半导体装置的制造方法的剖面图；
图8(A)～(D)是说明本发明的实施方式的半导体装置的制造方法的剖面图；
图9是说明本发明的实施方式的半导体装置的制造方法的剖面图；
图10(A)～(B)是说明本发明的实施方式的半导体装置的制造方法的剖面图；
图11(A)是现有的半导体装置的平面图，图11(B)是其剖面图，图11(C)是其剖面图。
附图标记说明
1：半导体芯片
2：肖特基金属层
3：第一电极层
4：绝缘膜
5：抗蚀剂
6：多层金属层
61：第一金属层
62：第二金属层
63：第三金属层
64：第四金属层
7：第二电极层
8、9：预成型材料
10：引线框
101：前端板
102、103：引线
11：n+型硅半导体基板
12：n-型半导体层
13：绝缘膜
15：连接件
16：树脂层
SB：半导体基板
201：半导体芯片
202：表面电极
203：多层金属层
203a：Ti层
203b：Ni层
203c：Cu层
203d：Au层
204：预成型材料
208：树脂层
220：引线框
226、227：金属板
具体实施方式
参照图1～图10，在本发明的半导体装置中，以肖特基势垒二极管(Schottky barrier diode，下面称为SBD)为例进行说明。
图1是表示半导体装置100的一例的图，图1(A)是立体图，图1(B)是a-a线的剖面图，图1(C)是电极部分的剖面放大图。另外，图1(A)、图1(C)中省略树脂层。
本发明的半导体装置100由半导体芯片1、多层金属层6、预成型材料8、连接件15构成。
参照图1(A)及图1(B)，半导体芯片1为例如在n+型半导体基板上层积n-型半导体层、设置有与该n-型半导体层表面形成肖特基结合的肖特基金属层(例如为钛Ti或钼Mo等)的SBD。
在半导体基板的一主面侧设置有第一电极层3。第一电极层3是在肖特基金属层(在此未图示)上设置的阳极电极。第一电极层3例如是膜厚为2～3μm左右的铝(Al)层或者含有硅(Si)的铝层。
另外，通过金属蒸镀在半导体基板的其他主面设置第二电极(衬板电极)层7。第二电极层7例如为Ti-镍(Ni)-金(Au)层(各自厚度为500
Figure A20081008376200071
-5000
Figure A20081008376200072
-500
Figure A20081008376200073
)，在此作为阴极电极。
在第一电极层3上例如设置氮化膜等绝缘膜4，并在绝缘膜4的所希望位置开口。从绝缘膜4的开口部露出的第一电极层3作为焊盘部P。
多层金属层6设置在第一电极层3的焊盘部P上，从下层(第一电极层3侧)由以Ti为主要材料的第一金属层61、以Ni为主要材料的第二金属层62、由铜(Cu)或铬(Cr)构成的第三金属层63、由金(Au)或钯(Pd)或白金(Pt)构成的第四金属层64构成。
半导体芯片1安装在支承基板10上。支承基板例如为引线框10。引线框10是具有阴极端子102、阳极端子103的以铜作为原料的冲压框，通过由焊料或Ag膏构成的预成型材料9，将SBD的半导体芯片(裸芯片)1固定在该框的前端板101上。由此，将SBD的第二电极层7与阴极端子102电连接。
参照图1(B)及图1(C)，在多层金属层6(第四金属层64)表面涂敷预成型材料8，并固定由例如Cu的金属板等构成的连接件15。
预成型材料8是焊料(铅(Pb)/锡(Sn)层)或者无铅焊料(例如银Ag/Sn层、Ag/Cu层、Ag/Au层)。
连接件15连接作为阳极端子的引线框103，并将第一电极层(阳极电极)3与阳极端子103电连接。另外，也可以在该状态下将连接件15一直延伸，作为阳极端子向外部导出。
SBD的半导体芯片1、引线框10及连接件15通过模具及传递模进行树脂封固，树脂层16构成封装外形。
这样，在半导体芯片1与引线框10的连接不使用接合线而通过连接件15等的金属板实现电连接的无引线结构的半导体装置100中，由于接合线自身的阻抗不加入到半导体芯片的阻抗上，因此，不影响元件的特性，可以实现损失少的半导体装置。
但是，在将连接件15与第一电极层3连接时，需要使用焊料等预成型材料8。另外，为了确保预成型材料8与第一电极层3的结合性，防止侵蚀，需要在第一电极层3上配置由所希望的金属构成的多层金属层6。
参照图1(C)，对本实施方式的多层金属层进行详细叙述。
为了保持与作为第一电极层3的Al层的粘接性良好，多层金属层6中，作为最下层(第一电极层3侧)的第一金属层61设置有以Ti为主要材料的金属层。以Ti为主要材料的金属层为Ti(纯Ti)层或含有硼(B)的Ti层。第一金属层61通过电子冲击加热蒸镀法形成，膜厚为400
Figure A20081008376200081
～2000
Figure A20081008376200082
(例如为1000)。
本实施方式的第一金属层61采用现有结构中的第一金属层203a(参照图11)的大约10倍的膜厚。通过将膜厚加厚，可以使第一金属层61的成膜状态良好。因此，可以降低半导体芯片1的作为第一电极层3与预成型材料8的结合部的多层金属层6的阻抗值波动，能使半导体装置100的电气特性的波动极小化。
另外，通过加厚形成第一金属层61，也可以缓和多层金属层61中的应力，例如可以使半导体装置100的温度循环试验前后的特性(例如正向电压特性)变动极小化，从而能提高可靠性。
在第一金属层61上，作为第二金属层62，考虑到防止预成型材料8的侵入(侵蚀)、以及与预成型材料8的结合性，设置有以Ni为主要材料的金属层。该金属层为Ni(纯Ni)层或含有磷(P)的Ni层或含有B的Ni层。第二金属层62通过电子冲击加热蒸镀法形成，膜厚为100
Figure A20081008376200091
～1000
Figure A20081008376200092
(例如为200
Figure A20081008376200093
)。
在第二金属层62上，考虑到抑制预成型材料8的扩展、防止预成型材料8的侵入以及结合性等，作为第三金属层63，设置Cu层或Cr层。第三金属层63通过阻抗加热蒸镀法形成，膜厚为500
Figure A20081008376200094
～2000
Figure A20081008376200095
(例如为1500)。
在第三金属层63上，作为第四金属层64，设置有与预成型材料8的润湿性、结合性良好并防止第三金属层63氧化的金属层。第四金属层64是通过阻抗加热蒸镀法形成的Au层或Pd层或Pt层，膜厚为600
Figure A20081008376200097
～2000
Figure A20081008376200098
(例如为1000
Figure A20081008376200099
)。
在本实施方式中，从所述第一金属层61到第四金属层64的膜厚是通过将各个金属层作为要素，并进行使用以各要素的厚度为基准值的L9正交表(田口方法)的实验，对选择的最适当值确认再现性而进行决定，下面对其进行说明。
首先，在图2中，表示使用用于选择本实施方式的多层金属层6的膜厚的田口方法的实验结果。
图2是对于多层金属层6的阻抗值使用3基准系统(L9)正交表进行实验的情况下的阻抗的主要原因的效果图，纵轴为阻抗的SN比[dB]，横轴为第一金属层61～第四金属层64的膜厚。另外，多层金属层6的阻抗值为第一金属层61～第四金属层64的层积方向的阻抗值。
在该情况下，优选SN比接近0dB。另外，根据图2，第一金属层(Ti层)61的主要原因的效果量(变化量)与其他膜相比显著。根据图2可知，在本实施方式的多层金属层6的结构中，特别是使第一金属层(Ti层)61的膜厚增厚，有助于多层金属层6的阻抗值波动的极小化。
于是，在本实施方式中，第一金属层61的膜厚比现有的结构(100
Figure A200810083762000910
)厚，为400
Figure A200810083762000911
～2000(例如为1000
Figure A200810083762000913
)。并采用第二金属层(Ni层)62的膜厚为100～1000
Figure A200810083762000915
(例如为200
Figure A200810083762000916
)、第三金属层(Cu层)63的膜厚为500
Figure A200810083762000917
～2000(例如为1500
Figure A200810083762000919
)、第四金属层(Au层)64的膜厚为600～2000
Figure A200810083762000921
(例如为1000
Figure A200810083762000922
)。
接着，对验证各金属层膜厚的再现性的结果进行说明。
图3是表示第一金属层(Ti层)61的膜厚与多层金属层6的层积方向的阻抗值的关系的图。
在图3中，表示对于第一金属层(Ti层)61的膜厚为不同的多个多层金属层6(横轴)测定的阻抗值Ω(纵轴)的结果。对于第一金属层(Ti层)，将与现有技术为相等厚度的100
Figure A20081008376200101
和厚度为其10倍的1000
Figure A20081008376200102
膜厚进行比较。由此可知，一般情况下，当金属膜的层积方向的膜厚变厚，就有阻抗值增加的趋势，但是，第一金属层(Ti层)61的膜厚为1000
Figure A20081008376200103
与膜厚为100
Figure A20081008376200104
的情况相比阻抗值本身降低。
可以认为，这是由于Ti层将Al层的自然氧化膜吸收，在第一金属层(Ti层)61的膜厚为1000
Figure A20081008376200105
的情况下，与100
Figure A20081008376200106
的情况相比，可以充分减少下层的第一电极层(Al层)“表面”的自然氧化膜(10
Figure A20081008376200107
～50
Figure A20081008376200108
左右)，使其与上层的第二金属层(Ni层)62充分反应。
图4是表示第一金属层(Ti层)61的厚度与温度循环试验的前后的正向电压特性关系的图。是对与具有第一金属层(Ti层)61的膜厚为不同的多层金属层6的多个晶片(横轴)，在2.0A时测定的正向电压VF值的结果。晶片a、晶片b各自的第一金属层61的膜厚为100
Figure A20081008376200109
，晶片c、晶片d各自的第一金属层61的膜厚为1000
Figure A200810083762001010
。
另外，虚线为温度循环试验前的正向电压VF值，实线为温度循环试验后的正向电压VF值。温度循环试验在环境温度Ta＝-55℃～125℃时进行50次循环。另外，正向电压VF值是对于图1所示的半导体装置100测定的结果。
由此可知，在第一金属层(Ti层)61的膜厚为100
Figure A200810083762001011
(晶片a、b)的情况下，温度循环试验的前后正向电压VF值变动大，对此，在第一金属层61的膜厚为1000
Figure A200810083762001012
(晶片c、d)的情况下，温度循环试验的前后正向电压VF值几乎没有变动。
温度循环试验中没有特性变动意味着对于热应力的强度大，能提高多层金属层6(及第一电极层3)部分的可靠性。
在该情况下，对于第二金属层(Ni层)62、第三金属层(Cu层)63、第四金属层(Au层)64，其各自的膜厚分别为200、1500
Figure A200810083762001014
、1000
Figure A200810083762001015
，在多层金属层6(晶片a～d)间为相同的条件。即、仅仅通过使第一金属层(Ti层)61增厚(膜厚为1000
Figure A200810083762001016
左右)，就可能使温度循环试验的特性变动极小化，可以实现在多层金属层6及第一电极层3部分的应力缓和。
接着，参照图5，对第一金属层(Ti层)61的膜厚与正向电压的波动的关系进行说明。
图5是对于第一金属层(Ti层)61的膜厚为不同的多个多层金属层6(横轴)而求出作为正向电压波动3σ(标准偏差σ的3倍)的结果。晶片a～晶片d与图4的情况相同。
由此，第一金属层(Ti层)61的膜厚为100
Figure A20081008376200111
(例如晶片b)的情况下，正向电压的3σ为0.071，对此，第一金属层61的膜厚为1000
Figure A20081008376200112
(晶片c、d)的情况下，正向电压的3σ为0.006，3σ降低90％(降低到10％)。
在该情况下，对于第二金属层(Ni层)62、第三金属层(Cu层)63、第四金属层(Au层)64，在多层金属层6(晶片a～d)间为相同的条件。即、仅仅通过使第一金属层(Ti层)61增厚(膜厚为1000
Figure A20081008376200113
左右)，就可能使正向电压的波动(3σ)大幅度地降低90％。
接着，对第四金属层(Au层)64的膜厚进行说明。根据图2的主要原因的效果图，优选第四金属层(Au层)64的膜厚也为厚的金属层，在本实施方式中采用600
Figure A20081008376200114
～2000
Figure A20081008376200115
(例如1000)。
图6是表示对于具有第一金属层61～第四金属层64的结构各自不同的多层金属层6的晶片e、f、g、通过俄歇电子分光分析装置分析多层金属层6(俄歇分析)的结果。
图6(A)是对第四金属层(Au层)64的膜厚为200
Figure A20081008376200117
的晶片e的分析结果，图6(B)是对第四金属层(Au层)64的膜厚为500
Figure A20081008376200118
的晶片f的分析结果，图6(C)是对第四金属层(Au层)64的膜厚为1000
Figure A20081008376200119
的晶片g的分析结果。
另外，各个晶片是在一主面形成多层金属层6之后，在其他主面设置第二电极(衬板电极)层7的状态下进行测定。另外，安装从各个晶片抽出的半导体芯片并对正向电压进行测定，一并表示所求出的其波动(3σ)的结果。
另外，虽然这些晶片e、f、g的第一金属层61～第三金属层63的结构(厚度)分别不同，但是，这里是对晶片状态下作为最表面的第四金属层64进行的探讨，由下层的金属层的膜厚的不同引起的影响小。
俄歇电子分光法是在试料表面照射电子射线时、根据自试料表面释放的元素固有电子(俄歇电子)而了解构成元素的极表面的元素分析法，在各图中，纵轴表示各金属层的元素的释放量(强度)，横轴是溅射时间。即、在溅射时间为零的位置表示各晶片(多层金属层6)的最表面的构成元素的存在，并表示随着溅射时间的经过，出现下层的构成元素的情况。
参照图6(A)可知，在第四金属层64为薄(200
Figure A20081008376200121
)的情况下，在分析初始(即、最表面的)第三金属层63的Cu检出量最多，在溅射时间为5分钟以下的最表面附近，应该为最表面的第四金属层(Au层)64的检出量非常少。
这表示通过第二电极(衬板电极)层形成时的辐射热量、多层金属层6中的第三金属层63的Cu在最表面扩散。即、第四金属层(Au层)64为薄的情况下，其下层的第三金属层(Cu层)63扩散，其结果，正向电压波动(3σ)为0.141。
另外，Cu向最表面的扩散会在安装半导体芯片时，产生预成型材料(焊料)的润湿性恶化、应力集中的问题。
图6(B)是第四金属层64比图6(A)厚、为500的情况。在该情况下，在最表面附近(溅射时间为2分以下)，第四金属层(Au层)64与第三金属层(Cu层)63的检出量相同。
即使第四金属层64为500
Figure A20081008376200123
，也能看见第三金属层63的扩散。其结果，正向电压波动(3σ)虽比图6(A)小，但也为0.033。
图6(C)是第四金属层64为1000
Figure A20081008376200124
的情况。在该情况下，在最表面附近(溅射时间为5分以下)，第四金属层(Au层)64的检出量最多，其后，第三金属层(Cu层)63的检出量变多。
即、在该情况下，在最表面第三金属层63的Cu的扩散量可以说几乎没有，其结果，正向电压波动(3σ)也为0.003，变得非常小。
另外，由于可以抑制Cu层向最表面的扩散，因此，在安装半导体芯片时可以避免由于预成型材料(焊料)的润湿性的恶化而导致的应力集中。
即、第四金属层(Au层)64优选为600
Figure A20081008376200125
以上，最优选为1000
Figure A20081008376200126
左右。
在此，通过增厚第四金属层64，预测到可以抑制Cu的扩散，降低正向电压波动。但是，如上所述，作为正向电压波动，膜厚为1000左右就足够，当将Au层过度增厚到需要以上，成本也就增加。因此，本实施方式的第四金属层64的膜厚只要为600
Figure A20081008376200128
以上(优选为1000
Figure A20081008376200129
)就可以，当膜厚为1000以上的情况，考虑到成本等，例如适当选择膜厚为2000
Figure A20081008376200132
等。
这样，通过将第一金属层61及第四金属层64的膜厚增厚，可以将阻抗值波动极小化，并降低正向电压波动。
再次参照图4，对作为层积第一金属层61～第四金属层64的多层金属层6的特性进行说明。
在图4中，晶片c与晶片d具有作为本实施方式的一例的多层金属层6。即、第一金属层(Ti层)61的膜厚为1000
Figure A20081008376200133
，第二金属层(Ni层)62的膜厚为200
Figure A20081008376200134
、第三金属层(Cu层)63的膜厚为1500
Figure A20081008376200135
、第四金属层(Au层)64的膜厚为1000
Figure A20081008376200136
。
即、本实施方式的多层金属层6在温度循环试验前后的正向电压VF值几乎没有波动。
因此，由于可以缓和多层金属层6(及第一电极层3)的应力，因此，可以说连接件15与多层金属层6之间的应力也为稳定的条件。
参照图7～图10，对本发明的半导体装置100的制造方法进行说明。
本发明的半导体装置的制造方法由以下的工序构成，即、形成电极层的工序，在作为半导体芯片的半导体基板的第一主面形成电极层；形成第一金属层的工序，利用电子冲击加热蒸镀法，在该电极层上形成膜厚为400
Figure A20081008376200137
～2000
Figure A20081008376200138
的以钛作为主要材料的第一金属层；形成第二金属层的工序，利用电子冲击加热蒸镀法，在该第一金属层上形成膜厚为100
Figure A20081008376200139
～1000
Figure A200810083762001310
的以镍作为主要材料的第二金属层；形成第三金属层的工序，利用阻抗加热蒸镀法，在该第二金属层上形成膜厚为500
Figure A200810083762001311
～2000
Figure A200810083762001312
的以铜或铬构成的第三金属层；形成第四金属层的工序，利用阻抗加热蒸镀法，在该第三金属层上形成膜厚为600
Figure A200810083762001313
～2000
Figure A200810083762001314
的以金或钯或白金构成的第四金属层；形成其他电极层的工序，在所述半导体基板的第二主面形成其他电极层；固定连接件的工序，在所述第四金属层上涂敷预成型材料固定由金属板构成的连接件。
第一工序(图7)：在作为半导体芯片的半导体基板的第一主面形成电极层的工序。
首先，准备作为半导体芯片的半导体基板SB。半导体基板SB例如是在n+型硅半导体基板11上层积n-型半导体层12的结构。在半导体基板SB的第一主面设置绝缘膜13，经由绝缘膜13的开口部设置与n-型半导体层12表面形成肖特基结合的肖特基金属层2(例如钛Ti、钼Mo等)。
接着，在肖特基金属层2上设置与其连接的第一电极层3。第一电极层3例如为通过溅射法形成的例如铝(Al层)，作为一例其膜厚为2.5μm。
第二工序(图8(A))：利用电子冲击加热蒸镀法，在电极层上形成膜厚为400
Figure A20081008376200141
～2000
Figure A20081008376200142
的以钛作为主要材料的第一金属层的工序。
在图8中，表示第一电极层3局部的放大剖面图。
考虑到Al层的耐氧化性、耐湿性等，在第一电极层3上形成绝缘膜4。绝缘膜4例如为氮化膜，通过800℃、2小时左右的CVD法，堆积成膜厚为6000
Figure A20081008376200143
～8000
Figure A20081008376200144
左右。然后，在绝缘膜4上设置抗蚀剂5，在所希望的位置开口。进而利用光刻技术，将抗蚀剂5作为掩膜，去除绝缘膜4的一部分。在绝缘膜4的开口部露出的第一电极层3在后续的工序中成为与连接件(金属板)电连接的焊盘部P。
于是，在焊盘部P上形成构成多层金属层的第一金属层61。即、利用电子冲击加热蒸镀法，保持抗蚀剂5不变，在整个面上形成以钛作为主要材料的第一金属层61。考虑到与Al层的粘接性等，第一金属层61采用钛(Ti(纯Ti))或含有硼(B)的Ti。第一金属层61的膜厚为400
Figure A20081008376200145
～2000
Figure A20081008376200146
，例如为1000
Figure A20081008376200147
。
另外，与现有的结构相比，通过使用10倍左右的较厚的膜厚，可以使第一金属层61的膜质良好。因此，可以避免作为预成型材料与第一电极层3的结合部的多层金属层的电气特性波动、温度循环试验等特性变动。
第三工序(图8(B))：利用电子冲击加热蒸镀法，在第一金属层上形成膜厚为100
Figure A20081008376200148
～1000
Figure A20081008376200149
的以镍作为主要材料的第二金属层的工序。
抗蚀剂5保持不变，考虑到提高与后续的工序中被涂敷的预成型材料的结合性及防止预成型材料的侵入(侵蚀)，在第一金属层61上形成第二金属层62。
第二金属层62是镍(Ni(纯Ni))层、含有磷(P)的Ni层或含有硼(B)的Ni层，利用电子冲击加热蒸镀法，堆积成膜厚为100
Figure A200810083762001410
～1000
Figure A200810083762001411
(例如200
Figure A200810083762001412
)。
第四工序(图8(C))：利用阻抗加热蒸镀法，在第二金属层上形成膜厚为500
Figure A200810083762001413
～2000
Figure A200810083762001414
的由铜或铬构成的第三金属层的工序。
考虑到抑制预成型材料的扩展、防止由预成型材料引起的侵蚀或提高与预成型材料的结合性等，在第二金属层62上堆积第三金属层63。第三金属层63是铜(Cu)层、或铬(Cr)层，利用阻抗加热蒸镀法，堆积成膜厚为500
Figure A20081008376200151
～2000
Figure A20081008376200152
(例如1500
Figure A20081008376200153
)。
通过将比作为第二金属层62的Ni层的润湿性差、容易被预成型材料(特别是焊料)侵蚀的Cu层的膜厚设置成膜厚比较厚，可以将由预成型材料导致的侵蚀控制为仅仅在Cu层的表面附近，可以使预成型材料对第二金属层62的影响变小。
第五工序(图8(D))：利用阻抗加热蒸镀法，在第三金属层上形成膜厚为600
Figure A20081008376200154
～2000
Figure A20081008376200155
的由金或钯(Pd)或白金(Pt)构成的第四金属层的工序。
考虑到与预成型材料的润湿性、防止第三金属层63的氧化等，在第三金属层63上堆积第四金属层64。第四金属层64是金(Au)层、钯(Pd)层或白金(Pt)层。另外，利用阻抗加热蒸镀法，堆积成膜厚600
Figure A20081008376200156
～2000(例如1000
Figure A20081008376200158
)。
通过使第四金属层64形成为比较厚的膜厚，可以抑制在后续工序(衬板工序)中由于温度上升(辐射热量)而引起第三金属层(Cu层)63扩散到最表面。由此，可以避免安装半导体芯片时由于预成型材料(焊料)的润湿性的恶化引起的应力集中。
然后，通过剥离，将抗蚀剂5及抗蚀剂5上的第一金属层61到第四金属层64同时除去，在第一电极层3的焊盘部P上形成多层金属层6。
第六工序(图9)：在半导体基板的第二主面形成其他电极层的工序。
图9是半导体芯片1省略肖特基金属层的大致的剖面图。
在半导体基板的第二主面形成第二电极(衬板电极)层7。第二电极层7在此为SBD的阴极电极。
第二电极层7首先利用电子中击加热蒸镀法分别蒸镀膜厚例如为500、5000
Figure A200810083762001510
的Ti层、Ni层，然后，利用阻抗加热蒸镀法蒸镀膜厚例如为500
Figure A200810083762001511
的Au层而形成。
利用这时的辐射热量，多层金属层6(第三金属层63)中的Cu层有时有扩散的情况。但是，在本实施方式中，由于第四金属层64(Au层)的厚度比较厚，因此，可以防止Cu扩散到第四金属层64(多层金属层6)的表面。
第七工序(图10)：在第四金属层上涂敷预成型材料固定由金属板构成的连接件的工序。
参照图10(A)，半导体基板通过切割被分割成各个半导体芯片1，半导体芯片1安装在支承基板(例如引线框)10的前端板101上。第二电极层7与前端板101通过预成型材料9固定，连接前端板的引线102作为阴极端子向外部导出。
另外，参照图10(B)，在多层金属层6的表面涂敷预成型材料8(例如铅pb/锡Sn层、银Ag/Sn层、Ag/Cu层、Ag/Au层等)，并固定由金属板构成的连接件15。连接件15与作为阳极端子的引线103连接向外部导出。
另外，也可以将连接件15的端部一直延伸作为阳极端子。
然后，半导体芯片1、连接件15及引线框10通过模具及经由树脂注入的传递模被一体地封固。树脂层构成封装外形，得到图1(B)所示的最终结构。
另外，在本实施方式中，作为一例对SBD半导体芯片1进行了说明，但是，并不限于此，半导体芯片1只要是MOSFET、pn结二极管、双极晶体管、IGBT等无接合线结构的半导体装置，都同样能够实施。

Claims (6)

1.一种半导体装置，其特征在于，具有：
半导体芯片，其在半导体基板的一主面设置有电极层；
多层金属层，其设置在所述电极层上；
连接件，其由金属板构成，通过预成型材料固定在所述多层金属层上，
所述多层金属层依照第一金属层、第二金属层、第三金属层的顺序进行层积，该第一金属层膜厚为400
Figure A20081008376200021
～2000、以钛作为主要材料，该第二金属层膜厚为100
Figure A20081008376200023
～1000
Figure A20081008376200024
、以镍作为主要材料，该第三金属层膜厚为500
Figure A20081008376200025
～2000、由铜或铬构成。
2.如权利要求1所述的半导体装置，其特征在于，所述电极层是铝层或者含有硅的铝层。
3.如权利要求1所述的半导体装置，其特征在于，所述第一金属层是钛或者含有硼的钛。
4.如权利要求1所述的半导体装置，其特征在于，所述第二金属层是镍、含有磷的镍或含有硼的镍中的任意一种。
5.如权利要求1所述的半导体装置，其特征在于，具有由金、钯或白金的任意一种构成的第四金属层。
6.一种半导体装置的制造方法，其特征在于，具有：
形成电极层的工序，在作为半导体芯片的半导体基板的第一主面形成电极层；
形成第一金属层的工序，利用电子冲击加热蒸镀法，在该电极层上形成膜厚为400
Figure A20081008376200027
～2000
Figure A20081008376200028
的以钛作为主要材料的第一金属层；
形成第二金属层的工序，利用电子冲击加热蒸镀法，在该第一金属层上形成膜厚为100
Figure A20081008376200029
～1000的以镍作为主要材料的第二金属层；
形成第三金属层的工序，利用阻抗加热蒸镀法，在该第二金属层上形成膜厚为500
Figure A200810083762000211
～2000
Figure A200810083762000212
的以铜或铬构成的第三金属层；
形成第四金属层的工序，利用阻抗加热蒸镀法，在该第三金属层上形成膜厚为600
Figure A200810083762000213
～2000
Figure A200810083762000214
的以金或钯或白金构成的第四金属层；
形成其他电极层的工序，在所述半导体基板的第二主面形成其他电极层；
固定连接件的工序，在所述第四金属层上涂敷预成型材料固定由金属板构成的连接件。
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